code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Dflip_flop_tb;
reg D, clk, r, s;
wire Q, notQ;
initial
fork
D <= 0;
clk <= 0;
repeat (5) #77 D <= ~D;
repeat (25) #20 clk <= ~clk;
join
initial begin
r <= 1;
#115 r <= ~r;
#15 r <= ~r;
end
initial begin
s <= 1;
#190 s <= ~s;
#15 s <= ~s;
end
Dflip_... | 6.531767 |
module dflop (
input in1,
input clk,
output out
);
reg out;
always @(posedge clk) begin
out <= in1;
end
endmodule
| 6.973832 |
module n_reg (
D,
Clk,
resetn,
Q
);
parameter n = 3; //define inputs and outputs
input [n-1:0] D;
input Clk, resetn;
output reg [n-1:0] Q;
always @(negedge resetn, posedge Clk) //on positive clock or when reset goes low
if (!resetn)
//if reset goes low
Q <= 0; //register ba... | 8.283153 |
module dflop (
input rst,
input clk,
input din,
output qout,
output qbout
);
/* write your code here */
/* write your code here */
endmodule
| 6.973832 |
module: dflow.v *
* *
* *
* *
* Cop... | 7.741739 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module dFPU (
input wire clk,
input wire rstn,
input wire [3:0] f_ope_data,
input wire [31:0] f_in1_data,
input wire [31:0] f_in2_data,
output reg f_in_rdy,
input wire f_in_vld,
output wire [31:0] f_out_data,
input wire f_out_rdy,
output reg f_out_vld,
output wire [2:0] f_e... | 7.707628 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module dfsinst (
CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
LOCKED_OUT
);
input CLKIN_IN;
input RST_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output LOCKED_OUT;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
B... | 6.695103 |
module DFT2_1_block4 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.805817 |
module DFT2_1_block5 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.58056 |
module DFT2_1_block7 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.75803 |
module DFT2_1_block8 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.878796 |
module DFT2_2_block (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input ... | 6.546174 |
module DFT2_2_block1 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.657064 |
module DFT2_2_block2 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.608236 |
module DFT2_2_block4 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.745861 |
module DFT2_2_block5 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.829508 |
module DFT2_2_block7 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.813007 |
module DFT2_2_block8 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_re; // sfix37_En22
input... | 6.852891 |
module DFT2_column_3 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_r... | 6.631788 |
module DFT2_column_3_block (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0]... | 6.631788 |
module DFT2_column_4 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_r... | 6.997217 |
module DFT2_column_4_block (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0]... | 6.997217 |
module DFT2_column_5 (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0] in2_r... | 6.692498 |
module DFT2_column_5_block (
clk,
reset_x,
enb,
in1_re,
in1_im,
in2_re,
in2_im,
out1_re,
out1_im,
out2_re,
out2_im
);
input clk;
input reset_x;
input enb;
input signed [36:0] in1_re; // sfix37_En22
input signed [36:0] in1_im; // sfix37_En22
input signed [36:0]... | 6.692498 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module dft_addsub #(
parameter DATA_W = 32,
parameter DATA_SIGNED = "off", // "on" / "off"
parameter OUTPUT_REG = "on", // "on" / "off"
parameter PIPELINE_STAGES = 0
) (
// System
input wire clk, // System clock
input wire rst, // Syst... | 6.99909 |
module dft_dline #(
parameter STAGES_N = 1, // 0 ... inf
parameter DATA_W = 1
) (
input wire clk, // System clock
input wire rst, // System reset
input wire [DATA_W-1:0] din, // Delay line input
output wire [DATA_W-1:0] dout // Delay line output
);
generate
begin : dline_genblk
... | 8.064857 |
module dft_fifo #(
parameter ADDR_W = 8, // Memory depth
parameter DATA_W = 12 // Data width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Write interface
input wire [DATA_W-1:0] wdata, // Write data
input wire ... | 7.39489 |
module dft_freq_ram #(
parameter ADDR_W = 2, // Memory depth
parameter DATA_W = 16 // Data width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Write interface
input wire [DATA_W-1:0] wdata_re, // Write data real p... | 7.194783 |
module dft_mul #(
parameter DATA_A_W = 16,
parameter DATA_B_W = 16,
parameter DATA_A_SIGNED = "on", // "on" / "off"
parameter DATA_B_SIGNED = "on", // "on" / "off"
parameter INPUT_REG = "off", // "on" / "off"
parameter OUTPUT_REG = "on" // "on" / "off"
) (
// System
... | 6.510218 |
module dft_postproc #(
parameter DATA_W = 16 // Data width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Input data from FIFO
input wire signed [DATA_W-1:0] data_re_in, // Data real part
input wi... | 6.630233 |
module dft_preproc #(
parameter DATA_W = 12 // Data width
) (
// System
input wire clk, // System clock
input wire rst, // System reset
// Input data
input wire signed [DATA_W-1:0] data_in, // Data input
input wire ... | 7.118958 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is ... | 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of me... | 7.680291 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module nextReg (
X,
Y,
reset,
clk
);
parameter depth = 2, logDepth = 1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @(posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0... | 6.59955 |
module swNet77550 (
itr,
clk,
ct
, x0,
y0
, x1,
y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t... | 6.687731 |
module D18_77723 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synt... | 6.758894 |
module D20_77731 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synt... | 7.0617 |
module codeBlock77555 (
clk,
reset,
next_in,
next_out,
i5_in,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in, X1_in, X2_in, X3_in;
reg [15:0] X0,... | 6.77364 |
module rc77818 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.624559 |
module swNet77816 (
itr,
clk,
ct
, x0,
y0
, x1,
y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t... | 6.793153 |
module D14_77993 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;... | 7.160394 |
module D16_78005 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;... | 6.911844 |
module rc78092 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.697344 |
module D12_78295 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'he782;
2: out3 <= 16'hd2bf;
3: out3 <= 16'hc4df;... | 6.836535 |
module codeBlock78095 (
clk,
reset,
next_in,
next_out,
i3_in,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in, X1_in, X2_in, X3_in;
reg [15:0] X0,... | 6.560602 |
module rc78382 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 7.186807 |
module D6_78581 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h353... | 7.198709 |
module D8_78617 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf384;
2: out3 <= 16'he782;
3: out3 <= 16'hdc72;
... | 6.971922 |
module codeBlock78385 (
clk,
reset,
next_in,
next_out,
i2_in,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in, X1_in, X2_in, X3_in;
reg [15:0] X0,... | 6.651457 |
module rc78704 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.555726 |
module D2_78934 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3... | 6.750416 |
module D4_79002 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf9ba;
2: out3 <= 16'hf384;
3: out3 <= 16'hed6c;
... | 6.834708 |
module codeBlock78706 (
clk,
reset,
next_in,
next_out,
i1_in,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in, X1_in, X2_in, X3_in;
reg [15:0] X0,... | 6.524264 |
module multfix (
clk,
rst,
a,
b,
q_sc,
q_unsc
);
parameter WIDTH = 35, CYCLES = 6;
input signed [WIDTH-1:0] a, b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q [CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer ... | 7.660857 |
module addfxp (
a,
b,
q,
clk
);
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a + b;
for (i = 1; i < ... | 6.519538 |
module dfu_helper_tb;
// Signals
// -------
reg clk = 1'b0;
reg rst = 1'b1;
reg btn = 1'b0;
// Setup recording
// ---------------
initial begin
$dumpfile("dfu_helper_tb.vcd");
$dumpvars(0, dfu_helper_tb);
#2000000 $finish;
end
always #10 clk <= !clk;
initial begin
#200 rst =... | 7.66707 |
module dfu_reset #(
parameter integer L = 24 // Bigger L = more time to press button
) (
input wire clk,
input wire nbtn, // active low (default uBtn on ECP5-Mini)
output wire programn // active low
);
// Debounce button
wire db, rise, fall;
debounce #(
.D(16),
.L(8)
) rst_d... | 7.460913 |
module DF_lab2 (
Oand,
Onot,
Oor,
I1,
I2
);
input I1, I2;
output Oand, Oor, Onot;
assign Onot = !I1;
assign Oand = I1 && I2;
assign Oor = I1 || I2;
endmodule
| 6.751297 |
module absolute (
a,
b,
out
);
input [7:0] a, b;
output [7:0] out;
assign out = (a > b) ? (a - b) : (b - a);
endmodule
| 7.309123 |
module dgt_decode (
output reg [3:0] dgt,
input [1:0] state
);
always @(state)
case (state)
0: dgt <= 4'b1110;
1: dgt <= 4'b1101;
2: dgt <= 4'b1011;
3: dgt <= 4'b0111;
endcase
endmodule
| 6.706835 |
module dhcp_client_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 7.545078 |
module dhcp_client_m_axis_open_port_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] openPort_V_V_din,
output wire openPort_V_V_fu... | 8.515157 |
module dhcp_client_m_axis_open_port_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.515157 |
module dhcp_client_m_axis_open_port_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire... | 8.515157 |
module dhcp_client_m_axis_tx_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [63:0... | 8.515157 |
module dhcp_client_m_axis_tx_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.515157 |
module dhcp_client_m_axis_tx_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 8.515157 |
module dhcp_client_m_axis_tx_length_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] dataOutLength_V_V_din,
output wire dataOutLen... | 8.515157 |
module dhcp_client_m_axis_tx_length_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.515157 |
module dhcp_client_m_axis_tx_length_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire... | 8.515157 |
module dhcp_client_m_axis_tx_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [95:0] TDATA,
// User signals
input wire [95:0] dataOutMeta_V_din,
output wire dataOutMeta_... | 8.515157 |
module dhcp_client_m_axis_tx_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wi... | 8.515157 |
module dhcp_client_s_axis_open_port_status_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [0:0] confirmPortStatus_V_dout,
output wire confirm... | 8.738232 |
module dhcp_client_s_axis_open_port_status_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.738232 |
module dhcp_client_s_axis_open_port_status_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
outp... | 8.738232 |
module dhcp_client_s_axis_rx_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0... | 8.738232 |
module dhcp_client_s_axis_rx_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.738232 |
module dhcp_client_s_axis_rx_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 8.738232 |
module dhcp_client_s_axis_rx_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [95:0] TDATA,
// User signals
output wire [95:0] dataInMeta_V_dout,
output wire dataInMeta_V... | 8.738232 |
module dhcp_client_s_axis_rx_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wi... | 8.738232 |
module DHT11wdisp (
input clk_i, //@50 MHz (the same for all modules)
inout w1_o, //Data wire of DHT11
output [6:0] DISP, //Segments of 7-seg display
output [3:0] AN, //Anodes of 4 7-seg display
output LED_d //LED that blinks at each transfer
);
wire [15:0] dataDisp; //{8 bits of temp, 8 bit... | 7.968867 |
module dht11tb ();
reg clk = 0;
always #1 clk = ~clk;
reg out = 0;
reg data_reg = 1;
inout data;
assign data = (out == 0) ? 1'bZ : data_reg;
pullup (data);
dht11 DHT (.data_io(data));
initial begin
#57; // wait for 5.7us
out = 1; // master controls the line
#15; // wait for 1.5us
... | 6.605763 |
module DHT22_control_tb ();
reg clk;
reg rst;
wire DHT_DATA;
wire [39:0] HT_data;
initial clk = 0;
always #1 clk = ~clk; //ʱź
initial begin
rst = 0; //ģһźţӻźţһʼһʼ2sʱ
#50;
rst = 1;
force DHT_DATA = 0;
#1000;
release DHT_DATA;
#1;
force DHT_DATA = 1;
#20;
release ... | 6.567113 |
module DHT22_MUX (
clk,
reset,
get,
sda,
data
);
input wire clk;
input wire reset;
input wire get;
inout sda;
output wire [39:0] data;
wire wdivClk;
divClk Add_DivClk2MHz (
.clk(clk),
.divClk(wdivClk)
);
DHT22 Add_DHT22 (
.clk (wdivClk),
.reset(reset),
... | 7.484607 |
module di (
in,
en,
PU,
PD,
PAD
);
output in;
input PU;
input PD;
input en;
input PAD;
assign in = PAD;
endmodule
| 7.414618 |
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