code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module diag_serial (
input clk, // 48MHz CPU clock
input reset, // Low-true reset
input [11:0] a0,
a1,
a2,
a3,
output tx
);
// hard-coded bit-rate
localparam sym_rate = 115200;
localparam clk_freq = 48000000;
localparam sym_cnt = clk_freq / sym_rate;
localparam SCW = $clog2(sym_... | 8.113867 |
module to perform the dialation operation
///Mubarik Mohamoud
//////
module dialate (clk, vclk, fvh, dv, pixel, d_pixel);
input clk; // system clock
input vclk; // video clock from camera
input [2:0] fvh;//hsync and vsync
input dv;
input [7:0] pixel;
output reg [7:0] d_pixel;
parameter C... | 6.60874 |
module dianziqing(clk,key,switch,speakers,num_show,);
input clk;
input [6:0]key;
input switch;
output speakers;
output reg [2:0]num_show; //数码管显示数字
reg [10:0]d; //分频系数
reg [10:0]o; //初始值
reg speaker;
assign speakers=switch&&speaker;
parameter do=1,
re=2,
mi=4,
fa=8,
so=16,
la=32,
xi=64;
... | 7.14244 |
module display_controller (
day0_dec,
day1_dec,
month0_dec,
month1_dec,
year0_dec,
year1_dec,
content,
clk_quick,
ssd_ctrl,
show
);
input [7:0] day0_dec;
input [7:0] day1_dec;
input [7:0] month0_dec;
input [7:0] month1_dec;
input [7:0] year0_dec;
input [7:0] year1_dec... | 6.902359 |
module DiceGame (
Rb,
Reset,
CLK,
Sum,
Roll,
Win,
Lose
);
input Rb;
input Reset;
input CLK;
input [3:0] Sum;
output Roll;
output Win;
output Lose;
reg Roll;
reg Win;
reg Lose;
reg [2:0] State;
reg [2:0] Nextstate;
reg [3:0] Point;
reg Sp;
initial begin
Stat... | 7.098886 |
module DiceGame (
//////////// CLOCK //////////
input CLOCK_50,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// KEY //////////
input [3:0] KEY,
//////////// VGA... | 7.801863 |
module dice_4 (
input rollbtn,
input clk,
input rst,
output reg [2:0] out
);
localparam SEED = 128'h843233523a613966423b622562592c62;
reg [2:0] M_dice_out_d, M_dice_out_q = 1'h0;
wire [1-1:0] M_detector_a_out;
reg [1-1:0] M_detector_a_in;
edge_detector_5 detector_a (
.clk(clk),
... | 7.226638 |
module dice_7 (
input clk,
input rst,
output reg [2:0] out
);
localparam SEED = 128'h843233523a613966423b622562592c62;
wire [1-1:0] M_edge_rng_out;
reg [1-1:0] M_edge_rng_in;
edge_detector_13 edge_rng (
.clk(clk),
.in (M_edge_rng_in),
.out(M_edge_rng_out)
);
wire [1-1:0] M_... | 6.830921 |
module dice_8 (
input clk,
input rst,
output reg [2:0] out
);
localparam SEED = 128'h843233523a613966423b622562592c62;
wire [1-1:0] M_edge_rng_out;
reg [1-1:0] M_edge_rng_in;
edge_detector_13 edge_rng (
.clk(clk),
.in (M_edge_rng_in),
.out(M_edge_rng_out)
);
wire [1-1:0] M_... | 6.607612 |
module implements a differentiator with 2 multiplexed inputs.
//
// 25 LUT6s and 72 registers used. 306 MHz maximum clock rate.
//
module dif24e2(
input [23:0] d, // input
output [23:0] q, // output
input ce0,ce1, // clock enables
input clk, // clock
input rst // reset
);
// internal signa... | 6.904081 |
module DifBitSync (
rst,
clk,
dataout,
Bit_Sync
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟:32MHz
output [5:0] dataout; //延时处理后的输出数据
output Bit_Sync; //位同步脉冲输出
//实例化输入数据产生模块
wire [5:0] datain;
DinProduce u1 (
.rst (rst),
.clk32 (clk),
.cosine (datain)
);
... | 7.247664 |
module meiadiferenca (
s0,
s1,
x,
y
);
output s0, s1;
input x, y;
xor XOR1 (s0, x, y);
and AND1 (s1, ~x, y);
endmodule
| 7.462199 |
module notgate (
s,
a
);
input a;
output s;
nor NOR1 (s, a, a);
endmodule
| 7.575943 |
module xorgate (
s6,
a,
b
);
input a, b;
output s6;
nor NOR1 (s1, a, a);
nor NOR2 (s2, b, b);
nor NOR3 (s3, a, s2);
nor NOR4 (s4, b, s1);
nor NOR5 (s5, s3, s4);
nor NOR6 (s6, s5, s5);
endmodule
| 7.421731 |
module diffeq_paj_convert (
Xinport,
Yinport,
Uinport,
Aport,
DXport,
Xoutport,
Youtport,
Uoutport,
clk,
reset
);
input [31:0] Xinport;
input [31:0] Yinport;
input [31:0] Uinport;
input [31:0] Aport;
input [31:0] DXport;
input clk;
input reset;
output [31:0] Xoutp... | 6.791642 |
module diffeq_paj_convert (
Xinport,
Yinport,
Uinport,
Aport,
DXport,
Xoutport,
Youtport,
Uoutport,
CLK,
reset
);
input [31:0] Xinport;
input [31:0] Yinport;
input [31:0] Uinport;
input [31:0] Aport;
input [31:0] DXport;
input CLK;
input reset;
output [31:0] Xoutp... | 6.791642 |
module top (
pixel_in,
predic_in,
\pixel_in$1 ,
\predic_in$2 ,
end_in,
rst,
clk,
val_out,
\val_out$3 ,
\val_out$4 ,
\val_out$5 ,
valid_out,
end_out,
valid_in
);
wire [17:0] \$10 ;
wire [16:0] \$11 ;
wire [17:0] \$13 ;
wire [17:0] \$15 ;
wire [16:0] \$16 ... | 7.033161 |
module Difference_3D (
input iclk,
input irst_n,
input signed [8:0] iData_right,
input signed [8:0] iData_left,
input signed [8:0] iData_bot,
input signed [8:0] iData_top,
input signed [8:0] iData_next,
input signed [8:0] iData_pre,
output signed [8:... | 9.452149 |
module Difference_Engine (
input wire [5:0] n, //max n = 2**6 - 1
input wire start,
clk,
reset,
output reg [12:0] data_out, //max data_out = f(n), so max bits is log base 2 of f(n)
output reg done_tick
);
localparam [1:0] IDLE = 2'b00, OPERATE = 2'b01, DONE = 2'b10;
//state reg
reg [1:0]... | 7.415147 |
module difference_lbp (
windowIn,
lbpPattern
); // 3x3 Center Threshold Pattern Computation
parameter inputWidth = 8;
parameter threshold = 5;
input [inputWidth*9-1:0] windowIn;
wire [inputWidth-1:0] win[0:8];
wire [7:0] comparisonString[0:7];
output [7:0] lbpPattern;
generate
// Make c... | 7.372612 |
module differpd (
rst,
clk32,
datain,
clk_i,
clk_q,
pd_bef,
pd_aft
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
input datain; //输入数据
input clk_i; //由控制分频模块送来的同相同步脉冲信号（占空比为1:1）
input clk_q; //由控制分频模块送来的正交同步脉冲信号（占空比为1:1）
output pd_bef; //输出的超前脉冲信号
output pd_aft... | 6.833712 |
module difficulty_converter (
input wire difficulty,
input wire clk,
input wire rst,
output reg [1:0] difficulty_converted
);
always @(posedge clk) begin
if (rst) begin
difficulty_converted <= 2;
end else begin
case (difficulty)
1'b0: difficulty_converted <= 2'b11;
... | 7.022752 |
module diffor (
input wire [31:0] x,
input wire [31:0] int_x,
output wire [31:0] out // out = x*dt + int_x
);
assign out = int_x_F0;
//assign out = 32'h3f67b7cc;
endmodule
| 7.259516 |
module DifftestArchEvent (
input io_clock,
input [ 7:0] io_coreid,
input [31:0] io_intrNO,
input [31:0] io_cause,
input [63:0] io_exceptionPC,
input [31:0] io_exceptionInst
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" function void v_difftest_ArchEvent(
input byte io_core... | 7.807102 |
module DifftestCSRState (
input io_clock,
input [ 7:0] io_coreid,
input [ 1:0] io_priviledgeMode,
input [63:0] io_mstatus,
input [63:0] io_sstatus,
input [63:0] io_mepc,
input [63:0] io_sepc,
input [63:0] io_mtval,
input [63:0] io_stval,
input [63:0] io_mtvec,
input [6... | 7.190099 |
module DifftestInstrCommit (
input io_clock,
input [ 7:0] io_coreid,
input [ 7:0] io_index,
input io_valid,
input [ 7:0] io_special,
input io_skip,
input io_isRVC,
input io_rfwen,
input io_fpwen,
input [31:0] io_wpdest,
input [ 7:0] i... | 7.953528 |
module DifftestIntWriteback (
input io_clock,
input [ 7:0] io_coreid,
input io_valid,
input [31:0] io_dest,
input [63:0] io_data
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" function void v_difftest_IntWriteback(
input byte io_coreid,
input bit io_valid,
in... | 6.738789 |
module DifftestRunaheadCommitEvent (
input io_clock,
input [ 7:0] io_coreid,
input [ 7:0] io_index,
input io_valid,
input [63:0] io_pc
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" function void v_difftest_RunaheadCommitEvent(
input byte io_coreid,
input byte io_... | 7.626274 |
module DifftestRunaheadEvent (
input io_clock,
input [ 7:0] io_coreid,
input [ 7:0] io_index,
input io_valid,
input io_branch,
input io_may_replay,
input [63:0] io_pc,
input [63:0] io_checkpoint_id
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" functio... | 7.626274 |
module DifftestRunaheadRedirectEvent (
input io_clock,
input [ 7:0] io_coreid,
input io_valid,
input [63:0] io_pc,
input [63:0] io_target_pc,
input [63:0] io_checkpoint_id
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" function void v_difftest_RunaheadRedirectEvent(
inp... | 7.626274 |
module DifftestTrapEvent (
input io_clock,
input [ 7:0] io_coreid,
input io_valid,
input [63:0] io_cycleCnt,
input [63:0] io_instrCnt,
input [ 2:0] io_code,
input [63:0] io_pc
);
`ifndef SYNTHESIS
`ifdef DIFFTEST
import "DPI-C" function void v_difftest_TrapEvent(
input b... | 8.420165 |
module difftest_commit_inst #(
parameter CONFIG_P_COMMIT_WIDTH = 0,
parameter CONFIG_NUM_IRQ = 0
) (
input clk,
input [(1<<CONFIG_P_COMMIT_WIDTH)-1:0] valid,
input [(1<<CONFIG_P_COMMIT_WIDTH)*30-1:0] pc,
input [(1<<CONFIG_P_COMMIT_WIDTH)*32-1:0] insn,
input [(1<<CONFIG_P_COMMIT_WIDTH)-1:0] w... | 6.611612 |
module diffusion_test_bench_harness ();
//wires for the diffusion
wire [7:0] diffusion_in[3:0][3:0];
wire [7:0] diffusion_out[3:0][3:0];
//wires for the tester
reg begintest;
wire dutpassed;
//instantiate the diffusion module
diffusion DUT (
.diffusion_in (diffusion_in),
.diffusion_out(d... | 7.012419 |
module diffusion_test_bench (
input begintest,
output reg endtest,
output reg dutpassed,
output reg [7:0] diffusion_in[3:0][3:0],
input [7:0] diffusion_out[3:0][3:0]
);
always @(posedge begintest) begin
$display("Testing diffusion now...");
endtest = 0;
dutpassed = 1;
#20
/... | 7.012419 |
module shift_rows (
input [7:0] shift_rows_in [3:0][3:0], //square matrix with 8 bits in each element; width is four, depth is four
output [7:0] shift_rows_out[3:0][3:0]
);
//push everything to the left and then wrap it around
assign shift_rows_out[3][3:0] = shift_rows_in[3][3:0]; //1: all the same
a... | 6.667518 |
module diffusion (
input [7:0] diffusion_in [3:0][3:0], //square matrix with 8 bits in each element; width is four, depth is four
output [7:0] diffusion_out[3:0][3:0]
);
wire [ 7:0] srows_out [3:0][3:0];
wire [31:0] col_1_in;
wire [31:0] col_1_out;
wire [31:0] col_2_in;
wire [31:0] col_2_out;
wire... | 6.849523 |
module Diff_2 (
input wire [7:0] In1,
input wire [7:0] In2,
output wire [8:0] Out
);
always @(*)
if (In1 > In2) Out = (In1 << 1) - (In2 << 1);
else Out = (In2 << 1) - (In1 << 1);
endmodule
| 7.35049 |
module diff_ddr_reg (
clk,
reset,
input_p,
input_n,
output_rise,
output_fall
);
// System Parameters
//==================
parameter width = 8;
// Inputs and Outputs
//====================
input clk;
input reset;
input [width-1:0] input_p;
input [width-1:0] input_n;
output [... | 7.32575 |
module diff_qdr_reg (
clk_0,
clk_90,
clk_180,
clk_270,
data_p,
data_n,
data_rise_0,
data_fall_0,
data_rise_90,
data_fall_90
);
// System Parameters
parameter width = 8;
// Inputs and Outputs
//===================
input clk_0;
input clk_90;
input clk_180;
input c... | 7.28209 |
module diff_TB;
reg [31:0] a = 32'd0;
reg [31:0] b = 32'd0;
wire [31:0] out;
diff uut (
.a(a),
.b(b),
.diffBit(out)
);
initial begin
$monitor("a = %d, b = %d, diff = %d", a, b, out);
#5 a = 32'd1;
b = 32'd0;
#5 a = 32'd5045;
b = 32'd45042;
#5 a = 32'd32768;
... | 7.212351 |
module diff_to_se #(
parameter width = 8
) (
input [width-1:0] data_p,
input [width-1:0] data_n,
output [width-1:0] data
);
genvar i;
generate
for (i = 0; i < width; i = i + 1) begin : se_gen
// Convert LVDS pair to single-ended
IBUFGDS #(
.DIFF_TERM ("TRUE"), // Dif... | 8.091918 |
module dif_radix2_64p_da #(
parameter DATA_WIDTH = 17,
parameter RF_DEPTH = 8
) (
input wire clk,
input wire rst_n,
input wire [ 3:0] wen_ctrl,
input wire [ 3:0] ren_ctrl,
input wire [ 2:0] waddr_ctrl,
input wire [ ... | 7.839753 |
module.
//
//////////////////////////////////////////////////
module dif_radix2_pe
#(
parameter DATA_WIDTH_IN = 10,
parameter DATA_WIDTH_OUT = 12,
parameter TWIDDLE_RANK = 8,
parameter FIFO_DEPTH = 32
)(
input wire clk,
input wire rst_n,
... | 7.119381 |
module DIGDUG_CORES (
input MCLK, //! Clock (48.0MHz)
input [2:0] RSTS, //! RESET [2:0]
input [2:0] IRQS, //! IRQ [2:0]
input [2:0] NMIS, //! NMI [2:0]
output DEV_CL, //! I/O device Interface
output [15:0] DEV_AD,
output DEV_RD,
input DEV_DV,
input [... | 6.685437 |
module CPUARB (
input CLK48M,
output DEV_CL,
output [15:0] DEV_AD,
output DEV_RD,
input DEV_DV,
input [ 7:0] DEV_DO,
output DEV_WR,
output [ 7:0] DEV_DI,
output CPU0CL,
input [15:0] CPU0AD,
input CPU0RD,
output CPU0DV... | 6.609135 |
module add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out = 4'b0000;
4'b0001: out = 4'b0001;
4'b0010: out = 4'b0010;
4'b0011: out = 4'b0011;
4'b0100: out = 4'b0100;
4'b0101: out = 4'b1000;
4'b0110: out = ... | 7.173963 |
module DIGDUG_IODEV (
input RESET,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] DSW0,
input [7:0] DSW1,
input VBLK, //! V-BLANK
input CL, //! CPU Interface
input [15:0] AD,
input WR,
input [ 7:0] DI,
input RD,
output DV,
output... | 7.71917 |
module DIGDUG_CLATCH (
input RESET,
input CL, // 24MHz
input [2:0] AD,
input WR,
input DI,
input VBLK,
output [2:0] RSTS,
output [2:0] IRQS,
output NMI2
);
// OSC 120Hz
`define H120FLOW (12500)
reg [3:0] clkdiv;
always @(posedge CL) ... | 6.810417 |
module digfoto (
input CLK,
input [3:0] BTN,
input SD_DO_7,
output [6:0] SEG,
output [3:0] AN,
output DP,
// output [2:0] RGB_R,
// output [2:0] RGB_G,
// output [2:1] RGB_B,
// output HSYNC,
// outp... | 6.612053 |
module digi #(
parameter SIZE = 8,
WIDTH = 16
) (
input wire RST,
input wire CK50,
input wire DAVAIL,
input wire TRIGGER,
input wire [WIDTH-1:0] adcdata_p,
input wire [ SIZE-1:0] howmany,
input wire [ SIZE-1:0] offset,
output... | 7.243574 |
module digit #(
parameter color = 3'b111
) (
input wire px_clk, // Pixel clock.
input wire [25:0] strRGB_i, // Input RGB stream.
input wire [ 9:0] pos_x, // X number position.
input wire [ 9:0] pos_y, // Y number position.
input wire [ 3:0] number, // Number to stream.... | 7.722797 |
module digit2num (
input [31:0] num,
output [10:0] int_,
output [12:0] deci
);
wire [22:0] frac, f1;
wire [23:0] decimal, tmp;
wire [7:0] mov;
assign frac[22:0] = num[22:0];
assign decimal[23:0] = {1'b1, frac[22:0]};
assign mov[7:0] = num[30:23];
assign f1[22:0] = frac[22:0] << (mov);
ass... | 6.826057 |
module digit2_rom (
input clk,
input [5:0] x,
input [2:0] y,
input [3:0] a0,
input [3:0] a1,
output reg [11:0] color
);
wire [7:0] col0;
wire [7:0] col1;
wire [7:0] col2;
wire [7:0] col3;
wire [7:0] col4;
wire [7:0] col5;
wire [7:0] col6;
wire [7:0] col7;
wire [7:0] col8;
wi... | 6.648061 |
module for counter
////////////////////////////////////////////////////////////////////////////////
module counter(clk,rst,count);
input clk;
input rst;
output count;
reg counter;
wire rst_2;
assign rst_2 = rst;
assign count =counter;
//use counter to define the period value of output
always @ (posedge)
begin
... | 7.300834 |
module digital_display_4 (
input [15:0] data,
input format_select, // 0 = hex, 1 = decimal
output reg [7:0] digit,
output reg [3:0] select,
input clk
);
reg [31:0] data_reg_formatted;
wire [31:0] data_formatted_dec;
wire [31:0] data_formatted_hex;
always @(posedge clk) begin
if (form... | 6.738405 |
module DigitalClock_Drive (
input clk,
input rst_N,
input [ 2:0] DTube_en,
input [ 2:0] Twinkle_en,
input [23:0] number_BCD,
input HOURLY,
input ALARM,
output [41:0] Dtube_out,
output LED_hourly,
output LED_alarm,
input VGA_CLK_IN, // (... | 7.319542 |
module.
//
// Delay the rising and falling edges of a digital signal.
// This design has ? clock cycles of latency.
//
///////////////////////////////////////////////////////////////////////////////
`include "timescale.v"
module DigitalDelay(
input wire clk_in,
input wire rst_in,
input w... | 8.543549 |
module dec3to8 (
W,
En,
Y
);
input [2:0] W;
input En;
output [0:7] Y;
reg [0:7] Y;
always @(W or En) begin
if (En == 1)
case (W)
3'b000: Y = 8'b10000000;
3'b001: Y = 8'b01000000;
3'b010: Y = 8'b00100000;
3'b011: Y = 8'b00010000;
3'b100: Y = 8'b000... | 7.162437 |
module DigitalLockerCtrl (
input clk,
rst_n,
output [3:0] row,
input [2:0] col,
output buzzer_out,
output servo_pwm,
/*** uncomment if you want to display the key on segment display*/
output [8:0] seg_led_1,
output [8:0] seg_led_2
);
wire [3:0] keyUserInput;
keypad_3by4 Locker... | 6.76213 |
module ***************************/
module ServoAngle(
input wire clk,rst_n,
input wire pw_true,
output reg [7:0] rotate_angle
);
parameter T_DELAY=28'd60000000;
reg delay_rst;
reg [27:0] cnt_delay;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
rotate_angle<=8'd90;
delay_rst<=1'b1;
end... | 7.014884 |
module ****************************/
module servo (
input clk, rst_n,
// Since a servo does not rotate beyond 180 degrees, use 8-bit is enough (0 - 255)
input [7:0] rotate_angle, // Rotation degrees in Binary form
output reg servo_pwm
);
localparam CNT_20MS = 240_000; // 240000 counts means 20ms
local... | 7.793578 |
module pwd_checker (
input wire clk,
rst_n,
input wire [3:0] keyUserInput,
output reg pw_true,
output reg pw_false,
output reg timeout_flag
);
parameter TIME_OUT = 28'd120000000;
parameter PASSWORD = 16'h1234;
localparam IDLE = 3'b001;
localparam LOAD_PWD = 3'b010;
localp... | 6.651481 |
module buzzer (
input wire clk,
rst_n,
input wire pw_false,
input wire timeout_flag,
output wire beep_out
);
parameter T_FREQ = 24'd12000; //1kHZ (1ms)-> T_FREQ=12000
parameter T_TIMEOUT = 28'd12000000; // Counter for 1s, beep time for time out
parameter T_PW_ERROR = 28'd36000000; // Co... | 8.246219 |
module DigitalLockerCtrl_top (
input clk,
rst_n,
output [3:0] row,
input [2:0] col,
output buzzer_out,
output servo_pwm
);
wire [3:0] keyUserInput;
keypad_3by4 LockerKeyIn (
clk,
rst_n,
col,
row,
keyUserInput
);
wire pw_true, pw_false, timeout_flag;
pwd_... | 6.76213 |
module DigitalSystemDesigning_tb ();
reg clk = 1'b0;
reg rst, sw;
reg [3:0] state_in;
reg [7:0] row = 8'b0000_0000;
reg [7:0] col_r = 8'b0000_0000;
reg [7:0] col_g = 8'b0000_0000;
reg [7:0] seg_row = 8'b0000_0000;
reg [7:0] seg_col = 8'b0000_0000;
initial begin
#5 clk = 1'b0;
#5 rst = 1'b0;
... | 6.580486 |
module DigitalTube (
CLK,
nRST,
KEY_ROW,
KEY_COL,
SEL,
SEG
);
input CLK;
input nRST;
input [3:0] KEY_COL;
output [3:0] KEY_ROW;
output [7:0] SEL; //位选
output [7:0] SEG; //段选
wire value_en;
wire [3:0] key_value;
KeyValue keyValue1 (
.CLK(CLK),
.nRST(nRST),
... | 7.718255 |
module DigitalTube_2b (
input clk,
input rst_N,
input enable,
input [7:0] number_BCD,
output [13:0] pin_out
);
DigitalTube DigitalTube_bit0_inst (
.clk (clk),
.rst_N(rst_N),
.enable(enable),
.number(number_BCD[3:0]),
.pin_out(pin_out[6:0])
);
Digital... | 6.581341 |
module DigitalTube_3b (
clk,
rst_N,
number_BCD,
pin_out
);
input clk, rst_N;
input [11:0] number_BCD;
output wire [20:0] pin_out;
DigitalTube DigitalTube_bit0_inst (
.clk (clk),
.rst_N(rst_N),
.number (number_BCD[3:0]),
.pin_out(pin_out[6:0])
);
DigitalTube ... | 6.561299 |
module AND_gate (
A,
B,
Out
); //AND gate
input [31:0] A;
input [31:0] B;
output [31:0] Out;
assign Out = (A & B);
endmodule
| 9.051243 |
module OR_gate (
A,
B,
Out
); //OR gate
input [31:0] A;
input [31:0] B;
output [31:0] Out;
assign Out = (A | B);
endmodule
| 7.299093 |
module XOR_gate (
A,
B,
Out
); //XOR gate
input [31:0] A;
input [31:0] B;
output [31:0] Out;
assign Out = (A ^ B);
endmodule
| 6.929818 |
module NOT_gate (
A,
Out
); //NOT gate
input [31:0] A;
output [31:0] Out;
assign Out = ~A;
endmodule
| 7.989412 |
module NAND_gate (
A,
B,
Out
); //NAND gate
input [31:0] A;
input [31:0] B;
output [31:0] Out;
assign Out = ~(A & B);
endmodule
| 8.717357 |
module NOR_gate (
A,
B,
Out
); //NOR gate
input [31:0] A;
input [31:0] B;
output [31:0] Out;
assign Out = ~(A | B);
endmodule
| 7.574279 |
module ADD_er (
A,
B,
SUM,
Cout
); //ADDER
input [31:0] A;
input [31:0] B;
output Cout;
output [31:0] SUM;
reg [31:0] SUM_local;
always @(*) begin
SUM_local = A + B;
end
assign SUM = SUM_local[31:0]; //SUM
assign Cout = SUM_local[32]; //Cout
endmodule
| 7.520217 |
module DIV_er (
A,
B,
Out,
Remainder
); //divider/remainder
input [31:0] A;
input [31:0] B;
output [31:0] Out;
output [31:0] Remainder;
reg [31:0] DIV_local;
reg [31:0] REMAIN_local;
always @(*) begin
DIV_local = B / A;
REMAIN_local = B % A;
end
assign Out = DIV_local[31:0];
... | 7.295858 |
module SHL_Logic (
A,
Out
); //1-bit logic shift left
input [31:0] A;
output [31:0] Out;
reg [31:0] SHL_local;
always @(*) begin
SHL_local = (A << 1);
end
assign Out = SHL_local[31:0];
endmodule
| 7.555215 |
module SHR_Logic (
A,
Out
); //1-bit logic shift right
input [31:0] A;
output [31:0] Out;
reg [31:0] SHR_local;
always @(*) begin
SHR_local = (A >> 1);
end
assign Out = SHR_local[31:0];
endmodule
| 7.502719 |
module DFF (
clk,
inputA,
Out
); //DFF for ERROR state
input clk;
input inputA;
output Out;
reg Out;
always @(posedge clk) begin
Out = inputA;
end
endmodule
| 8.191977 |
module DFF_register (
clk,
reset,
inputA,
Out
); //ACC
input clk;
input reset;
input [31:0] inputA;
output [31:0] Out;
wire [31:0] zeroes;
assign zeroes = {32{1'b0}};
reg [31:0] rst;
always @(posedge clk) begin
rst = inputA;
if (reset == 1) begin
rst = 0;
end
end
a... | 7.478858 |
module MUX (
channels,
select,
Out
); //16 channels(32bit) - Multiplexer
input [15:0][31:0] channels;
input [3:0] select;
output [31:0] Out;
assign Out = channels[select];
endmodule
| 7.447887 |
module breadboard (
clk,
reset,
A,
B,
C,
opcode,
ERR_out
); //breadboard
input clk;
input reset;
input [3:0] opcode;
input [31:0] A;
input [31:0] B;
output [31:0] C;
output ERR_out;
reg [31:0] curA;
reg [31:0] curB;
reg [31:0] curC;
reg curERROR;
reg [31:0] nextA;
... | 6.534342 |
module dig_clk_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire [6:0] sec;
wire [6:0] min;
wire [4:0] hr;
// Instantiate the Unit Under Test (UUT)
dig_clk uut (
.clk(clk),
.rst(rst),
.sec(sec),
.min(min),
.hr(hr)
);
initial
begin
$monitor($time," sec=%d min=%d hour=%d ",sec,min,hr);
end... | 6.603759 |
module using erification methods
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module digital_clock_tb_verification(
);
// Inputs
reg Clk_1sec;
reg reset;
reg ... | 7.43135 |
module digital_fltr (
input clk,
input signal_in,
output reg signal_out
);
parameter [7:0] clk_cnt = 20;
reg [7:0] cnt_pos = 8'h00;
reg [7:0] cnt_neg = 8'h00;
initial begin
signal_out <= 1'b0;
end
always @(posedge clk) begin
if (signal_in) begin
cnt_neg <= 8'h00;
cnt_pos... | 6.590004 |
module digital_part #(
//TMU Parameters
parameter HIGH_COUNT = 1,
parameter LOW_COUNT = 12,
//SAR Parameters
parameter PRECISION = 10
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
//Common Input Signals
input r... | 6.671483 |
module digital_piano (
inclk,
ps2_clk,
ps2_data,
start,
reset,
out,
ChannelSelect,
key,
record,
replay,
select,
hsync,
vsync,
vga_r,
vga_g,
vga_b,
anodes,
cathodes,
YinDiao
);
//input timbre;
input [2:0] YinDiao;
input start, reset; //ϵ... | 6.530986 |
module digital_pll (
`ifdef USE_POWER_PINS
VDD,
VSS,
`endif
resetb,
enable,
osc,
clockp,
div,
dco,
ext_trim
);
`ifdef USE_POWER_PINS
input VDD;
input VSS;
`endif
input resetb; // Sense negative reset
input enable; // Enable PLL
input osc; // Input oscillator to match
... | 6.677006 |
module DigitalPort (
input clk,
input rst,
input chipSelect,
input writeIO,
input writeDirection,
input [31:0] dataIn,
output [31:0] dataOut,
output [31:0] directionOut,
inout [31:0] IO // Connected to FPGA pins
);
reg [31:0] direction;
... | 7.014442 |
module digital_screen (
clock,
key1,
time1,
time2,
time3,
time4,
time5,
time6,
mark_a1,
mark_a2,
mark_a3,
mark_b1,
mark_b2,
mark_b3,
out_data,
c_pin
);
input clock, key1;
input [7:0] time1, time2, time3, time4, time5, time6;
input [7:0] mark_a1, mark... | 6.648385 |
module serial #(
parameter DATA_WIDTH = 163,
parameter DIGITAL = 32
) (
input wire [DIGITAL - 1:0] b,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DATA_WIDTH - 1 : 0] t_i1_j1,
output wire [DATA_WIDTH - 1 : 0] t_i_j
);
generate
genvar j;
for (j... | 7.084733 |
module digital_sound_output (
input clk,
input rst,
input enabled,
input [15:0] left,
input [15:0] right,
output bck,
output sd,
output lrck,
output consume
);
parameter CLK_FREQUENCY = 33868800;
localparam BCK_HALF_PERIOD = (CLK_FREQUENCY / 44100 / 64 / 2);
function integer... | 6.786059 |
module should behave in the following
* pattern:
* 1- get the slower clk from high clk input
* 2- count on posedge of slow clk
* 3- convert counter output to BCD values
* 4- send the BCD values to segment display decoder
*/
module digital_timer_top (seg_0,seg_1,clk_50MHz,reset);
input clk_50MHz;
input reset;
output [7:... | 6.770395 |
module digital_video (
input clk_25mhz,
input rst,
input [7:0] red,
input [7:0] green,
input [7:0] blue,
output [9:0] xout,
output [9:0] yout,
output vsync_out,
output [2:0] rgbout
);
wire [9:0] x_wire;
wire [9:0] y_wire;
assign xout = x_wire;
assign yout = y_wire;
assign... | 6.526846 |
module facilitates the blinking of the selected digit on the seven segment LED
module digitBlinker(isDigitSelected,digitInfo,digitOutput,clk,rst);
input isDigitSelected, clk, rst;
input [6:0] digitInfo;
output [6:0] digitOutput;
wire pulse;
oneSecTimer blinkPulser(1'b1,clk,rst,pulse);
outputLoadRegister outpu... | 8.353001 |
module digitDecoder (
digit,
decodedValue
);
// 4-bit input number, which should be between decimal 1-4 inclusive
input [3:0] digit;
// 4-bit binary value, decoded result
output [3:0] decodedValue;
reg [3:0] decodedValue;
always @(digit) begin
// Decode input digit, assign result to decodedVal... | 7.528302 |
module digitDisplay (
x,
y,
digit,
score_raw
);
input [2:0] x, y;
input [3:0] digit;
output wire [23:0] score_raw;
reg [0:14] digitShape;
always @(digit) begin
case (digit)
4'd0: digitShape <= 15'h7b6f;
4'd1: digitShape <= 15'h2492;
4'd2: digitShape <= 15'h73e7;
4... | 8.148757 |
module digitel2000_16x7seg (
input CLK,
output [7:0] extseg_out,
output [15:0] extdigit_out,
input refresh,
input [2:0] dig0,
input [2:0] dig1,
input [2:0] dig2,
input [2:0] dig3,
input [2:0] dig4,
input [2:0] dig5,
input [2:0] dig6,
input [2:0] dig7,
input [2:0] dig8... | 7.250135 |
module Digitizer (
lineIns,
lineOuts
);
// Define inputs and outputs
input [4:0] lineIns;
output [13:0] lineOuts;
wire [3:0] M;
wire Z;
wire [3:0] Mwires;
// Create the converter
Converter converter (
.lineIns (lineIns),
.lineOuts(Mwires)
);
// Create the comparator
Compara... | 7.938276 |
module lock_sub (
input wire [4:0] num,
output reg [6:0] a_to_g
);
always @(*)
case (num)
0: a_to_g = 7'b0000001; //0 - '0'
1: a_to_g = 7'b1001111; //1 - '1'
2: a_to_g = 7'b0010010; //2 - '2'
3: a_to_g = 7'b0000110; //3 - '3'
4: a_to_g = 7'b1001100; //4 - '4'
... | 6.842786 |
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