code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module locker_sub (
input wire [4:0] num,
output reg [6:0] a_to_g
);
always @(*)
case (num)
0: a_to_g = 7'b0000001; //0 - '0'
1: a_to_g = 7'b1001111; //1 - '1'
2: a_to_g = 7'b0010010; //2 - '2'
3: a_to_g = 7'b0000110; //3 - '3'
4: a_to_g = 7'b1001100; //4 - '4'
... | 7.202546 |
module digitos (
key1,
key2,
hex1,
hex2,
bcd1,
bcd2
);
input key1, key2;
output reg [6:0] hex1, hex2;
reg [3:0] d1, d2;
output reg [3:0] bcd1, bcd2;
initial begin
d2 <= 0;
d1 <= 0;
end
function [6:0] display;
input [3:0] bcd;
reg [6:0] segmentos;
//if (r) begi... | 7.792642 |
module DigitRenderer (
input [10:0] x,
y,
input [10:0] cx,
cy,
input [3:0] digit,
output wor hit
);
reg [6:0] enable;
// - [0]
// | | [5] [1]
// - [6]
// | | [4] [2]
// - [3]
always @(digit) begin
case (digit)
4'h0: enable = 7'b1000000;
4'h1: enab... | 6.719674 |
module DIGITS (
input clk,
// wishbone
input W_RST,
input W_CLK,
input wire [31:0] W_ADDR,
input wire [31:0] W_DAT_I,
output reg [31:0] W_DAT_O,
output wire W_ACK,
output reg [7:0] hex,
output reg [7:0] dig
);
parameter addr = 32'h0000_0000;
reg ack;
reg [31:0] data;
... | 6.971307 |
module digits10_array (
input wire [3 : 0] digit, // digit 0-9
input wire [2 : 0] yofs, // vertical offset (0-4)
output reg [4 : 0] bits // output (5 bits)
);
/*******************************************************
* WIRE AND REG DECLARATION *
****************... | 7.526921 |
module test_numbers_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/*******************************************************
* ... | 6.792031 |
module with 5x5 bitmaps for the digits 0-9.
digits10_case - Uses the case statement.
digits10_array - Uses an array and initial block.
These two modules are functionally equivalent.
*/
module digits10_array(digit, yofs, bits);
input [3:0] digit; // digit 0-9
input [2:0] yofs; // vertical offset (0-4)
outp... | 7.218525 |
module with 5x5 bitmaps for the digits 0-9.
digits10_case - Uses the case statement.
digits10_array - Uses an array and initial block.
These two modules are functionally equivalent.
*/
// module for 10-digit bitmap ROM
module digits10_case(digit, yofs, bits);
input [3:0] digit; // digit 0-9
input [2:0] yofs;... | 7.218525 |
module digitSeg (
input [3:0] bcd_i, // 输入BCD8421码
output a_o, // 数码管段选，低电平有效
output b_o,
output c_o,
output d_o,
output e_o,
output f_o,
output g_o
);
assign {a_o,b_o,c_o,d_o,e_o,f_o,g_o} =
(bcd_i == 4'd0) ? 7'b0000001 :
... | 6.949862 |
module digits_adapter (
input Clock,
input reset,
output hsync,
output vsync,
output HS_probe,
output VS_probe,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B
);
wire RED;
wire GREEN;
wire BLUE;
digits digits (
.Clock(Clock),
.reset(reset),
.hs... | 7.804755 |
module digits_rom (
//inputs
clk,
addr,
//outputs
data
);
(* rom_style = "block" *)
input wire clk;
input wire [7:0] addr;
output reg [7:0] data;
reg [7:0] addr_reg;
always @(posedge clk) addr_reg <= addr;
always @(*) begin
case (addr)
8'b00000001: data <= 8'b11111111;
... | 7.240472 |
module DigitToSeg (
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
mclk,
an,
dp,
seg
);
input wire [3:0] in1;
input wire [3:0] in2;
input wire [3:0] in3;
input wire [3:0] in4;
input wire [3:0] in5;
input wire [3:0] in6;
input wire [3:0] in7;
input wire [3:0] in8... | 6.993729 |
module DigitTrans (
output reg flicker,
output reg [7:0] sec,
input [4:0] lightTime
);
reg [4:0] temp;
always @(lightTime) begin
if (lightTime < 5'd5) begin
flicker <= 1;
end else begin
flicker <= 0;
end
if (lightTime > 5'd9) begin
sec[7:4] = 4'd1;
temp[4:0] = l... | 6.640783 |
module digit_bitmap (
address,
clock,
q
);
input [7:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
alts... | 6.637347 |
module digit_bitmap (
address,
clock,
q
);
input [7:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.637347 |
module digit_counter32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("digit_counter32A.vcd");
$dumpvars(0, digit_counter32A);
end
////// test bench
//////////////////////////////
////// circuit under test
... | 6.835046 |
module digit_counter32B;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#10000 $stop;
end
initial begin
$dumpfile("digit_counter32B.vcd");
$dumpvars(0, digit_counter32B);
end
////// test bench
//////////////////////////////
////// circuit under test
... | 6.835046 |
module digit_counter_ringA (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 stage... | 6.835046 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module digit_counter_ringB (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 stage... | 6.835046 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module digit_decoder (
input [3:0] number,
output reg [20:0] display_code
);
always @(*) begin
case (number)
4'd0: display_code <= 21'b111_101_101_101_101_101_111; // "0"
4'd1: display_code <= 21'b001_001_001_001_001_001_001; // "1"
4'd2: display_code <= 21'b111_100_100_111_001_001_111... | 8.148 |
module digit_driver (
input wire clk,
input wire rst_n,
input wire IOen,
input wire [11:0] IOaddr,
input wire [31:0] IOwdata,
output reg [ 7:0] led_en,
output reg led_ca,
output reg led_cb,
output reg led_cc,
output reg l... | 6.988305 |
module digit_pulse_generator (
output wire [35:0] digit_pulse,
input wire clk
);
reg [ 5:0] count = 6'b00_0000;
wire [35:0] outi;
genvar i;
genvar j;
always @(negedge clk) begin
if (count == 6'b01_1100) count <= 6'b11_1111;
else count <= count - 6'b00_0001;
end
assign outi[0] = (count... | 6.613954 |
module digit_pulse_generator_tb ();
reg clk = 1'b0;
wire [35:0] digit_pulse;
initial begin
$dumpfile("digit_pulse_generator.vcd");
$dumpvars(1, digit_pulse_generator_tb);
#2100 $finish;
end
digit_pulse_generator dpg (
.digit_pulse(digit_pulse),
.clk (clk)
);
alwa... | 6.613954 |
module digit_scan_decoder38 (
input [2:0] DIG
, output [7:0] OUT
);
reg [7:0] decoded;
always @(DIG) begin
case (DIG)
0: decoded <= 8'b00000001;
1: decoded <= 8'b00000010;
2: decoded <= 8'b00000100;
3: decoded <= 8'b00001000;
4: decoded <= 8'b00010000;
5: decoded ... | 7.523238 |
module digit_scan6 (
input CLK
, input ASYNC_RST_L
, input OEN
, input DIS_STATE
, input [23:0] DIG
, input [5:0] SEG_OEN
, output [5:0] SEG_SEL
, output [6:0] SEG_CODE
);
reg [2:0] scan_cnt;
reg [3:0] selected;
wire [7:0] decoded;
wire [6:0] seg_out;
wire seg_oen;
wire out... | 7.136628 |
module digit_select (
d1,
d2,
d3,
d4,
control,
digit
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] d1;
input [3:0] d2;... | 6.672326 |
module digit_selector (
input clk,
input rst,
output reg [3:0] digit_sel
);
reg [1:0] cnt;
initial cnt = 0;
// Select one digit at a time
always @(posedge clk, posedge rst) begin
if (rst) cnt <= 0;
case (cnt)
2'b00: digit_sel <= 4'b1110;
2'b01: digit_sel <= 4'b1101;
... | 6.773698 |
module digit_signal_generator (
input [1:0] dig_sel,
output reg [7:0] digit
);
always @(dig_sel)
case (dig_sel) // Designed for an 8 digit display with only 4 used
2'b00: digit = 8'b11111110;
2'b01: digit = 8'b11111101;
2'b10: digit = 8'b11111011;
2'b11: digit = 8'b11110111;
... | 8.047273 |
module digit_sprite (
//input
clk,
x,
y,
num,
en,
//output
rgb
);
input clk;
input en;
input [9:0] x;
input [9:0] y;
input [7:0] num;
output [7:0] rgb;
reg [7:0] addr = 0;
parameter pos_x = 0;
parameter pos_y = 0;
digits_rom rom_ (
.clk (clk),
.addr(a... | 6.509311 |
module digi_bench ();
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation file... | 6.881192 |
module to hold several channels of digitized ADC input.
// contains the ADC input, a circular buffer, and logic to
// send the data out to the ZYNQ
module digi_many_stream
#(parameter SIZE=8, WIDTH=12, CHAN=8)
(
input wire RST,
input wire CLK,
input wire [CHAN-1:0] DAVAIL,
input wire EOS,... | 7.593144 |
module digi_synth (
KEY,
SW,
GPIO_1,
CLOCK_50,
LEDG,
LEDR,
HEX0
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [1:0] GPIO_1;
output [7:0] LEDG, LEDR;
output [6:0] HEX0;
wire [2:0] note, s, z, y, selectOut;
wire [2:0] a, b, c, d, e, f, g, h;
wire clkOut, x;
... | 7.326962 |
module DIgi_tube (
input clk,
input rst,
input [15:0] data,
output reg [7:0] seg_data,
output reg [3:0] seg_cs
);
reg clk_500HZ; //一个新的脉冲信号，频率为50Hz
integer clk_cnt;
//产生一个50Hz的新脉冲信号
always @(posedge clk or posedge rst) begin
if (rst) begin
clk_500HZ <= 0;
clk_cnt <= ... | 6.852615 |
module digseg_driver (
input [3:0] data,
output reg [0:6] seg
);
always @(*) begin
case (data)
4'b0000: seg = 7'b1111110;
4'b0001: seg = 7'b0110000;
4'b0010: seg = 7'b1101101;
4'b0011: seg = 7'b1111001;
4'b0100: seg = 7'b0110011;
4'b0101: seg = 7'b1011011;
4'b011... | 6.56596 |
module DigSel (
input wire clk,
rst_n,
input wire [4:0] num5,
num4,
num3,
num2,
num1,
num0,
input wire [5:0] enb,
output reg [5:0] DIG,
output reg [4:0] num
);
parameter DIG1 = 3'b000;
parameter DIG2 = 3'b001;
parameter DIG3 = 3'b010;
parameter DIG4 = 3'b011;
param... | 7.180046 |
module digSwitch (
clk,
rst,
digit0,
digit1,
digit2,
digit3,
out,
enable
);
input clk, rst;
input [7:0] digit0, digit1, digit2, digit3;
output reg [7:0] out;
output reg [3:0] enable;
wire [7:0] digits[3:0];
assign digits[0] = digit0;
assign digits[1] = digit1;
assign digi... | 6.593843 |
module dig_clock_current (
input clk, //Clock with 1 Hz frequency
input reset, //active high reset
input mode, // default 1'b0 = 24 hr clock, 1'b1 = 12 hr clock
input [5:0] s_in,
input [5:0] m_in,
input [4:0] h_in,
output reg [5:0] seconds,
output reg [5:0] minutes,
output r... | 6.882089 |
module dig_clock_current_tb;
// Inputs
reg clk;
reg reset;
reg mode;
reg [5:0] s_in;
reg [5:0] m_in;
reg [4:0] h_in;
// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
dig_clock_current uut (
.clk(clk),
.reset(reset),
... | 6.882089 |
module DIG_decoder (
ctrl,
sel
);
input [1:0] ctrl;
output reg [5:0] sel;
always @(ctrl)
case (ctrl)
2'b00: sel = 6'b111000;
2'b01: sel = 6'b000111;
2'b10: sel = 6'b000000;
default: sel = 6'b111111;
endcase
endmodule
| 7.289636 |
module dig_control (
input dig_clk,
input rst,
output reg [2:0] dig_cnt
);
always @(posedge dig_clk or posedge rst) begin
if (rst == 1) dig_cnt <= 0;
else begin
if (dig_cnt < 7) dig_cnt <= dig_cnt + 1;
else dig_cnt <= 0;
end
end
endmodule
| 6.983331 |
module single_dig_driver (
input [3:0] num_in,
input rst,
input need_point,
output reg [7:0] seg_data
);
always @(*) begin
if (rst == 1) seg_data <= 8'b11111111;
else begin
case (num_in)
0: seg_data[6:0] <= 7'b1000000;
1: seg_data[6:0] <= 7'b1111001;
2: seg_data[... | 6.618289 |
module dig_regnize (
input w_en, // 写使能
input clk_w, // 写时钟
input clk_r, // 读时钟
input [18:0] addr_w, // 写地址
input [18:0] addr_r, // 读地址
input [15:0] dat_w, // 16位像素传入
output [11:0] dat_r, // 12位像素读出
output [1:0] n_node, // 竖直交点个数
output [1:0] m1_node_l, // 横左交点个数
... | 6.808202 |
module dig_volt (
input wire sys_clk, //系统时钟,50MHz
input wire sys_rst_n, //复位信号，低有效
input wire [7:0] ad_data, //AD输入数据
output wire ad_clk, //AD驱动时钟,最大支持20Mhz时钟
output wire stcp, //数据存储器时钟
output wire shcp, //移位寄存器时钟
output wire ds, //串行数据输入
output wire oe ... | 7.044512 |
module diila #(
parameter DATA_WIDTH = 96 // Has to be a multiplier of 4
) (
// WB
input wb_rst_i,
input wb_clk_i,
input [31:0] wb_dat_i,
input [23:2] wb_adr_i,
input [ 3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
i... | 6.661293 |
module DilateNode #(
parameter Width = 3,
parameter Height = 3
) (
input [Width*Height-1:0] element,
input [Width*Height-1:0] D,
output Q
);
wire [Width*Height-1:0] products;
assign Q = |products;
genvar l, c;
generate
for (l = 0; l < Height; l = l + 1) begin : _line_
for (c = 0... | 7.274933 |
module DilateTest;
parameter Width = 8;
parameter Height = 4;
reg [Width*Height-1:0] imageIn;
reg [8:0] mask;
wire [Width*Height-1:0] imageOut;
Dilate #(
.Width (Width),
.Height(Height)
) dilate (
.imageIn(imageIn),
.mask(mask),
.imageOut(imageOut)
);
initial begin
... | 6.704141 |
module dilation (
//global clock
input clk, //cmos video pixel clock
input rst_n, //global reset
//Image data prepred to be processd
input per_frame_vsync, //Prepared Image data vsync valid signal
input per_frame_href, //Prepared Image data href vaild signal
input per_frame_clken, //... | 6.985723 |
module dilation_filter_tb ();
reg clk;
reg rst_n;
reg i_pixel;
wire o_convolved_data;
wire tap0;
wire tap1;
wire [8:0] pixelCounter1;
wire [3:0] pixelRowCounter1;
wire [4:0] pixelStartUpCounter_check;
reg i_valid;
// wire o_valid;
localparam period = 20;
integer i;
// Clock Generation
... | 6.513259 |
module arbiter #(
parameter ARBITER_WIDTH =8,
parameter CHOISE = 1 // 0 blind round-robin and 1 true round robin
) (
clk,
reset,
request,
grant,
anyGrant
);
`LOG2
localparam N = ARBITER_WIDTH;
localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually
// I/O int... | 7.470414 |
module dinamic (
input wire clk, // System clock.
input wire clr, // Asynchronous reset.
input wire [9:0] x_numbers, // X position for actual numbers.
input wire [9:0] y_numbers, // Y position for actual numbers.
input wire inc_vel, // Increase velocity... | 8.214071 |
module dinoProject (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_... | 7.704813 |
module FSM3 (
clock,
resetn,
go,
jump,
finish_ground,
finish_draw,
finish_erase,
finish_tree_draw,
x,
y,
en_xy,
en_xy_tree,
en_delay,
right,
down,
draw_ground,
draw_tree,
draw,
plot,
is_move,
current_state,
finish_delay,
en_eras... | 6.979795 |
module LFSR (
clk,
resetn,
out
);
input clk;
input resetn;
output [4:0] out;
wire xor_out;
reg [12:0] random_reg;
reg [3:0] current_reg;
assign xor_out = random_reg[12] ^ random_reg[3] ^ random_reg[2] ^ random_reg[0];
always @(posedge clk) begin
if (!resetn) begin
random_reg <= ... | 6.729795 |
module ALUControl (
input io_aluop,
input io_itype,
input [6:0] io_funct7,
input [2:0] io_funct3,
output [3:0] io_operation
);
wire _T_1 = io_funct7 == 7'h0; // @[alucontrol.scala 32:35]
wire [2:0] _GEN_0 = io_itype | io_funct7 == 7'h0 ? 3'h7 : 3'h4; // @[alucontrol.scala 32:53 ... | 8.639118 |
module ALU (
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy; // @[alu.scala 26:28]
wire [31:0] _T_3 = io_inputx | io_inputy; // @[alu.scala 29:28]
wire [31:0] _T_6 = io_inputx + io_inputy; // @[al... | 7.960621 |
module Adder (
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy; // @[helpers.scala 23:26]
endmodule
| 7.642138 |
module NextPC (
input io_branch,
input io_jal,
input io_jalr,
input [31:0] io_inputx,
input [31:0] io_inputy,
input [ 2:0] io_funct3,
input [31:0] io_pc,
input [31:0] io_imm,
output [31:0] io_nextpc,
output io_taken
);
wire _GEN_0 = io_funct3... | 7.306707 |
module HazardUnitBP (
input [4:0] io_rs1,
input [4:0] io_rs2,
input io_idex_memread,
input [4:0] io_idex_rd,
input io_exmem_taken,
output [1:0] io_pcSel,
output io_if_id_stall,
output io_if_id_flush,
output io_id_ex_flush,
output io_ex_mem... | 6.645377 |
module StageReg (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_pc,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_pc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0]... | 7.496723 |
module StageReg_1 (
input clock,
input reset,
input [31:0] io_in_pc,
input [31:0] io_in_instruction,
input [31:0] io_in_sextImm,
input [31:0] io_in_readdata1,
input [31:0] io_in_readdata2,
input io_flush,
output [31:0] io_data_pc,
output [31:0] io_dat... | 7.20915 |
module StageReg_4 (
input clock,
input reset,
input [1:0] io_in_mem_ctrl_memop,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
output [1:0] io_data_mem_ctrl_memop,
output io_data_wb_ctrl_toreg,
output io_data_w... | 6.679582 |
module StageReg_5 (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_readdata,
input [31:0] io_in_ex_result,
output [31:0] io_data_instruction,
output [31:0] io_data_readdata,
output [31:0] io_data_ex_result
);
`ifdef RANDOMIZE_REG_INIT
re... | 7.658383 |
module StageReg_6 (
input clock,
input reset,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg reg_wb_ctrl_toreg;... | 7.016389 |
module ICombinMemPort (
input [31:0] io_pipeline_address,
output [31:0] io_pipeline_instruction,
output [31:0] io_bus_request_bits_address,
input [31:0] io_bus_response_bits_data
);
assign io_pipeline_instruction = io_bus_response_bits_data; // @[memory-combin-ports.scala 33:27]
assign io_bus_req... | 8.568869 |
module ALUControl (
input io_aluop,
input io_itype,
input [6:0] io_funct7,
input [2:0] io_funct3,
output [3:0] io_operation
);
wire _T_1 = io_funct7 == 7'h0; // @[alucontrol.scala 32:35]
wire [2:0] _GEN_0 = io_itype | io_funct7 == 7'h0 ? 3'h7 : 3'h4; // @[alucontrol.scala 32:53 ... | 8.639118 |
module ALU (
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy; // @[alu.scala 26:28]
wire [31:0] _T_3 = io_inputx | io_inputy; // @[alu.scala 29:28]
wire [31:0] _T_6 = io_inputx + io_inputy; // @[al... | 7.960621 |
module Adder (
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy; // @[helpers.scala 23:26]
endmodule
| 7.642138 |
module NextPC (
input io_branch,
input io_jal,
input io_jalr,
input [31:0] io_inputx,
input [31:0] io_inputy,
input [ 2:0] io_funct3,
input [31:0] io_pc,
input [31:0] io_imm,
output [31:0] io_nextpc,
output io_taken
);
wire _GEN_0 = io_funct3... | 7.306707 |
module HazardUnitBP (
input [4:0] io_rs1,
input [4:0] io_rs2,
input io_idex_memread,
input [4:0] io_idex_rd,
input io_exmem_taken,
output [1:0] io_pcSel,
output io_if_id_stall,
output io_if_id_flush,
output io_id_ex_flush,
output io_ex_mem... | 6.645377 |
module StageReg (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_pc,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_pc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0]... | 7.496723 |
module StageReg_1 (
input clock,
input reset,
input [31:0] io_in_pc,
input [31:0] io_in_instruction,
input [31:0] io_in_sextImm,
input [31:0] io_in_readdata1,
input [31:0] io_in_readdata2,
input io_flush,
output [31:0] io_data_pc,
output [31:0] io_dat... | 7.20915 |
module StageReg_4 (
input clock,
input reset,
input [1:0] io_in_mem_ctrl_memop,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
output [1:0] io_data_mem_ctrl_memop,
output io_data_wb_ctrl_toreg,
output io_data_w... | 6.679582 |
module StageReg_5 (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_readdata,
input [31:0] io_in_ex_result,
output [31:0] io_data_instruction,
output [31:0] io_data_readdata,
output [31:0] io_data_ex_result
);
`ifdef RANDOMIZE_REG_INIT
re... | 7.658383 |
module StageReg_6 (
input clock,
input reset,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg reg_wb_ctrl_toreg;... | 7.016389 |
module ICombinMemPort (
input [31:0] io_pipeline_address,
output [31:0] io_pipeline_instruction,
output [31:0] io_bus_request_bits_address,
input [31:0] io_bus_response_bits_data
);
assign io_pipeline_instruction = io_bus_response_bits_data; // @[memory-combin-ports.scala 33:27]
assign io_bus_req... | 8.568869 |
module cr2_lock (
m__i__stb,
a__i__stb,
w__i__stb,
d__o__stall,
x__i__stb
);
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _00_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _01_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _02_;
(* src =... | 6.985725 |
module cr4_lock (
m__i__stb,
a__i__stb,
w__i__stb,
d__o__stall,
x__i__stb
);
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _00_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _01_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _02_;
(* src =... | 7.0355 |
module cr5_lock (
m__i__stb,
a__i__stb,
w__i__stb,
d__o__stall,
x__i__stb
);
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _00_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _01_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _02_;
(* src =... | 6.524798 |
module cr7_lock (
m__i__stb,
a__i__stb,
w__i__stb,
d__o__stall,
x__i__stb
);
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _00_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _01_;
(* src = "/home/jf/src/dinofly/dinofly/reg/cr.py:46" *)
wire _02_;
(* src =... | 6.534176 |
module x_sh_gran (
o,
i
);
wire [4:0] _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire [4:0] _06_;
wire _07_;
(* src = "/home/jf/.cache/pypoetry/virtualenvs/power-fv-wTw7_vpu-py3.10/lib/python3.10/site-packages/amaranth/lib/coding.py:109" *)
input [2:0] i;
wire [2:0] i;
... | 7.261094 |
module DinoFSM (
/*input wire clk,*/
input wire rst,
input wire animationClk,
input wire [1:0] gameState,
input wire Airborne,
input wire onGround,
input wire isDuck,
output wire [3:0] DinoMovementSelect
);
reg [3:0] select;
always @(*) begin
if (rst) begin
select <= 4'... | 7.202632 |
module dinogame (
input wire jump_in,
input wire halt_in,
input wire debug_in,
output wire vga_hsync,
output wire vga_vsync,
output wire [3:0] vga_red,
output wire [3:0] vga_green,
output wire [3:0] vga_blue,
output wire vga_pixel,
`ifdef DINO_CONFIG
output wire dbg_reset,
... | 7.689669 |
module dinoProject (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_... | 7.704813 |
module FSM3 (
clock,
resetn,
go,
jump,
finish_ground,
finish_draw,
finish_erase,
finish_tree_draw,
finish_bird,
finish_death,
x,
y,
en_xy,
en_xy_tree,
en_delay,
en_bird,
right,
down,
draw_ground,
draw_tree,
draw_bird,
draw,
draw... | 6.979795 |
module LFSR (
clk,
resetn,
out
);
input clk;
input resetn;
output [4:0] out;
wire xor_out;
reg [12:0] random_reg;
reg [3:0] current_reg;
assign xor_out = random_reg[12] ^ random_reg[3] ^ random_reg[2] ^ random_reg[0];
always @(posedge clk) begin
if (!resetn) begin
random_reg <= ... | 6.729795 |
module StageReg_3 (
input clock,
input reset,
input [31:0] io_in_ex_result,
input [31:0] io_in_mem_writedata,
input [31:0] io_in_instruction,
input [31:0] io_in_next_pc,
input io_in_taken,
input io_flush,
output [31:0] io_data_ex_result,
output... | 7.51311 |
module ALU (
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy;
wire [31:0] _T_3 = io_inputx | io_inputy;
wire [31:0] _T_6 = io_inputx + io_inputy;
wire [31:0] _T_9 = io_inputx - io_inputy;
wire [31... | 7.960621 |
module Adder (
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
assign io_result = io_inputx + io_inputy;
endmodule
| 7.642138 |
module StageReg_4 (
input clock,
input reset,
input [1:0] io_in_mem_ctrl_memop,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
input io_flush,
output [1:0] io_data_mem_ctrl_memop,
output io_data_wb_ctrl_toreg,
output io_data_w... | 6.679582 |
module ALUControl (
input io_aluop,
input io_itype,
input [6:0] io_funct7,
input [2:0] io_funct3,
output [3:0] io_operation
);
wire [2:0] _GEN_0 = io_itype | io_funct7 == 7'h0 ? 3'h7 : 3'h4; // @[]
wire [1:0] _GEN_1 = io_funct7 == 7'h0 ? 2'h2 : 2'h3; // @[]
wire [2:0] _GEN_2 ... | 8.639118 |
module HazardUnitBP (
input [4:0] io_rs1,
input [4:0] io_rs2,
input io_idex_memread,
input [4:0] io_idex_rd,
input io_exmem_taken,
output [1:0] io_pcSel,
output io_if_id_stall,
output io_if_id_flush,
output io_id_ex_flush,
output io_ex_mem... | 6.645377 |
module StageReg_1 (
input clock,
input reset,
input [31:0] io_in_pc,
input [31:0] io_in_instruction,
input [31:0] io_in_sextImm,
input [31:0] io_in_readdata1,
input [31:0] io_in_readdata2,
input io_flush,
output [31:0] io_data_pc,
output [31:0] io_dat... | 7.20915 |
module StageReg_5 (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_readdata,
input [31:0] io_in_ex_result,
output [31:0] io_data_instruction,
output [31:0] io_data_readdata,
output [31:0] io_data_ex_result
);
`ifdef RANDOMIZE_REG_INIT
re... | 7.658383 |
module StageReg_6 (
input clock,
input reset,
input io_in_wb_ctrl_toreg,
input io_in_wb_ctrl_regwrite,
output io_data_wb_ctrl_toreg,
output io_data_wb_ctrl_regwrite
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg reg_wb_ctrl_toreg;... | 7.016389 |
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