code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module StageReg (
input clock,
input reset,
input [31:0] io_in_instruction,
input [31:0] io_in_pc,
input io_flush,
input io_valid,
output [31:0] io_data_instruction,
output [31:0] io_data_pc
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0]... | 7.496723 |
module NextPC (
input io_branch,
input io_jal,
input io_jalr,
input [31:0] io_inputx,
input [31:0] io_inputy,
input [ 2:0] io_funct3,
input [31:0] io_pc,
input [31:0] io_imm,
output [31:0] io_nextpc,
output io_taken
);
wire _GEN_1 = io_funct... | 7.306707 |
module DCombinMemPort(
input clock,
input reset,
input [31:0] io_pipeline_address,
input io_pipeline_valid,
input [31:0] io_pipeline_writedata,
input io_pipeline_memread,
input io_pipeline_memwrite,
input [1:0] io_pipeline_maskmode,
input io_pipeline... | 6.870769 |
module ICombinMemPort (
input [31:0] io_pipeline_address,
output [31:0] io_pipeline_instruction,
output [31:0] io_bus_request_bits_address,
input [31:0] io_bus_response_bits_data
);
assign io_pipeline_instruction = io_bus_response_bits_data;
assign io_bus_request_bits_address = io_pipeline_address... | 8.568869 |
module dinosprite (
input wire halt,
output reg sprite,
input wire clk,
input wire sys_rst
);
localparam TOGGLE_DIVIDER = 3000000;
reg [24:0] ctr;
always @(posedge clk) begin
if (sys_rst) begin
ctr <= 0;
sprite <= 0;
end else if (!halt) begin
ctr <= ctr + 1;
i... | 7.649391 |
module Dinout (
din,
z,
clk,
dout,
dinout
);
input [7:0] din;
input z;
input clk;
output [7:0] dout;
inout [7:0] dinout;
reg [7:0] dout;
reg [7:0] din_reg;
assign dinout = (!z) ? din_reg : 8'bz;
always @(posedge clk) begin
if (!z) din_reg = din;
else dout = dinout;
end... | 6.860499 |
module dino_jump
// (
// CLOCK_50, // On Board 50 MHz
// // Your inputs and outputs here
// KEY,
// SW,
// // The ports below are for the VGA output. Do not change.
// VGA_CLK, // VGA Clock
// VGA_HS, // VGA H_SYNC
// VGA_VS, // VGA V_SYNC
// VGA_BLANK_N, // VGA BLANK... | 9.210884 |
module rate_counter (
enable,
clk,
reset,
out
);
input clk, reset, enable;
output reg [1:0] out;
always @(posedge clk) begin
if (~reset) out <= 2'b11;
else if (enable) begin
if (out == 2'b0) out <= 2'b11;
else out <= out - 1'b1;
end
end
endmodule
| 6.605756 |
module delay_counter (
enable,
clk,
reset,
out,
q
);
input enable, clk, reset;
// 1/60 second equal to 60hz
// 50Mhz/60hz = 833333.333
// ceil(log2(833333.333)) = 20
output reg [19:0] out;
output reg q;
always @(posedge clk) begin
if (~reset) begin
out <= 20'd0;
q <... | 6.853164 |
module frame_counter (
enable,
clk,
reset,
out
);
input enable, clk, reset;
output reg [3:0] out;
always @(posedge clk) begin
if (~reset) out <= 4'b0;
else if (enable) begin
if (out == 4'd7) out <= 4'b0;
else out <= out + 1'b1;
end
end
endmodule
| 6.859338 |
module dino_datapath (
enable,
clk,
load_colour,
reset,
jump_sig,
x_out,
y_out,
c_out
);
input enable, clk, reset, load_colour, jump_sig;
output [7:0] x_out;
output reg [6:0] y_out;
output [2:0] c_out;
wire [19:0] delay_value;
wire delay_out;
wire [3:0] frame_out;
wire ... | 6.564018 |
module dino_control (
pause,
enable,
clk,
reset,
go,
load_colour,
plot
);
input clk, reset, go, pause;
output reg enable, plot, load_colour;
reg [2:0] current_state, next_state;
localparam S_LOAD_DINO = 3'd0, S_LOAD_DINO_WAIT = 3'd1, S_JUMP_DINO = 3'd2, PAUSE_STATE = 3'd3;
alwa... | 7.919098 |
module DinProduce (
rst,
clk32,
cosine
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
output signed [5:0] cosine; //延时处理后的输出数据
//对系统时钟分频处理，得到4分频的时钟信号
reg [1:0] c;
reg clk8;
always @(posedge clk32 or posedge rst)
if (rst) begin
c <= 0;
clk8 <= 0;
end else begi... | 7.621577 |
module din_syn (
input clk_in,
input [450:0]data_reg, // Data Register, 451 bits
input trig, // Trigger Signal
input dump, // Dump Signal (not implemented)
input [1:0]clr_mode, // 00 -> Normal
// 11 -> All zeros
// 01 -> All ones
output clk, // .clk(GPIO_0_D[0]), // CLOCK
o... | 7.098237 |
module DIN_SYN_vJTAG (
input clk_in,
input [619:0] data_reg, // Data Register, 451 bits
input trig, // Trigger Signal
input clr_2_one,
// 11 -> All zeros
// 01 -> All ones
input clr_mode,
output clk, // .clk(GPIO_0_D[0]), // CLOCK
output din, // .din(GPIO_0_D[1]), // Digital Inp... | 6.654062 |
module DipSwitch (
input Addr,
input [7:0] In0,
input [7:0] In1,
input [7:0] In2,
input [7:0] In3,
input [7:0] In4,
input [7:0] In5,
input [7:0] In6,
input [7:0] In7,
output [31:0] DOut
);
assign DOut = Addr ? ~{In7, In6, In5, In4} : ~{In3, In2, In1, In0};
endmodule
| 8.396559 |
module DipSwitchDriver ( //implements ROM
input [7:0] dip_switch0,
input [7:0] dip_switch1,
input [7:0] dip_switch2,
input [7:0] dip_switch3,
input [7:0] dip_switch4,
input [7:0] dip_switch5,
input [7:0] dip_switch6,
input [7:0] dip_switch7,
input [31:0] addr,
output [31:0] da... | 7.393876 |
module dip_led_test (
clk,
rst_n,
dips_in,
leds_out
);
input clk;
input rst_n;
input [3:0] dips_in;
output [7:0] leds_out;
/******************************/
reg [7:0] leds;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) leds <= 8'b0111_1111;
else leds <= {4'b1111, dips... | 7.220221 |
module dip_switch_driver (
input clk,
input reset,
input [7:0] Addr,
output [31:0] Dout,
input [7:0] dip_switch0,
input [7:0] dip_switch1,
input [7:0] dip_switch2,
input [7:0] dip_switch3,
input [7:0] dip_switch4,
input [7:0] dip_switch5,
input [7:0] dip_switch6,
input [7... | 6.578311 |
module DirectCache #(
parameter Width = 8,
parameter AddressWidth = 8,
parameter CacheAddressWidth = 4,
parameter PartialAddressWidth = AddressWidth - CacheAddressWidth
) (
input clk,
input rst,
input we,
output hit,
output miss,
input [AddressWidth-1:0] raddr,
output [Width... | 6.773824 |
module direction (
input CLK,
input [1:0] dir_in,
output reg dir_out1,
output reg dir_out2
);
always @(posedge CLK) begin
if (dir_in == 2'b00) begin
dir_out1 <= 1'b1;
dir_out2 <= 1'b0;
end else if (dir_in == 2'b01) begin
dir_out1 <= 1'b0;
dir_out2 <= 1'b1;
end else ... | 6.633442 |
module Directions (
input [1:0] addr,
input [3:0] line,
input id,
output reg dir
);
always @(*) begin
case (addr)
2'd00: dir = 1'b0;
2'd01: begin
if (line == 4'd0010) begin
dir = 1'b1;
end else if (line > 4'd0010) begin
dir = 1'b0;
end else ... | 7.378275 |
module.
// Revision:
// Revision 0.01 - File Created
//////////////////////////////////////////////////////////////////////////////////
module direction_ganglion(clk, dist, start, dir, colrcode, flat);
input clk, start, dir;
input [99:0] dist;
output reg colrcode;
output reg [6:0] flat;
reg [3:0] state, nextstate... | 6.615575 |
module direction_ram (
output reg [`DIRECTION_WIDTH-1:0] q,
input [`DIRECTION_WIDTH-1:0] d,
input [`ADDRESS_WIDTH-1:0] write_address,
read_address,
input we,
clk
);
reg [`DIRECTION_WIDTH-1:0] mem[`MEM_SIZE-1:0];
always @(posedge clk) begin
if (we) mem[write_address] <= d;
q <= mem[... | 6.993624 |
module DirectMappedDataCache (
clk,
rst,
start,
done,
address,
outData,
hitNum
);
input clk, rst, start;
input [14:0] address;
output done;
output [15:0] hitNum;
output [31:0] outData;
wire hit, wrEn;
Datapath DP (
.clk(clk),
.rst(rst),
.wrEn(wrEn),
.a... | 6.509071 |
module shows how pin assignments can be made using constraints
* directly added to the top-level module of your design using the
* Verilog Attributes (* *) command.
*
* These are made using the following command placed before each port:
* (* chip_pin = "pin"*) direction portName
*
* The constraint must be on... | 9.031058 |
module clkbuf
(
`INPUT(clk_in, 1),
`OUTPUT(clk_out, 1)
);
assign clk_out = clk_in;
endmodule
| 7.017282 |
module direct_instruction (
clk,
reset,
released,
ascii,
data_ready,
read,
a_left,
m_switch,
w_up,
s_down,
d_right,
enter_next,
esc_retry,
backspace_retract
);
input clk;
input reset;
input released;
input [7:0] ascii;
input data_ready;
output read;
... | 7.324971 |
module direct_io_assign (
input signed [2:0] foo
, output reg signed [2:0] bar
);
always_comb begin
end
always_comb begin
bar = foo;
end
endmodule
| 8.993295 |
module direct_transceiver_tester (
input wire CLOCK_50MHZ,
input wire [19:0] GPIO_IN,
output [6:0] DIG,
output [5:0] SEL
);
wire CLOCK_SWEEP;
clock_divider CLK_DIV_BLOCK (
.CLOCK_50MHZ(CLOCK_50MHZ),
.CLOCK_500HZ(CLOCK_SWEEP)
);
sseg_sweeper SSEG_SWPR (
.CLOCK_SWEEP(CLOCK_SWE... | 7.429621 |
module DIRP(
input clk,
input rst,
input is_br_i,
input [`BR_STATE_W-1:0] reslv_i,
input is_taken_i,
input [`BHR_W-1:0] recrv_BHR_i,
output pred_o,
output [`BHR_W-1:0] save_BHR_o
);
P_STATE PHT [`PHT_NUM-1:0]; // Use bimodal/saturation counter.
logic [`BHR_W-1:0] BHR;
logic ... | 6.708803 |
module dirty_block #(
parameter DW = 32,
parameter DP = 16
) (
input push,
input [DW-1:0] addr_i,
input pop,
output [DW-1:0] addr_o,
output empty,
output full,
input CLK,
input RSTn
);
localparam CW = $clog2(DP);
wire [CW-1:0] index;
wire [CW-1:0] index_push;
wire ... | 7.367563 |
module DIS (
flag,
display,
head,
clk,
rst,
addr,
data
);
input clk, rst;
input [3:0] head;
input flag;
output reg [15:0] display;
reg [3:0] state;
parameter s0 = 4'd0, s1 = 4'd1, s2 = 4'd2, s3 = 4'd3,
s4 = 4'd4, s5 = 4'd5, s6 = 4'd6, s7 = 4'd7, start =... | 7.236862 |
module for memory addresses; also feeds data to the memory retire unit
module lsq_req_ram(
clk,
rst,
read_addr,read_data,read_clkEn,
write0_addr,write0_data,write0_wen,
write1_addr,write1_data,write1_wen,
write2_addr,write2_data,write2_wen,
write3_addr,write3_data,write3_wen,
write4_addr,write4_data,... | 6.754236 |
module lsq_req_block (
clk,
rst,
read_clkEn,
read_addr,
read0_data,
read1_data,
read2_data,
read3_data,
read4_data,
read5_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,... | 7.026253 |
module lsq_ex_ram (
clk,
rst,
read_addr,
read_data,
read_clkEn,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,
write3_addr,
write3_data,
write3_wen,
write4_addr,
write4_data,... | 8.487053 |
module lsq_ex_block (
clk,
rst,
read_clkEn,
read_addr,
read0_data,
read1_data,
read2_data,
read3_data,
read4_data,
read5_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,
... | 8.084048 |
module lsq_shared_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = `lsqshare_width;
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_add... | 8.719191 |
module lsq_sharedB_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = `lsqshare_width;
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_ad... | 8.207565 |
module lsq_pend_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr0,
write_data0,
write_wen0,
write_addr1,
write_data1,
write_wen1
);
localparam DATA_WIDTH = `lsqpend_width;
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
input clk;
input rst;
i... | 8.38463 |
module.
* Philip Pemberton, 2012.
*
* This is a complete rewrite of the original DiscFerret MDR module, and fixes
* a number of race conditions and ambiguities which caused data corruption
* issues.
*
* This version both has a Verilog testbench, and has been tested against it.
* Acquisition is proven to work (u... | 6.735236 |
module discrete_dffn (
clk_ni,
d_i,
d_o
);
input wire clk_ni;
input wire d_i;
output reg d_o;
wire int_clk;
assign int_clk = ~clk_ni;
always @(posedge int_clk) begin
d_o <= d_i;
end
endmodule
| 6.88113 |
module disCtrl (
input clk,
input reset,
input K,
input [4:0] L,
input S,
input [7:0] data_in,
input rd_in,
output reg [7:0] saved_data_in,
output reg [4:0] saved_L,
output reg saved_K,
output rd_in_s4,
output reg COMPLS6,
output reg COMPLS4,
output rd_out
);
wi... | 6.599547 |
module discussion_tb;
// Inputs
reg clk;
reg Reset;
reg LoadInstructions;
reg [31:0] Instruction;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
CPU uut (
.out(out),
.clk(clk),
.Reset(Reset),
.LoadInstructions(LoadInstructions),
.Instruction(Instr... | 6.534714 |
module disdiv (
input inclk,
output outclk
);
reg [35:0] q;
always @(posedge inclk) q <= q + 1;
assign outclk = q[17]; //around 3kHz
endmodule
| 7.228994 |
module DisFIFO (
rst,
di, clkw, we,
do, clkr, re,
empty_flag,
full_flag
);
input rst;
input [7:0] di;
input clkw, we;
input clkr,re;
output [15:0] do;
output empty_flag;
output full_flag;
EF2_LOGIC_FIFO #(
.DATA_WIDTH_W(8),
.DATA_WIDTH_R(16),
.DATA_DEPTH_W(2048),
.DATA_DEPTH_R(1024),
.ENDIAN("BIG"... | 6.823199 |
module disjoint_switch_box #(
// The number of pairs of in and out wires each side.
parameter W = 8,
// There are 8 switches in each of the switch_box_element_ones.
parameter CONF_WIDTH = 8 * W
) (
input clk,
input rst,
input cset,
input... | 6.805371 |
module disjoint_switch_box_tb;
localparam W = 8; // WW * WN
reg clk = 0;
always #10 clk = ~clk;
reg [W-1:0] ni, ei, si, wi;
wire [W-1:0] no, eo, so, wo;
reg [W*8-1:0] c;
reg rst, cset;
disjoint_switch_box #(
.W(W)
) dut (
.clk(clk),
.rst(rst),
.cset(cset),
.north_in(... | 6.805371 |
module disk_uc
// all these parameters need to be set
#(
parameter uDEV = 0,
DEFAULT_ADDR = 0,
DEFAULT_INT_VEC = 0,
DEFAULT_INT_PRI = 0
) (
input init,
input qclk,
// The internal micro-controller bus
input [15:0] uADDR,
inout [15:0] uDATA,
input uWRITE,
... | 7.758518 |
module diskdrives #(
parameter NR_DISK = 2,
parameter SHARED_FDC = 0
) (
// from/to ctrl-module
input wire [7:0] disk_data_in,
output wire [7:0] disk_data_out,
output wire [31:0] disk_sr,
input wire [31:0] disk_cr,
input wire disk_data_clkout,
input wire disk_data_clkin,
input wi... | 7.109124 |
module disk_drive (
input wire clk,
input wire rst_n,
input wire [15:0] a,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe
);
assign dout = 8'hFF;
assign oe = (a[15:12] == 3'b001 && a[1] == 1'b0 && iorq_n == 1'b... | 6.740605 |
module DisMem (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [479:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [479:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVE... | 6.628162 |
module disp (
input clk,
input rst_n,
input [5:0] state_no,
output [3:0] dig,
output [7:0] seg
);
parameter IDLE = 6'd0;
parameter JUMP = 6'd1;
parameter SPEED = 6'd2;
parameter LEFT = 6'd3;
parameter RIGHT = 6'd4;
// indicate four seg
reg [5:0] num_0;
reg [5:0] num_1;
reg [5:... | 6.654347 |
module disp7 (
input clk_i,
input [31:0] number_i, //4x 7-seg data cluster
output reg [7:0] seg_o,
output reg [7:0] an_o
);
reg [16:0] div = 17'b0; //frequency divider
always @(posedge clk_i) div <= div + 1'b1;
always @(div[16:14], number_i) begin //Sweeps values to be displayed
//for e... | 6.839853 |
module Disp7segCntr (
clk,
dir_up,
clear,
AN,
CA,
sclk
);
input clk, clear, dir_up;
output reg [7:0] CA; //msb for dp
output reg [3:0] AN;
output sclk;
reg [ 2:0] Q;
reg [24:0] counter = 0; // for slowin clock
assign sclk = counter[24];
always @(posedge clk) count <= count ... | 6.550856 |
module disp7seg_clockgen (
clock,
reset,
clocken
);
input clock, reset;
output clocken;
reg clocken;
reg [17:0] clkdiv;
always @(posedge clock or posedge reset) begin
if (reset) begin
clkdiv <= 18'b0;
clocken <= 1'b0;
end else begin
if (clkdiv == 18'd200000) begin
... | 6.875379 |
module Disp8Num (
input wire clk,
rst,
input wire [31:0] num, // all 8 numbers to display //
input wire [7:0] point, // point to display // 1: activated
input wire [7:0] en, // "enable" for all 8 displays // 0: enable
// the output wires should be directly connected to the display hardware... | 8.177365 |
module DisplayDestAndCurr (
clock,
displayMode,
dest,
curr,
tube,
com
);
input clock;
input displayMode;
input [7:0] dest, curr;
output reg [7:0] tube;
output reg [3:0] com;
reg [1:0] comState;
reg [7:0] displayDest, displayCurr;
wire displayClock;
ClockGenerator#(
.UPPE... | 6.885154 |
module disparity_generator #(
parameter WIDTH = 320,
HEIGHT = 240,
START_UP_DELAY = 100,
HSYNC_DELAY = 160,
VALUE = 100
) (
input HCLK,
input [3:0] left_in,
input [3:0] right_in,
output [3:0] dOUT,
output [16:0] dOUT_addr,
output [16:0] left_right_addr,
output reg ctrl... | 7.339964 |
module MemoryDevice (
DataBus
);
inout [7:0] DataBus;
assign DataBus = 8'h8D; // STA abs
endmodule
| 6.720058 |
module DispBCD (
input [31:0] clkdiv,
input [31:0] hex,
output [ 3:0] sout
);
wire [39:0] bcd;
Seg7Device segDevice (
.clkIO(clkdiv[3]),
.clkScan(clkdiv[15:14]),
.clkBlink(clkdiv[25]),
.data(bcd[31:0]),
.point(8'h0),
.LES(8'h0),
.sout(sout)
);
/*
assign... | 7.284979 |
module dispController (
clock,
reset,
charRgbDepth,
bkRgbDepth,
flashClk,
moveSpeed,
charOffset,
romByte,
readEn,
addOffset,
vgaRGB,
vgaHsync,
vgaVsync
);
input clock;
input reset;
input flashClk;
input [8:0] charRgbDepth;
input [8:0] bkRgbDepth;
input [... | 7.168044 |
module dispdecoder (
data_in,
disp_select,
dp_s1hz,
dp_s10hz,
dp_s100hz,
Q5,
Q4,
Q3,
Q2,
Q1,
Q0,
counter_out,
data_out,
dp
);
output [6:0] data_out;
output dp;
input [3:0] data_in;
input [2:0] disp_select;
input dp_s1hz, dp_s10hz, dp_s100hz;
input [3:... | 6.921858 |
module DISPL (
input clk,
output wire [3:0] AN, //
input [7:0] HB,
output wire [6:0] seg, //
input [7:0] LB,
output wire seg_P, //
output reg ce1ms = 0
);
wire [15:0] dat = {HB, LB};
parameter Fclk = 50000; //50000 kHz
parameter F1kHz = 1; //1 kHz
wire [1:0] ptr_P = 2'b10; /... | 8.034761 |
module display_ctrl #(
parameter cdbits = 18, // clock divider bits
// Clock freq. bits
// 50MHz 18
// 100MHz 19
// 200MHz 20
// 400MHz 21
... | 7.314885 |
module display16bits (
input wire clk,
input wire [15:0] digit,
output reg [ 3:0] node,
output reg [ 7:0] segment
);
reg [ 3:0] code = 4'b0;
reg [15:0] count = 15'b0;
always @(posedge clk) begin
case (count[15:14])
2'b00: begin
node <= 4'b1110;
code <= digit[3:... | 7.155735 |
module display16bits (
input wire clk,
input wire [15:0] digit, //ʾ
output reg [ 3:0] node, //4ܵλѡ
output reg [ 7:0] segment
); //߶+С
reg [ 3:0] code = 4'b0;
reg [15:0] count = 16'b0;
always @(posedge clk) begin
case (count[15:14])
//(count[1:0])IJͬƵ
2'b00: begi... | 7.155735 |
module Display2VGA (
Clock,
DisplayAddr,
CursorEnable,
DisplayChar,
PixelOut,
HSync,
VSync
);
input Clock;
output [11:0] DisplayAddr;
input CursorEnable;
input [7:0] DisplayChar;
output PixelOut;
output reg HSync, VSync;
reg divisorCounter;
wire inFrame;
wire pixelVa... | 6.852963 |
module display3 (
offset,
rgb_en,
clk_lcd,
flagv,
flagh,
data_RED,
data_BLUE,
data_GREEN,
hcount_reg,
Vcount_reg
);
input clk_lcd, flagh, flagv, rgb_en;
input [9:0] hcount_reg, offset;
input [8:0] Vcount_reg;
output reg data_RED, data_BLUE;
output reg data_GREEN;
reg... | 6.817633 |
module display32bits (
clk,
disp_num,
digit_anode,
segment
);
input clk;
input [31:0] disp_num;
output [7:0] digit_anode;
output [7:0] segment;
reg [ 7:0] digit_anode;
reg [ 7:0] segment;
reg [12:0] cnt = 0;
wire [31:0] disp_num;
reg [ 3:0] num;
always @(posedge clk) begin
... | 7.840529 |
module display32bits (
clk,
disp_num,
digit_anode,
segment
);
input clk;
input [31:0] disp_num;
output [7:0] digit_anode;
output [7:0] segment;
reg [ 7:0] digit_anode;
reg [ 7:0] segment;
reg [12:0] cnt = 0;
wire [31:0] disp_num;
reg [ 3:0] num;
always @(posedge clk) begin
c... | 7.840529 |
module display7seg (
dp,
dado,
leds
);
input dp;
input [3:0] dado;
output reg [7:0] leds;
endmodule
| 7.450263 |
module display7segmentos (
numero,
outDisplay
);
input [3:0] numero;
output reg [6:0] outDisplay;
always @(*)
case (numero)
4'b0000: outDisplay = ~7'b1111110; //0
4'b0001: outDisplay = ~7'b0110000; //1
4'b0010: outDisplay = ~7'b1101101; //2
4'b0011: outDisplay = ~7'b111100... | 7.240202 |
module display7seg_testbench ();
reg [3:0] A_tb;
wire [6:0] Y_tb;
display7seg_main UTT (
.A(A_tb),
.Y(Y_tb)
);
initial begin
A_tb = 4'b0000;
#10;
A_tb = 4'b0001;
#10;
A_tb = 4'b0010;
#10;
A_tb = 4'b0011;
#10;
A_tb = 4'b0100;
#10;
A_tb = 4'b0101;
... | 6.93464 |
module Display7_Interface (
output [6:0] HEX0_D,
HEX1_D,
HEX2_D,
HEX3_D,
HEX4_D,
HEX5_D,
HEX6_D,
HEX7_D, // Displays Hex
output HEX0_DP,
HEX1_DP,
HEX2_DP,
HEX3_DP,
HEX4_DP,
HEX5_DP,
HEX6_DP,
HEX7_DP, // Displays Dot Point
input [31:0] Output
);
as... | 6.725497 |
module display7_out (
input x1,
input x2,
input x3,
input x4,
input clk,
output ya,
output yb,
output yc,
output yd,
output ye,
output yf,
output yg,
output yp,
output [3:0] display_enable
);
wire wire1, wire2, wire3;
wire [3:0] wire4;
reg mon_clk_reg;
w... | 6.774833 |
module display8digit (
input wire [31:0] val,
input wire clock,
output wire [7:0] segments,
output wire [7:0] digitselect
);
reg [31:0] counter = 0;
wire [ 2:0] topthree;
wire [ 3:0] value4bit;
always @(posedge clock) counter <= counter + 1'b1;
assign topthree[2:0] = counter[19:17];
// a... | 8.238318 |
module DisplayBCD (
input [15:0] DataIn,
input clk,
input clr,
output [6:0] seg,
output [3:0] an,
output dp
);
reg [ 6:0] to7SegReg;
reg [ 3:0] anReg;
wire [ 1:0] select;
reg [ 3:0] digit;
reg [19:0] clkdiv;
assign dp = 1'b1; //Turn off the decimal point
assign seg = to7Se... | 8.221486 |
module DisplayControl (
input wire clk,
input wire [3:0] enables,
input wire [4:0] digit3,
digit2,
digit1,
digit0,
output wire [3:0] an,
output wire [6:0] segment,
output wire dp
);
reg [4:0] current_digit;
reg [3:0] cur_dig_AN;
reg [6:0] segments;
assign an = ~(enables & c... | 7.598746 |
module DisplayController (
DispVal,
//anode,
segOut
);
// ==============================================================================================
// Port Declarations
// ==============================================================================================
input [3:0] Dis... | 7.598746 |
module displayCost(
input clk,
input rst,
input [15:0]cost,
output reg[6:0]seg0,
output reg[6:0]seg1,
output reg[6:0]seg2,
output reg[6:0]seg3
);
wire [3:0]bit;
wire [3:0]ten;
wire [3:0]hundred;
assign bit=cost%10;
assign ten=cost/10%10;
assign hundred=cost/100%10;
always@(posedge clk)
begin
//if(!rst)
//begin
case... | 6.909532 |
module DisplayDifference (
displayMode,
dest,
curr,
tube0,
tube1
);
input displayMode;
input [7:0] dest, curr;
output reg [7:0] tube0, tube1;
reg [7:0] difference, display;
reg neg;
initial begin
difference = 8'd0;
neg = 1'b0;
tube0 = 8'hFF;
tube1 = 8'hFF;
end
funct... | 6.988304 |
module displaydigit #(
parameter XPOS = 0,
parameter YPOS = 0
) (
input wire [9:0] hc, //horizontal counter
input wire [9:0] vc, //vertical counter
input wire [3:0] val, //value of the tile
output wire [2:0] red, //red vga output
output wire [2:0] green, //green vga output
... | 7.430237 |
module displayDriver (
input clk,
input [3:0] hex3,
input [3:0] hex2,
input [3:0] hex1,
input [3:0] hex0,
output reg [3:0] anode_select,
output reg [7:0] seven_seg
);
// Refresh the Seven segment at this rate: 50 Mhz / 2^16 = 763 Hz
localparam N = 18;
// internal signals
reg [N-1... | 8.37548 |
module DisplayGame (
input wire px_clk, // pixel clock.
input wire [25:0] RGBStr_i,
input wire [ 3:0] TabDat,
input wire [ 3:0] BmpDat,
output reg [10:0] TabAdd,
output reg [ 9:0] BmpAdd,
output reg [25:0] RGBStr_o //
);
// Logo dimension.
parameter Tab_width = 40;
... | 6.685622 |
module DisplayGamev2 (
input wire px_clk, // pixel clock.
input wire [25:0] RGBStr_i,
input wire [ 3:0] TabDat,
input wire [ 3:0] BmpDat,
output reg [10:0] TabAdd,
output reg [11:0] BmpAdd,
output reg [25:0] RGBStr_o //
);
// Logo dimension.
parameter Tab_width = 40;... | 6.700688 |
module displayhex (
res,
clr,
out1,
out2
);
input clr;
input [7:0] res;
output reg [6:0] out1;
output reg [6:0] out2;
always @(*) begin
if (clr) begin
out1 = 7'b1111111;
out2 = 7'b1111111;
end else begin
case (res / 16)
0: out1 = 7'b1000000;
1: out1 = ... | 7.114679 |
module displayIK_7seg_16 (
input wire CLK,
input wire RSTN,
input wire [15:0] data0,
input wire [15:0] data1,
input wire [15:0] data2,
input wire [15:0] data3,
input wire [15:0] data4,
input wire [15:0] data5,
input wire [15:0] data6,
input wire [15:0] dat... | 6.756401 |
module display_module_async_16b (
input wire [15:0] data,
output wire [31:0] SEG_32
);
display_module_async i0 (
.SEG_VAL(data[3:0]),
.SEG (SEG_32[7:0])
);
display_module_async i1 (
.SEG_VAL(data[7:4]),
.SEG (SEG_32[15:8])
);
display_module_async i2 (
.SEG_VAL(dat... | 6.815682 |
module display_module_async (
input wire [3:0] SEG_VAL,
output reg [7:0] SEG
);
always @(*) begin
case (SEG_VAL)
4'h0: SEG <= 8'b11111100;
4'h1: SEG <= 8'b01100000;
4'h2: SEG <= 8'b11011010;
4'h3: SEG <= 8'b11110010;
4'h4: SEG <= 8'b01100110;
4'h5: SEG <= 8'b10110110... | 6.815682 |
module displayImage (
myTrue,
myADDR,
startX,
startY,
ADDR
);
input wire [9:0] startX, startY;
input wire [18:0] ADDR;
output wire [18:0] myADDR;
output wire myTrue;
wire [18:0] ADDRcolumn, ADDRrow;
assign ADDRcolumn = ADDR % 'd640;
assign ADDRrow = ADDR / 'd640 + 'd1;
wire flag1,... | 6.722849 |
module DisplayInterface (
input CLK,
input [15:0] VALUE_IN,
output [7:0] HEX_OUT,
output [3:0] SEG_SELECT
);
wire [1:0] StrobeCount;
wire [4:0] MuxOut;
wire Bit17TriggOut;
// Clock counter
Generic_counter #(
.COUNTER_WIDTH(17),
.COUNTER_MAX (99999)
) Bit17Counter (
.RESE... | 7.202553 |
module DecoderLED (
input wire [3:0] W_in,
output reg [6:0] R_seg
);
always @(*) begin
case (W_in)
4'h0: R_seg = 7'b000_0001;
4'h1: R_seg = 7'b100_1111;
4'h2: R_seg = 7'b001_0010;
4'h3: R_seg = 7'b000_0110;
4'h4: R_seg = 7'b100_1100;
4'h5: R_seg = 7'b010_0100;
... | 6.718855 |
module DisplayLED #(
parameter INPUT_WIDTH = 32
) (
input wire clk,
rst,
input wire [INPUT_WIDTH-1:0] s,
output wire [6:0] seg,
output reg [7:0] sel
);
reg [20:0] R_count;
reg [ 4:0] R_digit;
always @(posedge clk) begin
if (rst) R_count = 21'h0;
else R_count = R_count + 21'b1;
en... | 6.696012 |
module displayLED_3 (
input clk,
input rst,
input [127:0] pattern,
output reg [7:0] a,
output reg [15:0] c
);
wire [4-1:0] M_slowclock_value;
counter_8 slowclock (
.clk (clk),
.rst (rst),
.value(M_slowclock_value)
);
reg [15:0] M_cSignal_d, M_cSignal_q = 1'h0;
reg [7... | 6.664898 |
module displayMail(
input clk,
input rst,
input [15:0]distance,
output reg[6:0]seg6,
output reg[6:0]seg7
);
wire [3:0]bit;
wire [3:0]ten;
wire [3:0]hundred;
assign bit=distance%10;
assign ten=distance/10%10;
always@(posedge clk)
begin
if(!rst)
begin
case(bit)
4'h0:seg6=7'b1000000;
4'h1:seg6=7'b1111001;
4'h2:s... | 7.703659 |
module DisplayMux (
D3,
D2,
D1,
D0,
Select,
Display,
Reset,
Clock
);
input [7:0] D3, D2, D1, D0;
input [3:0] Select;
input Reset, Clock;
output reg [7:0] Display;
reg [7:0] Digit3, Digit2, Digit1, Digit0; //stored values
always @(posedge Clock)
if (Reset == 1) begin
... | 7.046389 |
module displayMuxBasys (
input wire clk, // clock
input wire [3:0] hex3,
hex2,
hex1,
hex0, // hex digits
input wire [3:0] dp_in, // 4 dec pts
output reg [3:0] an, // enable for 4 displays
output reg [7:0] sseg // led segments
);
// constant for refresh rate: 50 ... | 7.905376 |
module displayout (
SW,
AluOut,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
LEDR
);
input [7:0] SW;
input [7:0] AluOut;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [7:0] LEDR;
aluseg7display u1 (
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
... | 6.711515 |
module DisplayPatternDecoder (
dynamicDigit,
sevenSegmentLed
);
input [2:0] dynamicDigit;
output [7:0] sevenSegmentLed;
assign sevenSegmentLed = (dynamicDigit == 3'b000) ? 8'b01001001:
(dynamicDigit == 3'b001) ? 8'b01110110:
(dynamicDigit == 3'b010) ? 8'b0110... | 7.336764 |
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