code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
module DisplayPosition (
output wire [7:0] LED
);
// create a binary counter
reg [7:0] cnt;
reg [3:0] choice;
initial begin
cnt <= 8'b0; // start at zero
//choice is x/8 amount done
choice <= 6;
end
always @(choice) begin
case (choice)
3'd1: cnt <= 8'd1;
3'd2: cnt <= 8'd3;
3'd3: cnt <= 8'd... | 6.807213 |
module DisplayPulse (
input Origin_Clock,
input reset,
output [2 : 0] pulse
);
reg [17:0] count;
initial begin
count = 'b0;
end
always @(posedge Origin_Clock or posedge reset) begin
if (reset) count <= 'd0;
else begin
if (count >= 'd131072) count <= 'd0;
else count <= count... | 7.227291 |
module DisplayRam (
input [A_WIDTH-1:0] address_a,
input [A_WIDTH-1:0] address_b,
input clock,
input [D_WIDTH-1:0] data_a,
input [D_WIDTH-1:0] data_b,
input wren_a,
input wren_b,
output reg [D_WIDTH-1:0] q_a,
... | 7.567751 |
module displayReg (
input wire CLK_190hz,
input wire [15:0] disp_data,
input wire clr, //clr为1，cur_data始终为1111,显示FFFF
output wire [3:0] pos_ctrl,
output wire [7:0] num_ctrl
);
reg [3:0] pos_sign = 4'b1011;
always @(posedge CLK_190hz) begin
pos_sign = {pos_sign[0], pos_sign[3:1]};
end
a... | 6.991013 |
module displays7seg (
i_clk,
i_rst_n,
i_addr,
i_we,
i_data,
o_disp0,
o_disp1,
o_disp2,
o_disp3,
o_disp4,
o_disp5
);
input i_clk;
input i_rst_n;
input i_we;
input [2:0] i_addr;
input [31:0] i_data;
output [6:0] o_disp0;
output [6:0] o_disp1;
output [6:0] o_dis... | 7.075319 |
module displaySelector (
clk,
SW,
en_ram,
en_sobel,
gen_addr,
vga_addr,
data_out,
Gx_out,
Gy_out,
cur_state,
red,
green,
blue,
rVGA,
bVGA,
gVGA,
rd_addr
);
input clk;
input [2:0] SW;
input en_ram;
input en_sobel; //new
input [9:0] gen_ad... | 7.1205 |
module displaySpeed(
input clk,
input rst,
input [15:0]speed,
output reg[6:0]seg4,
output reg[6:0]seg5
//output reg[6:0]seg6
//output reg[6:0]seg7
);
wire [3:0]bit;
wire [3:0]ten;
wire [3:0]hundred;
assign bit=speed%10;
assign ten=speed/10%10;
//assign hundred=speed/100%10;
always@(posedge clk)
begin
//if(!rst)
//be... | 6.97604 |
module displaysquares (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
V... | 8.688235 |
module specialdatapath (
leftsignal,
rightsignal,
clock,
reset,
xout,
yout,
colorout
);
input clock, reset, leftsignal, rightsignal;
output [2:0] colorout;
output [7:0] xout;
output [7:0] yout;
wire [19:0] c0;
wire [ 3:0] c1;
wire signal_x, signal_y;
wire [7:0] x_in, y_in;
... | 6.692334 |
module datapath (
X,
Y,
clock,
reset,
xout,
yout
);
input [7:0] X;
input [7:0] Y;
input clock;
input reset;
output [7:0] xout;
output [7:0] yout;
counter c1 (
X,
Y,
clock,
reset,
xout,
yout
);
endmodule
| 6.91752 |
module delay_counter (
clock,
reset_n,
q
);
input clock;
input reset_n;
output reg [19:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 20'b11001110111001100001;
else begin
if (q == 20'd0) q <= 20'b11001110111001100001;
else q <= q - 1'b1;
end
end
endmodule
| 6.853164 |
module x_counter (
clock,
clock_1,
reset_n,
signal,
leftsignal,
rightsignal,
q
);
input clock, reset_n, signal, leftsignal, rightsignal, clock_1;
output reg [7:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 8'd78;
if (clock_1 == 1'b0) begin
if (reset_n == ... | 6.671091 |
module frame_counter (
clock,
reset_n,
enable,
q
);
input clock, reset_n, enable;
output reg [3:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 4'b0000;
else if (enable == 1'b1) begin
if (q == 4'b1111) q <= 4'b0000;
else q <= q + 1'b1;
end
end
endmodule
| 6.859338 |
module DisplaySyn (
input wire [1:0] Scan,
input wire [15:0] Hexs, // four numbers in 2 based
input wire [3:0] Point,
input wire [3:0] LES,
output wire [3:0] HEX, // selected number to display in 2 based
output wire P, // point for the selected hex display
output wire LE, // is selected ... | 8.199709 |
module displays_and_keyboard (
input start,
input p1place,
p2place,
input p1fire,
p2fire,
input p1hit,
p1miss,
p2hit,
p2miss,
input p1wins,
p2wins,
output reg [35:0] keys_code,
// output [15:0] leds,
input Enter,
output [7:0] anode,
output [7:0] cathode,
... | 7.258669 |
module to act as test hardware for display interface.
// Defines top-level input and output signals (see comments on ports).
// Instantiates clock and reset generator block, for 5 MHz clock.
// Should instantiate the display interface to be tested.
// Created: 8 October 201... | 7.729492 |
module
// Module Name: D:/vga_disply/vga_tb.v
// Project Name: vga_disply
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: vga_top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////... | 6.999332 |
module DisplayValue (
CLK,
RST_N,
valx,
DISPX,
vald,
DISPD,
FINI
);
parameter width = 1;
input CLK;
input RST_N;
input DISPX;
input DISPD;
input FINI;
input [width - 1 : 0] valx;
input [width - 1 : 0] vald;
// synopsys translate_off
always @(posedge CLK) begin
if (DI... | 7.545484 |
module outputs multiple seven segment columns with the required information
module display_controller (
input clk, clear,
input [1:4] enables,
input [3:0] digit4, digit3, digit2, digit1,
output [0:3] AN,
output [6:0] C,
output DP
);
reg [3:0] current_digit, cur_dig_AN;
reg [6:0] segments;
... | 7.165825 |
module displayWinLose (
a,
b,
c,
d,
e,
f,
slotA,
slotB,
slotC,
slotD,
slotE,
slotF,
display1,
display2,
display3,
display4,
display5,
display6
);
input a, b, c, d, e, f;
input [0:4] slotA, slotB, slotC, slotD, slotE, slotF;
output reg [0:4] d... | 6.876079 |
module display_16 (
input wire clk,
input wire [15:0] digit,
output reg [3:0] node,
output reg [7:0] segment
);
reg [ 3:0] code = 4'b0;
reg [15:0] count = 16'b0;
always @(posedge clk) begin
case (count[15:14])
2'b00: begin
node <= 4'b1110;
code <= digit[3:0];
end
... | 7.02998 |
module display_32 (
clk,
disp_reg,
disp_ctrl,
digit_anode,
segment
);
input clk;
input wire [95:0] disp_reg;
input wire [1:0] disp_ctrl;
output reg [7:0] digit_anode;
output reg [7:0] segment;
reg [31:0] disp_num;
reg [12:0] cnt = 0;
reg [ 3:0] num;
always @(posedge clk) begin
... | 7.289772 |
module Display_4_16_decoder (
input wire clk,
input wire rst,
input wire [7:0] frame_cube [63:0], //64个灯柱，每个灯柱包含8个LED灯
output wire [7:0] led_v, //对应灯柱上8个LED灯的亮灭
output wire [3:0] scan, //经过解码后为16位的独热码，对应16个灯柱
output wire [3:0] en //切换到下一个解码器
);
parameter LEN = 20;
reg [LEN-1:0] ... | 6.707681 |
module display_4_7 (
input [3:0] in,
output reg [6:0] a
);
always @(in) begin
if (in == 4'b0000) out = 7'b0000001;
else if (in == 4'b0001) out = 7'b1001111;
else if (in == 4'b0010) out = 7'b0010010;
else if (in == 4'b0011) out = 7'b0000110;
else if (in == 4'b0100) out = 7'b1001100;
els... | 6.724925 |
module display_7s (
input clk,
input [6:0] N1,
N2,
output [3:0] an,
output [6:0] seg
);
reg btnC = 1'd0;
//reg [6:0] N1 = 7'd54;
//reg [6:0] N2 = 7'd32;
wire [3:0] D1, U1, D2, U2;
digit_separator(
N1, D1, U1
); digit_separator(
N2, D2, U2
);
wire [6:0] dig1a, dig2a, dig1b... | 6.87928 |
module Display_7SegLED (
input [3:0] display_data,
output reg [7:0] dispcode
);
always @(display_data) begin
case (display_data)
4'b0000: dispcode = 8'b1100_0000; //0;'0'-亮灯，'1'-熄灯
4'b0001: dispcode = 8'b1111_1001; //1
4'b0010: dispcode = 8'b1010_0100; //2
4'b0011: dispcode = ... | 6.550168 |
module display_7segmentos (
input clk, //100 MHz
input reset,
input [3:0] bin,
output [7:0] anodo,
output [6:0] catodos
);
wire reloj_actualizacion;
wire contador_actualizar;
wire [3:0] digito;
divisor_reloj D (
clk,
reset,
reloj_actualizacion
); //D por divisor
con... | 6.927779 |
module display_7seg_onboard (
input clk_100MHz,
input le,
input rst,
input [3:0] digit0,
input [3:0] digit1,
input [1:0] digit_sel,
input [1:0] dot,
output [7:0] AN,
output [7:0] C
);
reg [3:0] digit7_r;
reg [3:0] digit6_r;
reg [3:0] digit5_r;
reg [3:0] digit4_r;
reg [3:0]... | 7.119208 |
module display_7_seg (
input [2:0] in,
output [6:0] out
);
assign out = (in==4'b000) ? 7'b1000000:
(in==4'b001) ? 7'b1111001:
(in==4'b010) ? 7'b0100100:
(in==4'b011) ? 7'b0110000:
(in==4'b100) ? 7'b0011001:
(in==4'b101) ? 7'b0010010:
(in==4'b110) ? 7'b0000010:
... | 6.639533 |
module display_7_segment (
clk,
in,
an,
out
);
output reg [3:0] an;
output reg [7:0] out;
input clk;
input [15:0] in;
reg [1:0] count = 0;
wire [3:0] one, ten, hundred;
wire [7:0] one_7, ten_7, hundred_7, thous_7;
//bcd M0(in,one_orig,ten_orig);
bcd bcd_scoresystem (
.binary(... | 6.639533 |
module display_7_seg_hex (
input clk,
input [7:0] value,
output [6:0] seg,
output reg digit
);
reg [3:0] data;
reg posn;
reg [23:0] prescaler;
decoder_7_seg_hex decoder (
.clk (clk),
.seg (seg),
.data(data)
);
always @(posedge clk) begin
prescaler <= prescaler + 1;
... | 6.639533 |
module display_8hex (
input clk, // system clock
input [31:0] data, // 8 hex numbers, msb first
output reg [ 6:0] seg, // seven segment display output
output reg [ 7:0] strobe // digit strobe
);
localparam bits = 13;
reg [bits:0] counter = 0; // clear on power up
wire... | 7.899435 |
module display_admin (
input eleccion_1,
eleccion_2,
modo_conf,
input [13:0] monto_ingresado,
input [13:0] vuelto,
input [13:0] boletas_emitidas,
output reg [13:0] data
);
always @(*) begin
if (eleccion_1 & ~eleccion_2 & ~modo_conf) data = monto_ingresado;
else if (eleccion_2 & ~e... | 9.05797 |
module display_all (
clock, // On Board 50 MHz
// Your inputs and outputs here
// KEY,
position,
address,
done,
x,
y,
colour
);
input [7:0] position;
input [7:0] address;
input clock;
output reg done;
output reg [3:0] x, y;
wire resetn;
// declare the clock q,k,s
wir... | 6.610075 |
module counter_2bits (
s,
clear_b,
clock,
Enable
);
output reg [1:0] s; // declare q
input clear_b, clock, Enable;
always @(posedge clock, negedge clear_b) // triggered every time clock rises
begin
if (clear_b == 1'b0) // when Clear_b is 0...
s <= 0; // set s to 0
else if (s ... | 7.034602 |
module counter_8bits (
k,
clear_b,
clock,
Enable
);
output reg [7:0] k; // declare k
input clear_b, clock, Enable;
always @(posedge clock, negedge clear_b) // triggered every time clock rises
begin
if (clear_b == 1'b0) // when Clear_b is 0...
k <= 0; // set k to 0
else if (k ... | 8.014153 |
module display_and_drop (
output reg [6 : 0] seven_seg1,
output reg [6 : 0] seven_seg2,
output reg [6 : 0] seven_seg3,
output reg [6 : 0] seven_seg4,
output reg [0 : 0] drop_activated,
input [ 15:0] t_act,
input [ 15:0] t_lim,
input drop_en
);
always @(*) begin... | 7.081821 |
module display_border (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
enable_red_border
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
output enable_red_border;
/**************************************************/
parameter h_start = 11'd391;
parameter v... | 6.633614 |
module is a simple clock divider that produces the clock signal
// used in display controller.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////... | 7.514223 |
module display_clock (
input load,
input set,
input [3:0] set_id,
input [3:0] set_num,
input [3:0] seconds_ones,
minutes_ones,
load_minutes_ones,
input [2:0] seconds_tens,
minutes_tens,
load_minutes_tens,
output reg [3:0] out_seconds_... | 6.968116 |
module display_clocks_tb ();
reg rst;
reg clk;
// Display clocks: 640x480p60
wire pix_clk_480p;
wire pix_clk_5x_480p;
wire clk_lock_480p;
display_clocks #(
.MULT_MASTER(31.5),
.DIV_MASTER(5),
.DIV_5X(5.0),
.DIV_1X(25),
.IN_PERIOD(10.0)
) display_clocks_480p (
.i_... | 6.968116 |
module Display_clock_state_tb ();
reg clk_100MHz;
reg rst_time;
reg [3:0] L_sec;
reg [3:0] H_sec;
reg [3:0] L_min;
reg [3:0] H_min;
reg [3:0] L_hour;
reg [3:0] H_hour;
reg [1:0] select_time;
reg change_out;
//Ϊλѡź
wire [7:0] bit_sel;
//Ϊѡź
wire [6:0] seg_sel;
initial begin
clk_100MHz ... | 7.197681 |
module display_controler (
CLOCK_50MHZ,
DIG,
SEG
);
input CLOCK_50MHZ;
output [3:0] DIG;
output [6:0] SEG;
wire NEW_CLOCK;
reg [3:0] CONTROLER;
integer COUNTER;
initial CONTROLER = 4'b1111;
initial COUNTER = 0;
display_clock exec (
CLOCK_50MHZ,
NEW_CLOCK
);
assign DIG ... | 6.902359 |
module display_counter_main (
SW,
HEX0,
CLOCK_50
);
input [9:0] SW;
input CLOCK_50;
output [6:0] HEX0;
wire enable;
wire [27:0] RateDivider;
assign enable = (RateDivider == 28'd0) ? 1 : 0;
wire [3:0] Q;
hex_counter block0 (
.d(SW[6:3]), //Load value
.clock(CLOCK_50),
.... | 7.637494 |
module hex_counter (
d,
clock,
reset_n,
par_load,
enable,
q,
unpause
);
input [3:0] d;
input clock;
input reset_n;
input unpause;
input par_load, enable;
output [3:0] q;
reg [3:0] q;
always @(posedge clock, negedge reset_n, posedge par_load) //Very important: add negedge r... | 6.834855 |
module rate_divider (
rate,
clock,
reset_n,
count
);
input [1:0] rate;
input reset_n;
input clock;
output [27:0] count;
reg [27:0] count;
reg [27:0] scale;
always @(*) begin
case (rate[1:0])
2'b00: scale = 0;
2'b01: scale = 1;
2'b10: scale = 2;
2'b11: scale = 4;... | 7.346866 |
module hex (
c,
m
);
input [3:0] c;
output [6:0] m;
reg [6:0] z;
always @(*) begin
case (c[3:0])
4'b0000: z = 7'b1111110;
4'b0001: z = 7'b0110000;
4'b0010: z = 7'b1101101;
4'b0011: z = 7'b1111001;
4'b0100: z = 7'b0110011;
4'b0101: z = 7'b1011011;
4'b0110: z ... | 7.753835 |
module DISPLAY_DECODER (
RESETN,
CLK,
IN_TIME,
IN_DATE,
IN_ALARM_TIME,
OUT_H10,
OUT_H1,
OUT_M10,
OUT_M1,
OUT_S10,
OUT_S1,
OUT_Y10,
OUT_Y1,
OUT_MT10,
OUT_MT1,
OUT_D10,
OUT_D1,
OUT_ALARM_H10,
OUT_ALARM_H1,
OUT_ALARM_M10,
OUT_ALARM_M1,
... | 6.86596 |
module Display_Digits #(
parameter NUMBER_OF_DIGITS = 1,
parameter REFRESH_RATE_IN_HERTZ = 500,
parameter BOARD_CLOCK_FREQUENCY_IN_HZ = 100_000_000
) (
input wire clk, // clock
input wire [((NUMBER_OF_DIGITS*4)-1):0] number, // reset
input wire [(NUMBER_OF_DIGITS-1):0] an,
output wire [3:0... | 6.954411 |
module Display_Digits_tb ();
// inputs
reg clk;
reg [3:0] seconds_1;
reg [3:0] seconds_10;
reg [3:0] minutes_1;
// outputs
wire [3:0] io_sel;
wire [7:0] io_seg;
Display_Digits #(
.NUMBER_OF_DIGITS(3),
.REFRESH_RATE_IN_HERTZ(10),
.BOARD_CLOCK_FREQUENCY_IN_HZ(60)
) dut (
.c... | 6.954411 |
module Display_double (
in,
out
);
input [5:0] in;
output reg [13:0] out;
always @(*) begin
case (in)
6'b000000: out = {7'b1000000, 7'b1000000};
6'b000001: out = {7'b1000000, 7'b1111001};
6'b000010: out = {7'b1000000, 7'b0100100};
6'b000011: out = {7'b1000000, 7'b0110000};
... | 7.158281 |
module display_driver (
input en,
input [3:0] dig,
input dot,
output [7:0] _gfedcba
);
// . g f e d c b a // Letter from the diagram below
// 7 6 5 4 3 2 1 0 // Bit in _gfedcba
// --a--
// | |
// f b
// | |
// --g--
// | |
// e c
// ... | 6.908978 |
module: display_driver
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module display_driver_t;
// Inputs
reg clk;
reg rst;
reg en;
// Outputs
wire a_l;
wire b_l;
wire c_l;
wire ... | 6.728094 |
module display_four (
in,
out
);
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @* begin
case (in)
4'b0000: // 0
out = 7'b1000000;
4'b0001: // 1
out = 7'b1111001;
4'b0010: // 2
out = 7'b0100100;
4'b0011: // 3
out = 7'b0110000;
4'... | 6.944141 |
module display_eight (
in,
first_led,
second_led
);
input [7:0] in;
output [6:0] first_led;
output [6:0] second_led;
wire [3:0] first_portion;
assign first_portion = in[3:0];
wire [3:0] second_portion;
assign second_portion = in[7:4];
display_four disp1 (
first_portion,
first... | 6.507178 |
module Display_Generator (
clock,
act_D,
addr[3:0],
disp7[6:0]
);
// PI and PO
input act_D;
input clock;
input [3:0] addr;
output [6:0] disp7;
reg [6:0] disp7;
always @(posedge clock)
if (act_D == 1) begin
case (addr)
4'b0000: disp7 <= 7'b1000000; // '0'
4'... | 6.976508 |
module display_HEX_Bin2HexorDec (
binary_input,
hex_output
);
input [3:0] binary_input;
output reg [0:6] hex_output;
always begin
case (binary_input)
0: hex_output = 7'b0000001;
1: hex_output = 7'b1001111;
2: hex_output = 7'b0010010;
3: hex_output = 7'b0000110;
4: he... | 7.117485 |
module display_hex_byte (
input clk,
input [7:0] hex_byte,
output wire [7:0] segments,
output wire [2:0] segments_enable
);
/* These are the module's configurable parameters */
parameter refresh_rate = 1000; // Refresh rate in Hz
parameter sys_clk_freq = 100000000; // Input clock frequency in H... | 9.849534 |
module nibble_to_segments (
input [3:0] nibble,
output wire [7:0] segments
);
/*
* Store the segment information in segments_out and send that signal
* through the "segments" wire.
*/
reg [7:0] segments_out;
assign segments = segments_out;
/*
* This section is essentially a lookup table that m... | 7.15649 |
module display_HEX_DE1 (
S1,
S0,
O6,
O5,
O4,
O3,
O2,
O1,
O0
);
input S1, S0;
output O6, O5, O4, O3, O2, O1, O0;
assign O0 = S1 | (~S0);
assign O1 = S0;
assign O2 = S0;
assign O3 = S1 & (~S0);
assign O4 = S1;
assign O5 = (~S0) | S1;
assign O6 = S1;
endmodule
| 7.144743 |
module display_if (
input clk,
input rst,
input [12:0] mem_waddr,
input [23:0] mem_wdata,
input mem_web,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_SYNC,
output VGA_BLANK,
output VGA_CLK,
output VGA_HS,
output VGA_VS
);
wire iCLK;
wir... | 7.674847 |
module display_integrator (
input clk,
input reset,
input [5:0] min_out, // 6 bit input from timer
input [5:0] sec_out, // 6 bit input from timer
output [6:0] seg, // 7 segment output
output dp, // decimal point -> not used
output [3:0] an, // anode output
output [3:0] sec0,
sec... | 8.503251 |
module display_interface (
input clk,
input rst,
input [9:0] mario_x,
input [9:0] mario_y,
input [9:0] mario_x1,
input [9:0] mario_y1,
input [9:0] coin_x,
input [9:0] coin_y,
output HSYNC,
output VSYNC,
output wire [2:0] R,
output wire [2:0] G,
output wire [1:0] B
);
... | 7.761525 |
module display_logic (
input pxl_clk,
input [9:0] hcount,
input [9:0] vcount,
input [9:0] ball_y,
input [9:0] ball_x,
input [5:0] player_position,
input [3:0] block_num,
input vsync,
input lose,
input win,
output reg drawing_player,
output reg drawing_block,
output re... | 7.442316 |
module display_lpr_boundary (
input pixelclk,
input reset_n,
input [23:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] v... | 7.19544 |
module display_sD_avalon_interface #(
parameter LEN = 4,
parameter CHAR_LEN = 6
) (
input csi_clk,
input rsi_reset_n,
input avs_s0_write,
input avs_s0_read,
input [3:0] avs_s0_address,
input [31:0] avs_s0_writedata,
output reg [31:0] avs_s0_readdata,
output [CHAR_LEN - 1:0] n... | 6.929825 |
module single_7seg (
number,
seg
);
input [3:0] number;
output [6:0] seg;
reg [6:0] seg;
always @(number)
case (number)
4'b0000: seg = 8'b11000000; //0
4'b0001: seg = 8'b11111001; //1
4'b0010: seg = 8'b10100100; //2
4'b0011: seg = 8'b10110000; //3
4'b0100: seg = 8... | 6.783583 |
module clk_div #(
parameter width = 1
) (
clk_in,
clk_out
);
input clk_in;
output clk_out;
reg clk_out = 0;
integer idx = 0;
always @(posedge clk_in) begin
if (idx >= width) begin
idx <= 0;
clk_out <= ~clk_out;
end else idx <= idx + 1;
end
endmodule
| 7.516677 |
module display_module(seg,select,clk_base,type,PC,NPC,rs_a,rs_d,rt_a,rt_d,alu_out,db);
input [1:0]type;
input clk_base;
input [31:0] PC,NPC,rs_d,rt_d,alu_out,db;
input [4:0] rs_a,rt_a;
output [6:0] seg;
output [3:0] select;
reg [6:0] seg;
reg [3:0] select;
wire [15:0] pc,rs,rt,alu;... | 6.815682 |
module display_mux (
input clk,
input clk_enable,
input [31:0] bcd,
input [7:0] dots,
input is_negative,
input turn_off,
output [7:0] ss_value,
output [7:0] ss_select
);
/*
* Using one-hot coding is particularly useful since the state itself can be
* connected to the selector bus d... | 8.563006 |
module display_next_square (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
loading_square,
next_yellow_display,
square_type_out
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
input loading_square;
input [2:0] square_type_out;
output next_yellow_displ... | 7.087311 |
module decoder3_8 (
input [2:0] pos,
input off,
output reg [7:0] an
);
initial an = 0;
always @(*)
if (off == 1) an = ~8'b00000000;
else begin
case (pos) //注意低电平有效！
3'o0: an = ~8'b00000001;
3'o1: an = ~8'b00000010;
3'o2: an = ~8'b00000100;
3'o3: an = ~8'b0... | 7.729152 |
module display_number (
input clk,
input [13:0] N,
output [3:0] an,
output [6:0] seg
);
wire [15:0] BCD;
wire X;
wire clock;
clk_divider_7segment(
clk, 0, clock
); Binary_to_BCD(
clk, N, clock, BCD, X
); display_7s(
clk, 10 * BCD[15:12] + BCD[11:8], 10 * BCD[7:4] + BCD[3... | 7.149276 |
module display_out (
input wire [2:0] indata, // R,G,B
input wire DT, // fBXvC^C~O
input wire EXP, // ͐
output reg RD,
output reg GD,
output reg BD
);
always @* begin
if (~EXP) begin
RD <= #1 indata[2] & DT;
GD <= #1 indata[1] & DT;
BD <= #1 indata[0] & DT;
end els... | 6.936769 |
module display_pal_testbench ();
reg clk;
reg rst;
reg [15:0] data;
reg [18:0] dram_addr;
reg dram_rclk;
reg dram_ce0_n;
reg dram_ren;
reg pf_blank, pf_sync;
reg [7:0] pf_pixel;
always #1 clk = ~clk;
initial begin
clk = 0;
rst = 1;
data = 16'h333... | 8.274066 |
module display_pane (
input clk,
input rst,
input [23:0] data_in,
input empty,
input full,
output reg write_en,
output [12:0] mem_addr,
output [23:0] data_out
);
// States
localparam WAIT = 1'b0;
localparam LOAD = 1'b1;
// Flop registers
reg [2:0] h_count, v_count;
reg [7:0... | 7.115832 |
module display_pane_tb ();
reg stm_clk, stm_rst, stm_empty, stm_full;
reg [23:0] stm_data_in;
wire [23:0] data_out_mon;
wire [12:0] mem_addr_mon;
wire write_en_mon;
display_pane dp0 (
.clk(stm_clk),
.rst(stm_rst),
.data_in(stm_data_in),
.empty(stm_empty),
.full(stm_full),
... | 8.087643 |
module pic_chess_piece (
input wire en,
input wire [31:0] i,
output reg [22:0] ret
);
always @(en or i)
if (!en) ret = 23'b0;
else
case (i)
32'd00: ret = 23'b00000000000000000000000;
32'd01: ret = 23'b00000000000000000000000;
32'd02: ret = 23'b00000000111111100000... | 6.952867 |
module pic_side_player (
input wire en,
input wire [31:0] i,
output reg [71:0] ret
);
always @(en or i)
if (!en) ret = 72'b0;
else
case (i)
32'd00: ret = 72'b000000111111100000000000000000000000000000000000000000000000000000000000;
32'd01: ret = 72'b00001111111111100000000... | 8.128301 |
module pic_side_ai (
input wire en,
input wire [31:0] i,
output reg [71:0] ret
);
always @(en or i)
if (!en) ret = 72'b0;
else
case (i)
32'd00: ret = 72'b000000111111100000000000000000000000000000000000000000000000000000000000;
32'd01: ret = 72'b00001111111111100000000000000... | 7.050544 |
module pic_crt_ptr (
input wire en,
input wire [31:0] i,
output reg [31:0] ret
);
always @(en or i)
if (!en) ret = 32'b0;
else
case (i)
32'd00: ret = 32'b00000000001111111100000000000000;
32'd01: ret = 32'b00000001110000000011111111111110;
32'd02: ret = 32'b011111... | 7.056762 |
module pic_author_info (
input wire en,
input wire [31:0] i,
output reg [124:0] ret
);
always @(en or i)
if (!en) ret = 125'b0;
else
case (i)
32'd00:
ret = 125'b000000000000100010000000000010000000000000100000000000000000011100000000001000000000100000001000000000101010000000... | 8.044259 |
module Display_process_number #(
parameter DATA_WIDTH = 32
) (
input single_clk,
input [(DATA_WIDTH-1):0] new_proc_num,
output reg [(DATA_WIDTH-1):0] last_proc_num
);
reg [(DATA_WIDTH-1):0] proc_num;
always @(posedge single_clk) begin
if (new_proc_num != 32'b00000000000000000000000000000000) be... | 7.392316 |
module display_regs ( /*AUTOARG*/
// Outputs
data_out,
segment0,
segment1,
segment2,
segment3,
// Inputs
clk,
reset,
port_id,
data_in,
read_strobe,
write_strobe
);
parameter BASE_ADDRESS = 8'h00;
input clk;
input reset;
input [7:0] port_id;
input [7:0] da... | 6.566059 |
module display_reset_controller (
input clk,
input reset_in,
v_blank,
output reg reset_out
);
//
parameter MAX_FRAME_COUNT = 13;
reg last_v_blank;
reg [4:0] frame_counter;
initial begin
frame_counter <= 1'b0;
end
always @(posedge clk) begin
last_v_blank <= v_blank;
if (res... | 6.925407 |
module describes an mapping to
// the colors of the scene (background, foreground, etc)
// from the coordinates (x, y). It is always synchronized
// with game_state (i.e. It is a pure function).
module display_scene(
input wire clk,
input wire clk_100Hz,
input wire [8:0] y,
input wire [9:0] x,
input wire [1:0] ... | 7.320601 |
module display_score (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
score_out,
color_score_out
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
input [15:0] score_out;
output color_score_out;
reg data;
reg [11:0] addra;
wire [15:0] data_n;
assign... | 7.081047 |
module display_screen (
input [ 4:0] switch_state,
input [23:0] display_pattern, //the numbers to be displayed
input clk, //the synchronizing clock working at 50MHz (see ucf file)
input [ 5:0] blinking_pattern, //select which digits will blink
output lcd_rs,
lc... | 7.270961 |
module display_seg (
input [3:0] num, // 需要显示的数字
output reg [7:0] dig, // 输出的数码管信号
output [7:0] bit_ctrl // 输出的数码管位控
);
/**************************************************************
参数定义
*************************************************************/
parameter D0 = 8'b1100_0000;... | 7.400351 |
module display_sel (
num,
dig,
code
);
input [2:0] num;
input [31:0] dig;
output reg [3:0] code;
always @* begin
case (num)
3'd0: code = dig[3:0];
3'd1: code = dig[7:4];
3'd2: code = dig[11:8];
3'd3: code = dig[15:12];
3'd4: code = dig[19:16];
3'd5: code = dig... | 7.599068 |
module Select (
input [15:0] In1,
In2,
In3,
In4,
input [ 1:0] SelectCode,
output reg [15:0] DataOut
);
always @(*) begin
case (SelectCode)
2'b00: DataOut = In1;
2'b01: DataOut = In2;
2'b10: DataOut = In3;
2'b11: DataOut = In4;
endcase
end
endmodule
| 7.361613 |
module Display_select_counter (
input wire mudou_volume,
input wire clk,
input wire reset,
output reg display_select
);
parameter clock_freq = 28'd100, // Considerando a frequência do clk_timer como 1MHz
five_seconds = clock_freq * 5; // Fica contando por 5 passagem do timer
reg [27:0] cou... | 6.82816 |
module divider #(
parameter N = 100000
) (
input iData,
output reg oData = 0
);
integer tc = 0;
always @(posedge iData) begin
if (tc < N / 2 - 1) ///ƵӦǷֵ1/50000
tc <= tc + 1;
else begin
tc <= 0;
oData <= ~oData;
end
end
endmodule
| 7.259052 |
module converts a pixel clock into a hsync+vsync+disp_enable+x+y structure.
module display_signal #(
H_RESOLUTION = 640,
V_RESOLUTION = 480,
H_FRONT_PORCH = 16,
H_SYNC = 96,
H_BACK_PORCH = 48,
V_FRONT_PORCH = 10,
V_SYNC = 2,
V_BACK_PORCH = 33,
H_SYNC_POLARITY = 0, /... | 7.377366 |
module display_signals (
input clk,
input reset,
input strobe,
output reg [9:0] xPos = 0,
output reg [9:0] yPos = 0,
output horizSync,
output vertSync,
output reg valid
);
reg [9:0] HS;
reg [9:0] VS;
localparam horizActiveEnd = 639; // end of the active pixels
localparam hori... | 8.560745 |
module display_signals_test ();
reg clk;
reg reset;
wire [9:0] xPos;
wire [9:0] yPos;
wire horizSync;
wire vertSync;
wire valid;
display_signals test (
.valid(valid),
.clk(clk),
.reset(reset),
.xPos(xPos),
.yPos(yPos),
.horizSync(horizSync),
.vertSync(vertSync... | 8.560745 |
module display_stuff (
input wire OSC_FPGA,
// For GPMC control/interfacing
inout wire [15:0] GPMC_AD,
input wire GPMC_CSN,
input wire GPMC_OEN,
input wire GPMC_ADVN,
input wire GPMC_WEN,
input wire [1:0] GPMC_BEN,
input wire GPMC_CLK,
// For control of the HUB75 interface
... | 7.148814 |
module displaySystem #(
parameter FFT_SIZE = 256,
DATA_WIDTH = 4
) (
input wire hdmi_clk,
input wire hdmi_clk_lock,
input wire reset,
input wire [DATA_WIDTH-1:0] data_rd,
input wire [IDX_WIDTH-1:0] OLDEST_FFT_IDX,
output wire [NO_BANKS-1:0] bank_rd,
output wire [RAM_ADDR_WIDTH-1:0] ... | 7.365641 |
module display_task ();
// Task for displaying
task disp(input integer a, input integer b);
begin
#(a) $display($time, "ns : a = %d, b = %d", a, b);
end
endtask
// Call the task multiple times
initial #10 disp(1, 2);
initial #10 disp(1, 4);
initial #10 disp(2, 3);
endmodule
| 6.808243 |
module Display_testbench;
wire [3:0] minutes0_tb, seconds0_tb, seconds1_tb;
wire [3:0] volume0_tb, volume1_tb;
reg reset_tb, clk_tb, clk_timer, aumenta_tb, diminui_tb, mute_tb, reset_display_tb;
wire mudou_volume_tb;
wire select_tb;
wire [6:0] digit2_tb, digit1_tb, digit0_tb, digit4_tb;
function [4... | 7.164005 |
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