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11.5
module madd_core_112 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.155797
module madd_113 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_113 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.013356
module madd_core_113 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.843148
module madd_114 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_114 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.255515
module madd_core_114 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.973101
module madd_115 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_115 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.962535
module madd_core_115 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.969983
module madd_116 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_116 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.187257
module madd_core_116 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.985542
module madd_117 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_117 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.30936
module madd_core_117 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.073935
module madd_118 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_118 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.300327
module madd_core_118 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.107028
module madd_119 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_119 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.90673
module madd_core_119 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.043821
module madd_120 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_120 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.691866
module madd_core_120 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.118515
module madd_121 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_121 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.29167
module madd_core_121 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.042729
module madd_122 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_122 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.457723
module madd_core_122 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.257273
module madd_123 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_123 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.381899
module madd_core_123 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.112492
module madd_124 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_124 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.693069
module madd_core_124 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.258902
module madd_125 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_125 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.96742
module madd_core_125 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.011474
module madd_126 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_126 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.465738
module madd_core_126 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.970151
module madd_127 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_127 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.265235
module madd_core_127 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.089728
module madd_128 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_128 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.440349
module madd_core_128 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.096173
module madd_129 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_129 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.657642
module madd_core_129 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.925468
module madd_130 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_130 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.129558
module madd_core_130 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.808765
module madd_131 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_131 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.934776
module madd_core_131 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.858799
module madd_132 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_132 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.689442
module madd_core_132 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.953719
module madd_133 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_133 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.203582
module madd_core_133 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.977217
module madd_134 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_134 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.607224
module madd_core_134 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.963353
module madd_135 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_135 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.369146
module madd_core_135 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.939739
module madd_136 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_136 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.7036
module madd_core_136 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.16364
module madd_137 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_137 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.094361
module madd_core_137 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.867944
module madd_138 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_138 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.157039
module madd_core_138 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.137558
module madd_139 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_139 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.739915
module madd_core_139 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.938787
module madd_140 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_140 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.345596
module madd_core_140 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.932553
module madd_141 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_141 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.237503
module madd_core_141 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.904522
module madd_142 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_142 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.420298
module madd_core_142 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.921179
module madd_143 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_143 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.369198
module madd_core_143 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.038852
module multiplier_core_1 ( input CLK, input update, input [32-1:0] a, input [16-1:0] b, output [48-1:0] c ); reg signed [32-1:0] _a; reg signed [16-1:0] _b; wire signed [48-1:0] _mul; reg signed [48-1:0] _pipe_mul0; reg signed [48-1:0] _pipe_mul1; assign _mul = _a * _b; assign c =...
6.701364
module madd_144 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_144 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
8.05365
module madd_core_144 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.31279
module madd_145 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_145 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.040445
module madd_core_145 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.886991
module madd_146 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_146 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.285894
module madd_core_146 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.921082
module madd_147 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_147 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.915834
module madd_core_147 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.859777
module madd_148 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_148 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.397823
module madd_core_148 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.016075
module madd_149 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_149 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.761739
module madd_core_149 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.969008
module madd_150 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_150 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.081835
module madd_core_150 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.799323
module madd_151 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_151 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.93995
module madd_core_151 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.801349
module madd_152 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_152 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.40692
module madd_core_152 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.035704
module madd_153 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_153 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.011899
module madd_core_153 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.903539
module madd_154 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_154 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.550213
module madd_core_154 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.162249
module madd_155 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_155 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.392986
module madd_core_155 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.153583
module madd_156 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_156 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.529041
module madd_core_156 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.14901
module madd_157 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_157 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.128104
module madd_core_157 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.02998
module madd_158 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_158 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.145817
module madd_core_158 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.170644
module madd_159 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_159 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.422127
module madd_core_159 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.138544
module madd_160 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_160 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.920979
module madd_core_160 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.833362
module madd_161 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_161 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.673599
module madd_core_161 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.884597