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11.5
module madd_162 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_162 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.905038
module madd_core_162 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.286219
module madd_163 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_163 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.299634
module madd_core_163 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.094028
module madd_164 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_164 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.508053
module madd_core_164 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.230193
module madd_165 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_165 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.986765
module madd_core_165 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.093361
module madd_166 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_166 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.194521
module madd_core_166 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.043107
module madd_167 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_167 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.883603
module madd_core_167 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.008911
module madd_168 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_168 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.999775
module madd_core_168 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.108549
module madd_169 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_169 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.230792
module madd_core_169 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.997822
module madd_170 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_170 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.245952
module madd_core_170 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.930235
module madd_171 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_171 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.934226
module madd_core_171 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.84941
module madd_172 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_172 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.348129
module madd_core_172 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.074876
module madd_173 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_173 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.440287
module madd_core_173 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.126156
module madd_174 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_174 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.84654
module madd_core_174 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.328606
module madd_175 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_175 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.438801
module madd_core_175 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.053754
module madd_176 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_176 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.429849
module madd_core_176 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.040546
module madd_177 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_177 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.271441
module madd_core_177 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.053592
module madd_178 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_178 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.375875
module madd_core_178 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.04821
module madd_179 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_179 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.921741
module madd_core_179 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.053205
module madd_180 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_180 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.564307
module madd_core_180 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.931212
module madd_181 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_181 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.141312
module madd_core_181 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.994138
module madd_182 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_182 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.410312
module madd_core_182 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.244098
module madd_183 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_183 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.58847
module madd_core_183 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.220839
module madd_184 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_184 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.547471
module madd_core_184 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.237051
module madd_185 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_185 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.423215
module madd_core_185 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.088007
module madd_186 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_186 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.630422
module madd_core_186 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.093939
module madd_187 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_187 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.178229
module madd_core_187 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.925864
module madd_188 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_188 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.497705
module madd_core_188 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.03379
module madd_189 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_189 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.915257
module madd_core_189 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.17551
module madd_190 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_190 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.809507
module madd_core_190 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.000173
module madd_191 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_191 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.642538
module madd_core_191 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.004725
module madd_192 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_192 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.997497
module madd_core_192 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.251999
module madd_193 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_193 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.295315
module madd_core_193 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.044513
module madd_194 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_194 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.681799
module madd_core_194 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.164954
module madd_195 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_195 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.401299
module madd_core_195 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.93165
module madd_196 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_196 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.485413
module madd_core_196 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.114147
module madd_197 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_197 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.422221
module madd_core_197 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.07903
module madd_198 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_198 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.631925
module madd_core_198 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.990898
module madd_199 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_199 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
8.007623
module madd_core_199 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.173866
module madd_200 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_200 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.231091
module madd_core_200 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.062695
module madd_201 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_201 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.451008
module madd_core_201 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.009971
module madd_202 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_202 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.97716
module madd_core_202 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.238361
module madd_203 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_203 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.423469
module madd_core_203 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.972397
module madd_204 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_204 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.828903
module madd_core_204 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.203336
module madd_205 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_205 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.463276
module madd_core_205 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.132592
module madd_206 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_206 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.660049
module madd_core_206 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.210058
module madd_207 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_207 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.937659
module madd_core_207 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.060443
module madd_208 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_208 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.720977
module madd_core_208 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.323605
module madd_209 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_209 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.873405
module madd_core_209 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.200788
module madd_210 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_210 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.365713
module madd_core_210 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.863952
module madd_211 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_211 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.399828
module madd_core_211 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.040781