code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dotprod1_block (
In1,
In2,
Out1
);
input [63:0] In1; // double
input [63:0] In2; // double
output [63:0] Out1; // double
real In1_double; // double
real In2_double; // double
real Dot_Product_out1; // double
always @* In1_double = $bitstoreal(In1);
always @* In2_double = ... | 7.296424 |
module dotproduct2 (
clk,
rst,
g_input,
e_input,
o
);
input [1:0] g_input;
input [1:0] e_input;
input clk, rst;
output o;
wire N4, n3, n4;
assign o = N4;
NAND U4 (
.A(n3),
.B(n4),
.Z(N4)
);
XOR U5 (
.A(g_input[0]),
.B(e_input[0]),
.Z(n4)
);
... | 7.386916 |
module dotproduct3 (
clk,
rst,
g_input,
e_input,
o
);
input [2:0] g_input;
input [2:0] e_input;
input clk, rst;
output o;
wire N8, n8, n9, n10, n11, n12, n13, n14;
assign o = N8;
NAND U11 (
.A(n8),
.B(n9),
.Z(N8)
);
OR U12 (
.A(n10),
.B(n11),
.Z... | 6.815078 |
module dotproduct4 (
clk,
rst,
g_input,
e_input,
o
);
input [3:0] g_input;
input [3:0] e_input;
input clk, rst;
output o;
wire N13, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22;
assign o = N13;
NAND U13 (
.A(n12),
.B(n13),
.Z(N13)
);
NANDN U14 (
.B... | 6.813309 |
module dotproduct5 (
clk,
rst,
g_input,
e_input,
o
);
input [4:0] g_input;
input [4:0] e_input;
input clk, rst;
output o;
wire N7, N8, \popcount[3] , \popcount[2] , \popcount[1] ,
\add_2_root_add_29_I5/carry[1] , \add_2_root_add_29_I5/CI ,
\add_2_root_add_29_I5/A[0] , n... | 7.063443 |
module dotproduct6 (
clk,
rst,
g_input,
e_input,
o
);
input [5:0] g_input;
input [5:0] e_input;
input clk, rst;
output o;
wire N8, N9, N11, N12, \popcount[3] , \popcount[2] , \popcount[1] ,
\add_2_root_add_29_I6/carry[1] , n23, n24, n25, n26, n27, n28, n29,
n30, n31, n3... | 6.791687 |
module dotproduct7 (
clk,
rst,
g_input,
e_input,
o
);
input [6:0] g_input;
input [6:0] e_input;
input clk, rst;
output o;
wire \popcount[3] , n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47;
assign o = \popcount... | 6.674613 |
module dotproduct8 (
clk,
rst,
g_input,
e_input,
o
);
input [7:0] g_input;
input [7:0] e_input;
input clk, rst;
output o;
wire N19, \add_3_root_add_29_I8/carry[2] , n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, ... | 6.902137 |
module dotproduct9 (
clk,
rst,
g_input,
e_input,
o
);
input [8:0] g_input;
input [8:0] e_input;
input clk, rst;
output o;
wire N11, N12, N14, N15, N18, N19, \popcount[3] , \popcount[2] ,
\popcount[1] , N25, N24, N23, \add_4_root_add_29_I9/carry[1] , n33,
n34, n35, n36, ... | 6.847772 |
module dotProduct_1_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.801679 |
module dotProduct_1_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.801679 |
module dotProduct_1_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.801679 |
module dotProduct_1_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.801679 |
module dotProduct_1_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.801679 |
module dotProduct_1_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.801679 |
module dotProduct_2_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.654649 |
module dotProduct_2_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.654649 |
module dotProduct_2_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.654649 |
module dotProduct_2_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.654649 |
module dotProduct_2_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.654649 |
module dotProduct_2_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.654649 |
module dotProduct_3_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.755767 |
module dotProduct_3_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.755767 |
module dotProduct_3_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.755767 |
module dotProduct_3_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.755767 |
module dotProduct_3_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.755767 |
module dotProduct_3_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.755767 |
module dotProduct_4_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.743588 |
module dotProduct_4_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.743588 |
module dotProduct_4_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.743588 |
module dotProduct_4_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.743588 |
module dotProduct_4_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.743588 |
module dotProduct_4_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.743588 |
module dotProduct_5_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 7.046959 |
module dotProduct_5_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 7.046959 |
module dotProduct_5_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 7.046959 |
module dotProduct_5_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 7.046959 |
module dotProduct_5_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 7.046959 |
module dotProduct_5_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 7.046959 |
module dotProduct_6_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.733866 |
module dotProduct_6_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.733866 |
module dotProduct_6_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.733866 |
module dotProduct_6_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.733866 |
module dotProduct_6_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.733866 |
module dotProduct_6_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.733866 |
module dotProduct_7_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.846175 |
module dotProduct_7_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.846175 |
module dotProduct_7_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.846175 |
module dotProduct_7_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.846175 |
module dotProduct_7_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.846175 |
module dotProduct_7_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.846175 |
module dotProduct_8_featcud_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed... | 6.937415 |
module dotProduct_8_featcud (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.937415 |
module dotProduct_8_gradjbC_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 6.937415 |
module dotProduct_8_gradjbC (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 6.937415 |
module dotProduct_8_parabkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.937415 |
module dotProduct_8_parabkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.937415 |
module DOTPRODUCT_MODULE (
input ACLK,
ARESETN,
input [5:0] DEST_I,
input [31:0] A_ELEM0,
A_ELEM1,
A_ELEM2,
A_ELEM3,
A_ELEM4,
A_ELEM5,
A_ELEM6,
A_ELEM7,
input [31:0] B_ELEM0,
B_ELEM1,
B_ELEM2,
B_ELEM3,
B_ELEM4,
B_ELEM5,
B_ELEM6,
B_ELEM7,
ou... | 6.762295 |
module dot_prod_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 30
);
reg clk, rst;
reg [XLEN_PIXEL-1 : 0] x_test;
reg [XLEN_PIXEL-1 : 0] x_sv;
wire [4*XLEN_PIXEL -1 : 0] mac_out;
integer i;
dot_prod uut (
.clk(clk),
.rst(rst),
.x_test(x_test),
.x_sv(x_sv),
.... | 6.907427 |
module dot_adder (
input [6:0] pattern,
input [3:0] dots,
input [1:0] dig_sel,
output reg [7:0] segments
);
always @(dig_sel, pattern, dots)
case (dig_sel)
2'b00: segments = {pattern, !(dots[0])}; // dot sigal needs to be inverted before adding
2'b01: segments = {pattern, !(dots[1]... | 7.597012 |
module dot_display (
clk,
rst,
board,
dot_col,
dot_row,
IsRight
);
input clk;
input rst;
input [17:0] board;
input IsRight;
output [13:0] dot_col;
output [9:0] dot_row;
reg [17:0] board;
reg [13:0] dot_col;
reg [ 9:0] dot_row;
reg [3:0] cnt_row, cnt_fra;
reg [7:0] cnt_col;... | 6.78994 |
module dot_mux (
input [1:0] select,
output reg dot
);
always @(*) begin
case (select)
2'b00: dot = 1;
2'b01: dot = 1;
2'b10: dot = 0;
2'b11: dot = 1;
default: dot = 1;
endcase
end
endmodule
| 8.285353 |
module dot_product #(
parameter N = 8, //the number of the numbers in a row
N_bit = 3, //the number of bits for 8 100 is 3
DW = 8 //the number of buts for each number
) (
input wire [(DW * N) -1 : 0] inp1,
input wire [(DW * N) -1 : 0] inp2,
output wire [(2*DW) + N_bit - 1 : 0] outp
);
//lo... | 7.179877 |
module dot_product_16_8_30_2 (
input clk,
input i_reset,
input [15:0] i_features_0,
input [7:0] i_weights_0,
input [15:0] i_features_1,
input [7:0] i_weights_1,
output [23:0] o_result
);
wire [63:0] chains_0;
wire [23:0] res;
reg [15:0] f_pipeline_0_0;
reg [7:0] w_pipeline_0_0;
re... | 7.079393 |
module dot_product_16_8_30_4 (
input clk,
input i_reset,
input [15:0] i_features_0,
input [7:0] i_weights_0,
input [15:0] i_features_1,
input [7:0] i_weights_1,
input [15:0] i_features_2,
input [7:0] i_weights_2,
input [15:0] i_features_3,
input [7:0] i_weights_3,
output [23:... | 7.079393 |
module inner_product_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
reg reset, enable;
reg tb_clk = 1'b0;
initial begin
#10
//00000010 000001... | 6.900175 |
module dot_ram (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q
);
input [0:0] data;
input [10:0] rdaddress;
input rdclock;
input rden;
input [10:0] wraddress;
input wrclock;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off... | 6.594116 |
module dot_top (
input wire clk,
reset,
input wire [1:0] btn,
input wire [2:0] sw,
output wire hsync,
vsync,
output wire [2:0] rgb
);
// signal declaration
wire [9:0] pixel_x, pixel_y;
wire video_on, pixel_tick;
reg [2:0] rgb_reg;
wire [2:0] rgb_next;
// body
// instantiate ... | 7.364107 |
module double (
reset,
clk,
we_line_drawin,
vsync,
line_drawing_data,
line_drawing_addr_1,
vga_addr_2,
outdata_r,
outdata_g,
outdata_b,
str_line_drawing
);
input reset, clk, we_line_drawin, vsync, line_drawing_data;
input [18 : 0] line_drawing_addr_1, vga_addr_2;
output... | 6.622615 |
module doublediff #(
parameter dw = 28,
parameter dsr_len = 4
) (
input clk,
input [dw-1:0] d_in, // Input data
input g_in, // A gate when set to high differentiates input data
output [dw-1:0] d_out,
output g_out
);
reg signed [dw-1:0] d1 = 0, d2 = 0;
reg valid1 = 0, valid2 = 0;
wir... | 6.944024 |
module doublediff1 (
input clk,
input reset,
input [dw-1:0] d_in,
input [gw-1:0] g_in,
output [dw-1:0] d_out,
output [gw-1:0] g_out
);
parameter dw = 28;
parameter gw = 1;
parameter dsr_len = 4;
reg signed [dw-1:0] d1 = 0, d2 = 0;
wire [gw-1:0] valid1, valid2;
wire [dw-1:0] dpass1, ... | 6.948671 |
module DoubleFifo (
input wire CLK,
input wire RST,
input wire [7:0] data_in,
input wire wren,
input wire buf_sel,
input wire rd_req,
output reg fifo_empty,
output reg [7:0] data_out
);
reg fifo1_rd;
reg fifo1_wr;
wire [7:0] fifo1_q;
wire fifo1_ful... | 7.551764 |
module toplevel (
clock,
reset
);
input clock;
input reset;
reg flop1;
reg flop2;
always @(posedge reset or posedge clock)
if (reset) begin
flop1 <= 0;
flop2 <= 1;
end else begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule
| 8.460384 |
module toplevel (
clock,
reset
);
input clock;
input reset;
reg flop1;
reg flop2;
always @(posedge reset or posedge clock)
if (reset) begin
flop1 <= 0;
flop2 <= 1;
end else begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule
| 8.460384 |
module doubleMotor (
input clk,
input forward,
input turnLeft,
input turnRight,
input tooClose,
output pulseLeft,
output pulseRight,
output reg startCount
);
reg turnForwardL;
reg turnForwardR;
reg turnBackwardL;
reg turnBackwardR;
reg [31:0] countIt;
initial begin
star... | 6.562009 |
module doubleMotor_top (
input clk,
input forward,
input turnLeft,
input turnRight,
output pulseLeft,
input tooClose,
output pulseRight,
output turning
);
doubleMotor bothWheels (
.clk(clk),
.pulseLeft(pulseLeft),
.pulseRight(pulseRight),
.forward(forward)... | 7.117927 |
module DoublePulseGene (
clk,
rst_n,
pulse2start1,
pulse2end1,
pulse2start2,
pulse2end2,
startclock,
gpio
);
input clk;
input rst_n;
input [31:0] pulse2start1;
input [31:0] pulse2end1;
input [31:0] pulse2start2;
input [31:0] pulse2end2;
input startclock;
output reg [5:0] ... | 7.908505 |
module DoubleRegisters (
clk,
bus_in,
bus_out1,
bus_out2,
num1,
num2,
cs_h_in,
cs_l_in,
cs_16_in,
cs_h_out1,
cs_l_out1,
cs_16_out1,
cs_h_out2,
cs_l_out2,
cs_16_out2
);
input [15:0] bus_in;
output reg [15:0] bus_out1, bus_out2;
input [1:0] num1, num2;
i... | 6.873728 |
module is used to transfer 1 bit signal across clock domains.
// It use one DFF_ from the original clock domain and two DFFs from the
// destination clock domain. Metastability is eliminated at the output
// port.
// Name rules: [i/o]_[a/b]SigName
// i/o/r/c is input/output/register/logic
// ... | 7.363285 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_adder_TB ();
reg clk = 0, rst = 1;
reg [63:0] a, b;
wire [63:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
always #10 clk = ~clk; // 25MHz
double_adder double_adder_39759952 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.input_a_ack(a_a... | 6.751429 |
module double_add_tb;
reg clk;
reg [63:0] double_add_a;
reg [63:0] double_add_b;
wire [63:0] double_add_z;
integer double_add_a_file;
integer double_add_b_file;
integer double_add_z_file;
integer double_add_a_count;
integer double_add_b_count;
integer double_add_z_count;
double_add double_add1 (
... | 6.964411 |
module double_ram_asyn (
clk,
rst,
cs,
din_a,
addr_a,
dout_a,
we_a,
oe_a,
din_b,
addr_b,
dout_b,
we_b,
oe_b
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = DATA_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din_a;
i... | 9.003328 |
module double_buffer #(
parameter BUF_SIZE = 9
) (
input clk,
input reset,
input clear,
// Random access interface to RAM
input access_we,
input access_stb,
output access_ok,
input access_done,
input access_skip_read,
input [BUF_SIZE-1:0] access_adr,
output [BUF_SIZE-1:0... | 9.15181 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_ceil_tb;
reg clk;
reg [63:0] double_ceil_a;
wire [63:0] double_ceil_z;
integer double_ceil_a_file;
integer double_ceil_z_file;
integer double_ceil_a_count;
integer double_ceil_z_count;
double_ceil double_ceil1 (
clk,
double_ceil_a,
double_ceil_z
);
initial begin
... | 6.683225 |
module double_click (
button,
single,
double,
clk,
rst_n
);
parameter WAIT_WIDTH = 19;
input button;
output single, double;
input clk, rst_n;
reg btn_now, btn_last, collect;
reg [2:0] click_cnt;
reg [WAIT_WIDTH-1:0] dbl_click_cnt;
// if we are done counting and we have 1 click... | 7.372831 |
module double_core (
clk,
rst,
en,
seed1,
seed2,
seed3,
seed4,
rho,
sqrt_rho_sqr,
S_0,
V_0,
sqrt_delta_t,
theta,
epsilon_sqrt_delta_t,
one_plus_mu_delta_t,
kappa_delta_t,
Price1,
Price2
);
// --- I/O Declaration ---
input clk, rst;
input en;... | 6.983947 |
module double_core (
clk,
rst,
en,
seed1,
seed2,
seed3,
seed4,
rho,
sqrt_rho_sqr,
S_0,
V_0,
sqrt_delta_t,
theta,
epsilon_sqrt_delta_t,
one_plus_mu_delta_t,
kappa_delta_t,
Price1,
Price2
);
input [22:0] seed1;
input [22:0] seed2;
input [22:0] ... | 6.983947 |
module double_dabble #(
parameter WIDTH_I = 8,
parameter WIDTH_O = WIDTH_I + ((WIDTH_I - 4) / 3)
) (
input [WIDTH_I -1:0] binary,
output reg [WIDTH_O:0] bcd
);
initial begin
$display("WIDTH_O:", WIDTH_O);
end
integer i, j;
always @(binary) begin
bcd = 0;
for (i = WIDTH_I - 1; i >= ... | 6.978891 |
module has a latency of 65 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_lin... | 6.771891 |
module double_divider_TB ();
reg clk = 0, rst = 1;
reg [63:0] a, b;
wire [63:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
integer fd;
always #10 clk = ~clk; // 25MHz
double_divider_newton divider_0 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.in... | 7.118947 |
module dual_port_ram (
input wire clk,
input wire en_1,
input wire [ADDR_WIDTH-1:0] addr_1,
input wire [DATA_WIDTH-1:0] write_1,
input wire we_1,
output reg [DATA_WIDTH-1:0] read_1,
input wire en_2,
input wire [ADDR_WIDTH-1:0] a... | 8.55547 |
module count_bits (
input wire [11:0] in,
output wire out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7] ^ in[8] ^ in[9] ^ in[10] ^ in[11];
endmodule
| 6.749928 |
module double_dual_port_ram (
input wire clk,
input wire [11:0] addr_a_1,
input wire [23:0] write_a_1,
input wire en_a_1,
input wire we_a_1, // also used for switching *both* port 1's between reading and writing
output reg [23:0] read_a_1,
input wire [11:0] addr_b_1,
input wire [23:... | 7.195924 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_floor_tb;
reg clk;
reg [63:0] double_floor_a;
wire [63:0] double_floor_z;
integer double_floor_a_file;
integer double_floor_z_file;
integer double_floor_a_count;
integer double_floor_z_count;
double_floor double_floor1 (
clk,
double_floor_a,
double_floor_z
);
initial... | 6.717457 |
module fpu_round (
clk,
rst,
enable,
round_mode,
sign_term,
mantissa_term,
exponent_term,
round_out,
exponent_final
);
input clk;
input rst;
input enable;
input [1:0] round_mode;
input sign_term;
input [55:0] mantissa_term;
input [11:0] exponent_term;
output [63:0] ro... | 6.526875 |
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