code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_inte (
input clk, // timespec 8.4 ns
input signed [dwi-1:0] in, // possibly muxed
output signed [dwo-1:0] out,
input reset // reset integrator to 0
);
parameter dwi = 16; // data width in
parameter dwo=28; // data width out n bits more the in, 2^n should be more than the cic fact... | 7.180855 |
module double_inte_reset (
clk,
in,
out,
reset
);
parameter dwi = 16; // data width in
parameter dwo=28; // data width out n bits more the in, 2^n should be more than the cic factor^2 in sel case, 47^2=2209 adding 12 bit seems a little limited
input clk; // timespec 8.4 ns
input reset;
inpu... | 7.716301 |
module double_inte_smp #(
parameter dwi = 16, // data width in
parameter dwo = 28 // data width out. When used for decimation, output width should
// be dwi + N*log2(decimation rate), where N=2 is the order of this
// double integrator.
) (
input ... | 7.935276 |
module double_latch(
input clk,
input reset,
input async,
output dlatched
);
reg lat1, lat2;
assign dlatched = lat2;
always @(posedge clk)
begin
if (reset) begin
lat1 <= `SD 0;
lat2 <= `SD 0;
end else begin
lat1 <= `SD async;
lat2 <= `SD lat1;
en... | 7.243492 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_lt_tb;
reg clk;
reg [63:0] double_lt_a;
reg [63:0] double_lt_b;
wire [0:0] double_lt_z;
integer double_lt_a_file;
integer double_lt_b_file;
integer double_lt_z_file;
integer double_lt_a_count;
integer double_lt_b_count;
integer double_lt_z_count;
double_lt double_lt1 (
clk,
... | 6.816607 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_max_tb;
reg clk;
reg [63:0] double_max_a;
reg [63:0] double_max_b;
wire [63:0] double_max_z;
integer double_max_a_file;
integer double_max_b_file;
integer double_max_z_file;
integer double_max_a_count;
integer double_max_b_count;
integer double_max_z_count;
double_max double_max1 (
... | 6.54012 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_min_tb;
reg clk;
reg [63:0] double_min_a;
reg [63:0] double_min_b;
wire [63:0] double_min_z;
integer double_min_a_file;
integer double_min_b_file;
integer double_min_z_file;
integer double_min_a_count;
integer double_min_b_count;
integer double_min_z_count;
double_min double_min1 (
... | 6.840227 |
module has a latency of 21 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_lin... | 6.771891 |
module double_multiplier_TB ();
reg clk = 0, rst = 1;
reg [63:0] a, b;
wire [63:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
always #10 clk = ~clk; // 25MHz
double_multiplier double_multiplier_39759952 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.... | 6.968085 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_neg_tb;
reg clk;
reg [63:0] double_neg_a;
wire [63:0] double_neg_z;
integer double_neg_a_file;
integer double_neg_z_file;
integer double_neg_a_count;
integer double_neg_z_count;
double_neg double_neg1 (
clk,
double_neg_a,
double_neg_z
);
initial begin
double_neg_... | 6.823656 |
module double_ne_tb;
reg clk;
reg [63:0] double_ne_a;
reg [63:0] double_ne_b;
wire [0:0] double_ne_z;
integer double_ne_a_file;
integer double_ne_b_file;
integer double_ne_z_file;
integer double_ne_a_count;
integer double_ne_b_count;
integer double_ne_z_count;
double_ne double_ne1 (
clk,
... | 6.736656 |
module**/
module double_ram#(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 4,
parameter RAM_DEPTH = 16
)
(
input WCLK, //write clk
input write, //write en
input [ ADDR_WIDTH - 1:0 ] waddr, //write address from full.v
input [ DATA_WIDTH - 1:0 ] wdata, //write data
input... | 9.033663 |
module double_ram1024x8 (
input [9:0] addr,
input cs,
input rw,
input clk,
inout [15:0] data
);
ram1024x8 ram1 (
.addr(addr),
.cs (cs),
.rw (rw),
.clk (clk),
.data(data[15:8])
);
ram1024x8 ram2 (
.addr(addr),
.cs (cs),
.rw (rw),
.clk (... | 7.179829 |
module double_ram_sy (
clk,
rst,
cs,
din_a,
addr_a,
dout_a,
we_a,
oe_a,
din_b,
addr_b,
dout_b,
we_b,
oe_b,
load
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = ADDR_WIDTH * 10;
input clk, rst, cs;
input [DATA_WIDTH-1:0] din... | 7.6003 |
module double_rategen (
input clk50M,
input rst,
output reg clk70_1,
output reg clk70_2
);
reg [22:0] counter = 0;
localparam value = 714283; //70Hz
always @(posedge clk50M) begin
if (clk70_1 | rst) counter <= 0;
else counter <= counter + 1;
clk70_1 <= counter == value;
clk70_2 ... | 8.109656 |
module DOUBLE_RESET
(
input CLK,
input PLLLKDET,
output GTXTEST_DONE,
output GTXTEST_BIT1
);
reg plllkdet_sync = 1'b0;
reg plllkdet_r = 1'b0;
reg [10:0] reset_dly_ctr = 11'b0;
reg reset_dly_done = 1'b0;
reg [3:0] t... | 6.86422 |
module double_shift_reg (
i_clk,
i_ce,
i_data,
o_data
);
input wire i_clk, i_ce;
input wire i_data;
output wire o_data;
wire a_data, b_data;
shift_reg a (
.i_clk(i_clk),
.i_reset(1'b0),
.i_ce(i_ce),
.i_in(i_data),
.o_bit(a_data)
);
shift_reg b (
.i_clk... | 7.138375 |
module has a latency of 10 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_lin... | 6.771891 |
module double_sync_high (
in_data,
out_clk,
out_rst_n,
out_data
);
parameter WIDTH = 1;
input [WIDTH-1:0] in_data; // Input from Different clock domain
input out_clk; // Output clock
input out_rst_n; // Active low Reset
output [WIDTH-1:0] out_data; // Output Data
reg [WIDTH-1:0] in_d... | 7.313462 |
module double_sync_low (
in_data,
out_clk,
out_rst_n,
out_data
);
parameter WIDTH = 1;
input [WIDTH-1:0] in_data; // Input from Different clock domain
input out_clk; // Output clock
input out_rst_n; // Active low Reset
output [WIDTH-1:0] out_data; // Output Data
reg [WIDTH-1:0] in_da... | 8.185375 |
module double_tones (
PS2_DATA,
PS2_CLK,
clk,
rst,
double,
audio_mclk,
audio_lrclk,
audio_sclk,
audio_sdin,
show,
ssd_ctrl
);
inout PS2_DATA, PS2_CLK;
input clk, rst, double;
output audio_mclk, audio_lrclk, audio_sclk, audio_sdin;
output [7:0] show;
output [3:0] ssd... | 7.945533 |
module has a latency of 2 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_to_int (
clk,
double_to_int_a,
double_to_int_z
);
input clk;
input [63:0] double_to_int_a;
output [63:0] double_to_int_z;
wire [63:0] s_0;
wire [63:0] s_1;
wire [63:0] s_2;
wire [63:0] s_3;
wire [63:0] s_4;
wire [63:0] s_5;
wire [52:0] s_6;
wire [ 0:0] s_7;
wire [ 0:0] ... | 7.213429 |
module double_to_int_tb;
reg clk;
reg [63:0] double_to_int_a;
wire [63:0] double_to_int_z;
integer double_to_int_a_file;
integer double_to_int_z_file;
integer double_to_int_a_count;
integer double_to_int_z_count;
double_to_int double_to_int1 (
clk,
double_to_int_a,
double_to_int_z
)... | 7.213429 |
module has a latency of 1 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_to_unsigned_int (
clk,
double_to_unsigned_int_a,
double_to_unsigned_int_z
);
input clk;
input [63:0] double_to_unsigned_int_a;
output [63:0] double_to_unsigned_int_z;
wire [63:0] s_0;
wire [63:0] s_1;
wire [63:0] s_2;
wire [52:0] s_3;
wire [ 0:0] s_4;
wire [ 0:0] s_5;
wire ... | 6.949311 |
module double_to_unsigned_int_tb;
reg clk;
reg [63:0] double_to_unsigned_int_a;
wire [63:0] double_to_unsigned_int_z;
integer double_to_unsigned_int_a_file;
integer double_to_unsigned_int_z_file;
integer double_to_unsigned_int_a_count;
integer double_to_unsigned_int_z_count;
double_to_unsigned_int doub... | 6.949311 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module double_trunc_tb;
reg clk;
reg [63:0] double_trunc_a;
wire [63:0] double_trunc_z;
integer double_trunc_a_file;
integer double_trunc_z_file;
integer double_trunc_a_count;
integer double_trunc_z_count;
double_trunc double_trunc1 (
clk,
double_trunc_a,
double_trunc_z
);
initial... | 6.970464 |
module double_UART (
input wire clk,
reset,
rx,
input wire [7:0] din,
output wire [7:0] dout,
output wire err,
tx
);
wire tx_full, rx_empty, btn_tick;
wire [7:0] rec_data, rec_data1;
uart_with_parity #( // Default setting:
// 19,200 baud, 8 data bits, 1 stop b... | 7.896351 |
module ram_mod (
input clk,
input rst_n,
input write_en,
input [7:0] write_addr,
input [3:0] write_data,
input read_en,
input [7:0] read_addr,
output reg [3:0] read_data
);
///write enable
reg [3:0] mem[7:0];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) mem[write_... | 7.012862 |
module DouMux(
output[7:0] Dout,
input[3:0] DoutSelect,
input[7:0] PAInBuf,
input[7:0] PAin,
input[7:0] PBInBuf,
input[7:0] PBin,
input[7:0] PCStatus
);
always @(DoutSelect or PAin or PAInBuf or PBin or PBInBuf or PCStatus) begin
case (DoutSelect) begin
3'b000: Dout = PAin;
3'b001... | 7.827547 |
module DOUT_FIB (
input clk_in,
input [1023:0] data_reg, // Data Register, 451 bits
input trig, // Trigger Signal
input [9:0] seq_length,
input clr_2_one,
// 11 -> All zeros
// 01 -> All ones
input clr_mode,
output clk, // .clk(GPIO_0_D[0]), // CLOCK
output [7:0] dout, // .d... | 6.666039 |
module dout_SYN_vJTAG (
input clk_in,
input [1023:0] data_reg, // Data Register, 451 bits
input trig, // Trigger Signal
input [9:0] seq_length,
input clr_2_one,
// 11 -> All zeros
// 01 -> All ones
input clr_mode,
output clk, // .clk(GPIO_0_D[0]), // CLOCK
output dout, // .d... | 6.823928 |
module downcount3_flash (
halfsecclk,
resetn,
counter,
status
);
input halfsecclk, resetn;
output reg [2:0] counter;
output status;
// Turn on/off sevensegs and LEDs.
assign status = !(counter % 2);
always @(posedge halfsecclk or negedge resetn) begin
if (!resetn) counter <= 6;
els... | 6.721043 |
module downcount5 (
secclk,
resetn,
counter
);
input secclk, resetn;
output reg [2:0] counter;
always @(posedge secclk or negedge resetn) begin
if (!resetn) counter <= 5;
else if (counter > 0) counter <= counter - 1;
end
endmodule
| 7.782615 |
module for digital watch
// Last Modified : Date: 2009-03-10
// Revision : Revision: 1
// Copyright (c), Laboratory for Reliable Computing (LaRC), EE, NTHU
// All rights reserved
//************************************************************************
`include "global.v"
module downcounter_2d(
digit1, // 2nd ... | 6.51421 |
module for digital watch
// Last Modified : Date: 2009-03-10
// Revision : Revision: 1
// Copyright (c), Laboratory for Reliable Computing (LaRC), EE, NTHU
// All rights reserved
//************************************************************************
`include "global.v"
module downcounter(
value, // counter ... | 6.51421 |
module DOWNCOUNTER_TB;
reg RST;
reg CLK;
wire [0:3] COUNT;
DOWNCOUNTER uut (
.rst (RST),
.clk (CLK),
.count(COUNT)
);
initial begin
CLK <= 0;
end
always #10 CLK = ~CLK;
initial begin
RST = 1;
#20 RST = 0;
#250 RST = 1;
end
endmodule
| 7.407698 |
module downcount_tb;
// L: Load Counter (if this is on, the counter will never count, only load)
// E: Enable Counter (L needs to be 0 also)
// R: Data from input stream, the counter will load this value
// Q: Counter state, the output
// This testbench will instantiate the downcounter module, load the count... | 7.121406 |
module DOWNSAMP #(
parameter SAMPLE_RATE = 4, // sampling per 2^n data
parameter DATA_WIDTH = 14
) (
input clk,
input rst,
input ena,
input signed [DATA_WIDTH-1:0] dataIn,
output [DATA_WIDTH-1:0] us_dsoutdata,
output signed [DATA_WIDTH-1:0] s_dsoutdata,
output out_en,
input ou... | 8.14912 |
module Downsampler (
input clock,
input reset,
input valid,
input [7:0] data,
output reg [7:0] dataout,
output reg validout,
output reg blankingregion
);
localparam ROW_WITH_PAD = 639;
localparam COL_WITH_PAD = 839;
reg [12:0] rowcounter, colcounter;
wire validoutregin, blanking... | 6.769238 |
module Downsampler4x (
input clock,
input reset,
input valid,
input [7:0] data,
output reg [7:0] dataout,
output reg validout,
output reg blankingregion
);
localparam ROW_WITH_PAD = 319;
localparam COL_WITH_PAD = 419;
reg [12:0] rowcounter, colcounter;
wire validoutregin, blanki... | 6.581485 |
module Downsampler4xWrap (
input clock1,
input clock2,
input reset,
input valid,
input [7:0] data,
output [7:0] dataout,
output blankingregion,
output validout
);
wire [7:0] data_to_fifo_d;
wire [8:0] data_to_fifo;
wire blanking;
wire fifo_wren;
wire [8:0] fifoout;
Downsa... | 6.581485 |
module DownsamplerTest ();
// Clock generation
parameter Halfcycle = 1; // half period is 5 nanoseconds
localparam Cycle = 2 * Halfcycle;
reg Clock;
initial Clock = 0;
always #(Halfcycle) Clock = ~Clock;
// dut test wires
reg rst;
reg validin;
reg [7:0] datain;
wire [7:0] dataout;
wire validou... | 6.891838 |
module DownsamplerWrap (
input clock1,
input clock2,
input reset,
input valid,
input [7:0] data,
output [7:0] dataout,
output blankingregion,
output validout
);
wire [7:0] data_to_fifo_d;
wire [8:0] data_to_fifo;
wire blanking;
wire fifo_wren;
wire [8:0] fifoout;
Downsamp... | 6.653911 |
module
Output clock frequency is the original frequency divided by an even number
*/
module down_clocking_even(
input i_clk,
input i_rst,
input [15:0]i_divisor,
output o_clk
);
wire [15:0]divisor;
wire borrow;
minus_one minus_one_0(
i_divisor,
divisor,
borrow
);
wire go;
assign go=((i_divisor!=0)&&i_rst);
reg [15:0]... | 6.888518 |
module
Output clock frequency is the original frequency divided by an odd number
*/
module down_clocking_odd(
input i_clk,
input i_rst,
input [15:0]i_divisor,
output o_clk
);
reg a,b;
wire c;
assign c=(~a)&(~b);
wire [15:0]divisor;
wire borrow;
minus_one minus_one_0(
i_divisor,
divisor,
borrow
);
wire go;
assign go=... | 6.888518 |
module down_counter (
clk,
rst,
count
);
input rst, clk;
output [3:0] count;
reg [3:0] count;
always @(posedge clk or negedge rst) begin
if (rst == 0) count <= 4'b1111;
else count <= count - 1;
end
endmodule
| 6.658739 |
module: down_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module down_counter_tb;
reg clk;
reg rst;
wire [3:0] count;
down_counter uut (
.clk(clk),
.rst(rst),
.count(... | 6.632049 |
module Down_Counter_Zero #(
parameter WORD_WIDTH = 0
) (
input wire run,
input wire [WORD_WIDTH-1:0] count_in,
input wire load_wren,
input wire [WORD_WIDTH-1:0] load_value,
output reg count_out_wren,
output reg [WORD_WIDTH-1:0] count_o... | 8.259295 |
module Down_FIFO (
wr_data,
wr_en,
wr_clk,
wr_rst,
full,
almost_full,
rd_data,
rd_en,
rd_clk,
rd_rst,
empty,
almost_empty
);
localparam ADDR_WIDTH = 8; //@IPC int 4,10
localparam DATA_WIDTH = 24; //@IPC int 1,256
localparam OUT_REG = 0; //@IPC bool
lo... | 7.799642 |
module dp_sync_ram (
input rst,
input clk,
// PORT 0
input cs_0,
input we_0,
input oe_0,
input [ADDR_WIDTH-1:0] addr_0,
input [DATA_WIDTH-1:0] data_in_0,
output [DATA_WIDTH-1:0] data_out_0,
... | 8.515088 |
module dpbram18_rfa (
wda,
aa,
wea,
ena,
clka,
rdb,
ab,
enb,
clkb
);
//port A
input [35:0] wda; //write data, port A
// output [35:00] rda; //read data, port A
input [8:0] aa; //address, port A
input wea; //write enable, port A
input ena; //port A enable
input clka... | 7.600663 |
module dpbram18_rfb (
wda,
aa,
wea,
ena,
clka,
rdb,
ab,
enb,
clkb
);
//port A
input [35:0] wda; //write data, port A
// output [35:00] rda; //read data, port A
input [8:0] aa; //address, port A
input wea; //write enable, port A
input ena; //port A enable
input clka... | 7.778769 |
module DPCMChan (
PHI1,
ACLK1,
nACLK2,
RES,
DB,
RnW,
LOCK,
W4010,
W4011,
W4012,
W4013,
W4015,
n_R4015,
n_DMCAB,
RUNDMC,
DMCRDY,
DMCINT,
DMC_Addr,
DMC_Out
);
input PHI1; // PHI1 is used together with the R/W core signal to determine the 65... | 7.284824 |
module DPCM_ControlReg (
ACLK1,
W4010,
DB,
Fx,
n_IRQEN,
LOOPMode
);
input ACLK1;
input W4010;
inout [7:0] DB;
output [3:0] Fx;
output n_IRQEN;
output LOOPMode;
RegisterBit f_reg[3:0] (
.ACLK1(ACLK1),
.ena(W4010),
.d(DB[3:0]),
.q(Fx)
);
RegisterBit loop... | 6.991065 |
module DPCM_IntControl (
RES,
W4015,
n_R4015,
n_IRQEN,
AssertInt,
DB,
DMCINT
);
input RES;
input W4015;
input n_R4015;
input n_IRQEN;
input AssertInt;
inout [7:0] DB;
output DMCINT;
wire int_ff_nq;
rsff_2_4 int_ff (
.res1(W4015),
.res2(n_IRQEN),
.res3(R... | 7.739081 |
module DPCM_SampleCounterControl (
nACLK2,
ACLK1,
ACLK2,
PCMDone,
DMCFinish,
DMCEnable,
DFLOAD,
DSLOAD,
DSSTEP,
NSTEP,
CTRL2
);
input nACLK2;
input ACLK1;
input ACLK2;
input PCMDone;
input DMCFinish;
input DMCEnable;
input DFLOAD;
output DSLOAD;
output DSST... | 7.071712 |
module DPCM_SampleBufferControl (
nACLK2,
ACLK1,
ACLK2,
PHI1,
RES,
LOCK,
DFLOAD,
DOUT,
n_NOUT,
n_DMCAB,
BLOAD,
BSTEP,
PCM,
DSTEP,
DMC1,
CTRL1
);
input nACLK2;
input ACLK1;
input ACLK2;
input PHI1;
input RES;
input LOCK;
input DFLOAD;
input... | 6.962097 |
module DPCM_Decoder (
Fx,
FR
);
input [3:0] Fx;
output [8:0] FR;
wire [15:0] Dec1_out;
DPCM_Decoder1 dec1 (
.Dec1_in (Fx),
.Dec1_out(Dec1_out)
);
DPCM_Decoder2 dec2 (
.Dec2_in (Dec1_out),
.Dec2_out(FR)
);
endmodule
| 7.711627 |
module DPCM_LFSRBit (
ACLK1,
load,
step,
val,
sin,
sout
);
input ACLK1;
input load;
input step;
input val;
input sin;
output sout;
wire d;
wire in_latch_nq;
assign d = load ? val : (step ? sin : 1'bz);
dlatch in_latch (
.d (d),
.en(1'b1),
.nq(in_latch_nq... | 6.644547 |
module DPCM_SampleCounterReg (
ACLK1,
W4013,
DB,
DSC
);
input ACLK1;
input W4013;
inout [7:0] DB;
output [7:0] DSC;
RegisterBit scnt_reg[7:0] (
.ACLK1(ACLK1),
.ena(W4013),
.d(DB[7:0]),
.q(DSC[7:0])
);
endmodule
| 7.071712 |
module DPCM_SampleCounter (
ACLK1,
RES,
DSLOAD,
DSSTEP,
DSC,
SOUT
);
input ACLK1;
input RES;
input DSLOAD;
input DSSTEP;
input [7:0] DSC;
output SOUT;
wire [11:0] cout;
DownCounterBit cnt[11:0] (
.ACLK1(ACLK1),
.d({DSC[7:0], 4'b0000}),
.load(DSLOAD),
.c... | 7.071712 |
module DPCM_SampleBitCounter (
ACLK1,
RES,
NSTEP,
n_NOUT
);
input ACLK1;
input RES;
input NSTEP;
output n_NOUT;
wire [2:0] cout;
CounterBit cnt[2:0] (
.ACLK1(ACLK1),
.d(3'b000),
.load(RES),
.clear(RES),
.step(NSTEP),
.cin({cout[1:0], 1'b1}),
.cout... | 7.973448 |
module DPCM_SampleBuffer (
ACLK1,
RES,
BLOAD,
BSTEP,
PCM,
DB,
n_BOUT
);
input ACLK1;
input RES;
input BLOAD;
input BSTEP;
input PCM;
inout [7:0] DB;
output n_BOUT;
wire [7:0] buf_nq;
wire [7:0] sout;
RegisterBit buf_reg[7:0] (
.ACLK1(ACLK1),
.ena(PCM),
... | 6.962097 |
module DPCM_SRBit (
ACLK1,
clear,
load,
step,
n_val,
sin,
sout
);
input ACLK1;
input clear;
input load;
input step;
input n_val;
input sin;
output sout;
wire d;
wire in_latch_nq;
assign d = clear ? 1'b0 : (load ? n_val : (step ? in_latch_nq : (ACLK1 ? ~sout : 1'bz)));
... | 7.254655 |
module DPCM_AddressReg (
ACLK1,
W4012,
DB,
DPA
);
input ACLK1;
input W4012;
inout [7:0] DB;
output [7:0] DPA;
RegisterBit addr_reg[7:0] (
.ACLK1(ACLK1),
.ena(W4012),
.d(DB[7:0]),
.q(DPA[7:0])
);
endmodule
| 7.033189 |
module DPCM_AddressCounter (
ACLK1,
RES,
DSLOAD,
DSSTEP,
DPA,
DMC_Addr
);
input ACLK1;
input RES;
input DSLOAD;
input DSSTEP;
input [7:0] DPA;
output [15:0] DMC_Addr;
wire [7:0] addr_lo_cout;
wire [6:0] addr_hi_cout;
wire [7:0] addr_lo_q;
wire [6:0] addr_hi_q;
CounterBit... | 7.477853 |
module DPCM_Output (
ACLK1,
RES,
W4011,
CountDown,
DSTEP,
DB,
DMC_Out,
DOUT
);
input ACLK1;
input RES;
input W4011;
input CountDown;
input DSTEP;
inout [7:0] DB;
output [6:0] DMC_Out;
output DOUT;
wire out_reg_q;
wire [5:0] out_cnt_q;
wire [5:0] cout;
RevCounte... | 7.26531 |
module DPCMDecoder_Run ();
reg [3:0] val;
wire [3:0] Dec_in;
wire [8:0] Dec_out;
always #1 val = val + 1;
assign Dec_in = val;
DPCM_Decoder dec (
.Fx(Dec_in),
.FR(Dec_out)
);
initial begin
$dumpfile("dpcm_decoder.vcd");
$dumpvars(0, dec);
val <= 0;
repeat (17) @(val);... | 8.463842 |
module DPCMChan_Run ();
reg CLK;
reg RES;
wire PHI1;
wire RnW;
wire nACLK2;
wire ACLK1;
reg W4010;
reg W4011;
reg W4012;
reg W4013;
reg W4015;
reg n_R4015;
wire [7:0] DataBus;
wire [31:0] AuxOut;
wire n_DMCAB; // 0: Gain control of the address bus to read the DPCM sample
wire RUNDM... | 6.972046 |
module executes a "program" sequence of writes to the DPCM registers
module DPCMRegMaster (W4010, W4012, W4013, W4015, DataBus);
input W4010;
input W4012;
input W4013;
input W4015;
inout [7:0] DataBus;
//LDA #$E
//STA $4010
//LDA #$C0
//STA $4012
//LDA #$FF
//STA $4013
//LDA #$F
//STA $4015
//LDA #$1F
... | 7.110462 |
module DPCMSampleMem (
addr,
data,
ReadMode
);
input [15:0] addr; // address bus
inout [7:0] data; // data bus
input ReadMode; // 1: read mode
reg [7:0] mem[0:65535];
reg [7:0] temp_data;
initial begin
$readmemh("dpcm_sample.mem", mem, `SampleAddr);
end
always @(posedge ReadMode) ... | 8.208161 |
module dpedg_wClear (
Clr,
Clk,
D,
Q
);
input D, Clk, Clr;
output reg Q;
reg Qm;
always @(D, Clk, Clr) begin
if (~Clr) begin
Qm = 0;
Q = 0;
end else begin
if (~Clk) Qm = D;
else Q = Qm;
end
end
endmodule
| 7.396353 |
module dpe_timer (
clk,
rst_n,
start,
stop,
timeout
);
input clk;
input rst_n;
input start;
input stop;
output timeout;
parameter VALUE = 20;
parameter WIDTH = 5;
reg [WIDTH-1 : 0] timer_cnt;
always @(posedge clk or negedge ... | 7.867252 |
module dphy (
/* byte clock */
input wire byte_clk,
/* bit clock: 4x byte clock */
input wire bit_clk,
/* reset signal */
input wire byte_rst,
bit_rst,
/* data */
input wire [7:0] data,
/* data ready */
input wire enable,
/* data accepted */
output wire ack,
/* ... | 8.449327 |
module dphy_dummy_ipgen_lscc_clock_divider #(
parameter integer TGT_FREQ_IN = 100
) (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// target frequency in 24 - 200... | 7.871867 |
module dphy_iserdes (
input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)
input [1:0] din, // Input from arch DDR primitive, D1 should be the bit after D0
input sys_clk, // System byte clock
input areset, // Active high async reset
output [7:0] dout // Output data
);
parameter REG_INPUT = 1... | 6.583989 |
module dphy_oserdes (
input sys_clk, // System byte clock
input areset, // Active high async reset
input [7:0] din, // Input from CSI-2 packetiser
input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)
output reg [1:0] dout // Output data, bit 1 should be the second bit transmitted
);
paramete... | 6.579261 |
module dphy_serdes #(
parameter g_delay = 0
) (
input clk_serdes_i,
input clk_word_i,
input rst_n_a_i,
input strobe_i,
input oe_i,
input [7:0] d_i,
output q_p_o,
output q_n_o,
output tq_o
);
wire tq_int;
wire dout_int, dout_predelay;
wire ms_d, ms_t, sm_d, sm_t;
assi... | 6.988688 |
module dphy_top (
input clock,
output lcd_1v8_en,
output lcd_3v0_en,
output lcd_rst,
output [1:0] LPCLK,
output [1:0] LPDATA,
output DCK_P,
output DCK_N,
output DATA_P,
output DATA_N
);
wire dck_int;
wire ddr_c... | 7.116282 |
module Dpipe (
clk,
clr,
en,
npcout,
iseret,
instr_i,
pc8_i,
bd_i,
exccode_i,
instr_d,
pc8_d,
bd_d,
exccode_d
);
input clk, clr, en, bd_i, iseret;
input [31:0] instr_i, pc8_i, npcout;
input [4:0] exccode_i;
output reg [31:0] instr_d, pc8_d;
output reg bd_d;
... | 7.108015 |
module dpi_memory (
input clk,
input rst,
input re,
input [AWIDTH-1:0] raddr,
output reg [DWIDTH-1:0] rdata,
input we,
input [AWIDTH-1:0] waddr,
input [DWIDTH-1:0] wdata
);
parameter AWIDTH = 16;
parameter DWIDTH = 16;
parameter INSTANCE = 0;
import "DPI-C" function void dpi_m... | 8.270733 |
module dpi_recevier #(
parameter INPUT_RESOLUTION_H = 640,
parameter INPUT_RESOLUTION_V = 480,
parameter WHOLE_LINE = 800,
parameter WHOLE_FRAME = 525,
parameter BACK_PORCH_V = 33,
parameter BACK_PORCH_H = 48,
parameter FRONT_PORCH_V = 16,
parameter FRONT_PORCH_H = 10
) (
input CLK,
... | 6.824445 |
module dpi_sync_detector #(
parameter TARGET_FREQ = 25175,
parameter TARGET_WIDTH = 640,
parameter HYSTERESIS_FREQ = 256,
parameter HYSTERESIS_WIDTH = 2
) (
input CLK,
input RESET,
input [15:0] FREQ,
input [10:0] WIDTH,
output IS_SYNC
);
reg is_sync;
wire is_freq_ok, is_width_... | 8.126364 |
module */
module dpll(SignalIn, SignalOut, MainClock,
Positive, Negative, Lead, Lag
);
input SignalIn; // input signal
input MainClock; // reference signal
output SignalOut; // output
output Positive, Negative; // internal DPLL signals
output Lea... | 7.683765 |
module freqdivider (
MainClock,
Positive,
Negative,
FrequencyOut
);
input MainClock; // main clock
input Positive, Negative; // signals Positive, Negative are synchronous with MainClock
output FrequencyOut; // output frequency
/* needed counter length */
parameter DividerLength = 7;
/* ... | 7.749213 |
module phasecomparator (
InputSignal,
OutputSignal,
MainClock,
Lead,
Lag
);
input InputSignal, OutputSignal; // PLL input(reference) and output(dejittered clock) signals
input MainClock; // System Clock
output Lead, Lag; // Lead and Lag signals
reg [1:0] InputSignalEdgeDet; // detector... | 8.807653 |
module
SXP Processor
Sam Gladstone
This can not be synthesized!
The purpose is to emmulate standard dual port memories.
*/
module dpmem ( clk,
reset_b,
addra, // address a port
addrb, // address b port
wea, // write enable a
web, // write enable b
oea, // output ena... | 7.705169 |
module dpMem_dc (
addrIn,
addrOut,
wrClk,
rdClk,
dataIn,
writeEn,
readEn,
dataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input wrClk;
input rdClk;
input [FIFO_WIDTH-1:0] dataIn;
output [FIFO_WIDTH-1:0... | 6.941014 |
module dpMem_dc_simlib (
addrIn,
addrOut,
wrClk,
rdClk,
dataIn,
writeEn,
readEn,
dataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input wrClk;
input rdClk;
input [FIFO_WIDTH-1:0] dataIn;
output [FIFO_WI... | 6.680383 |
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