code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dport_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
//... | 7.672013 |
module dport_bridge_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------... | 7.166726 |
module dport_ram
#(
parameter DATA_WIDTH=8,
parameter ADDR_WIDTH=36
)(
input clk,
input [(DATA_WIDTH-1):0] di,
input [(ADDR_WIDTH-1):0] read_addr,
input [(ADDR_WIDTH-1):0] write_addr,
input we,
output reg [(DATA_WIDTH-1):0] do
);
localparam ACTUAL_ADDR_WIDTH=16; //due to small size of internal ... | 8.034964 |
module dpram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
(
input clock,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
output [DATAWIDTH-1:0] q_a,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:0] data_b... | 7.91975 |
module dpram1 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteen_a,
byteen_b,
out_a,
out_b
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 32;
parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input [(AWIDTH-1):0] addres... | 6.95423 |
module dpram1024x24 (
wr_clk_i,
rd_clk_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
);
input wr_clk_i;
input rd_clk_i;
input wr_clk_en_i;
input rd_en_i;
input rd_clk_en_i;
input wr_en_i;
input [23:0] wr_data_i;
input [9... | 6.565811 |
module dpram1024x24 (
wr_clk_i,
rd_clk_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input wr_clk_en_i;
input rd_en_i;
input rd_clk_en_i... | 6.565811 |
module dpram1024x8 (
wr_clk_i,
rd_clk_i,
rst_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input rst_i;
input wr_clk_en_i;
input rd_... | 6.556983 |
module dpram128x24 (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
input [23:0] data;
input wren;
input [6:0] wraddress;
input [6:0] rdaddress;
input wrclock;
input rdclock;
output [23:0] q;
dpram128x24_bb ram1 (
.data(data),
.wren(wren),
.wrad... | 7.210445 |
module dpram_512x32 (
input clk,
input wen,
input ren,
input [0:8] waddr,
input [0:8] raddr,
input [0:31] d_in,
output [0:31] d_out
);
dpram_512x32_core memory_0 (
.wclk(clk),
.wen(wen),
.waddr(waddr),
.data_in(d_in),
.rclk(clk),
.ren(ren),
.raddr... | 7.614009 |
module dpram_512x32_core (
input wclk,
input wen,
input [0:8] waddr,
input [0:31] data_in,
input rclk,
input ren,
input [0:8] raddr,
output [0:31] d_out
);
reg [0:31] ram[0:511];
reg [0:31] internal;
assign d_out = internal;
always @(posedge wclk) begin
if (wen) begin
... | 7.184075 |
module dpram_128x8 (
input clk,
input wen,
input ren,
input [0:6] waddr,
input [0:6] raddr,
input [0:7] d_in,
output [0:7] d_out
);
dpram_128x8_core memory_0 (
.wclk(clk),
.wen(wen),
.waddr(waddr),
.data_in(d_in),
.rclk(clk),
.ren(ren),
.raddr(rad... | 7.564563 |
module dpram_128x8_core (
input wclk,
input wen,
input [0:6] waddr,
input [0:7] data_in,
input rclk,
input ren,
input [0:6] raddr,
output [0:7] d_out
);
reg [0:7] ram[0:127];
reg [0:7] internal;
assign d_out = internal;
always @(posedge wclk) begin
if (wen) begin
ram... | 6.877201 |
module dpram2048x16 (
wr_clk_i,
rd_clk_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
);
input wr_clk_i;
input rd_clk_i;
input wr_clk_en_i;
input rd_en_i;
input rd_clk_en_i;
input wr_en_i;
input [15:0] wr_data_i;
input [1... | 6.571586 |
module dpram2048x16 (
wr_clk_i,
rd_clk_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input wr_clk_en_i;
input rd_en_i;
input rd_clk_en_i... | 6.571586 |
module dpram2048x8 (
wr_clk_i,
rd_clk_i,
rst_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input rst_i;
input wr_clk_en_i;
input rd_... | 6.59317 |
module dpram256x16 (
wr_clk_i,
rd_clk_i,
rst_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input rst_i;
input wr_clk_en_i;
input rd_... | 6.956288 |
module dpram256x32 (
wr_clk_i,
rd_clk_i,
rst_i,
wr_clk_en_i,
rd_en_i,
rd_clk_en_i,
wr_en_i,
wr_data_i,
wr_addr_i,
rd_addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input wr_clk_i;
input rd_clk_i;
input rst_i;
input wr_clk_en_i;
input rd_... | 6.829614 |
module dpram2 (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [7:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QI... | 6.610551 |
module dpram32 #(
parameter AWIDTH = 15,
parameter RAM_SIZE = 16384
) (
input clk,
input [AWIDTH-1:0] adr1_i,
input [31:0] dat1_i,
output reg [31:0] dat1_o,
input we1_i,
input en1_i,
input [3:0] sel1_i,
input [AWIDTH-1:0] adr2_i,
input [31:0] dat2_i,
output reg [31:0]... | 7.973818 |
module dpram40x256 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock_a,
enable_a,
clock_b,
enable_b,
q_a,
q_b
);
input [39:0] data_a;
input wren_a;
input [7:0] address_a;
input [39:0] data_b;
input [7:0] address_b;
input wren_b;
input clock_a;
... | 6.877326 |
module dpram512w (
addra,
addrb,
clka,
clkb,
dina,
douta,
doutb,
wea
); // synthesis black_box
input [8 : 0] addra;
input [8 : 0] addrb;
input clka;
input clkb;
input [31 : 0] dina;
output [31 : 0] douta;
output [31 : 0] doutb;
input wea;
// synopsys translate_off
... | 7.249013 |
module dpram64 #(
parameter SIZE = 0,
parameter mem_clear = 0,
parameter memfile = ""
) (
input wire clk,
input wire [7:0] we,
input wire [63:0] din,
input wire [$clog2(SIZE)-1:0] waddr,
input wire [$clog2(SIZE)-1:0] raddr,
output reg [63:0] dout
);
localparam AW = $clog2... | 7.255664 |
module of dual port RAM 1024 addresses x 8 bit
// Coder : Xifan tang
//-----------------------------------------------------
module dpram_1024x8 (
input clk,
input wen,
input ren,
input[0:9] waddr,
input[0:9] raddr,
input[0:7] data_in,
output[0:7] data_out );
dpram_1024x8_core memory_0 (
... | 7.637335 |
module of dual port RAM 1024 addresses x 8 bit
// Coder : Xifan tang
//-----------------------------------------------------
module dpram_1024x8_core (
input wclk,
input wen,
input [0:9] waddr,
input [0:7] data_in,
input rclk,
input ren,
input [0:9] raddr,
output [0:7] data_out );
reg[0:7] ram[... | 7.637335 |
modules)
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module DPR2KV
(
input CL0,
input [10:0] AD0,
input EN0,
input WR0,
input [7:0] DI0,
output [7:0] DO0,
input ... | 7.049601 |
module DPR2K (
input CL0,
input [10:0] AD0,
input EN0,
input WR0,
input [ 7:0] DI0,
output reg [ 7:0] DO0,
input CL1,
input [10:0] AD1,
input EN1,
input WR1,
input [ 7:0] DI1,
out... | 6.741712 |
module LBUF1K (
input CL0,
input [9:0] AD0,
input WR0,
input [7:0] DI0,
input CL1,
input [9:0] AD1,
input WR1,
input [7:0] DI1,
output [7:0] DO1
);
dpram #(10, 8) lbuf (
.clock_a(CL0),
.address_a(AD0),
.data_a(DI0),
.wren_a(WR0)... | 6.582694 |
module DLROM #(
parameter AW,
parameter DW
) (
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [DW-1:0] core[0:((2**AW)-1)] /* synthesis ramstyle = "no_... | 6.544719 |
module dpram_1024_40bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 6.916304 |
module dpram_1024_60bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 6.674433 |
module dpram_1024_64bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 64;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inp... | 6.976284 |
module dpram_16x32 (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
input [31:0] data;
input wren;
input [3:0] wraddress;
input [3:0] rdaddress;
input wrclock;
input rdclock;
output [31:0] q;
dpram_16x32_bb ram1 (
.data(data),
.wren(wren),
.wrad... | 7.354932 |
module dpram_16x32_bb (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q);
input [31:0] data;
input wren;
input [3:0] wraddress;
input [3:0] rdaddress;
input wrclock;
input rdclock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_componen... | 6.641698 |
module dpram_2048x8 (
input clk,
input wen,
input ren,
input [0:10] waddr,
input [0:10] raddr,
input [0:7] data_in,
output [0:7] data_out
);
dpram_2048x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (data_in),
.rclk (clk),
... | 7.169091 |
module of dual port RAM 2048 addresses x 8 bit
// Coder : Xifan tang
//-----------------------------------------------------
module dpram_2048x8_core (
input wclk,
input wen,
input[0:10] waddr,
input[0:7] data_in,
input rclk,
input ren,
input[0:10] raddr,
output[0:7] data_out );
reg[0:7] ram[0:... | 7.637335 |
module dpram_2048_32bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 32;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inp... | 6.745551 |
module dpram_2048_40bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 7.111127 |
module dpram_2048_60bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 6.99541 |
module dpram_2048_64bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 64;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inp... | 7.026407 |
module dpram_256x32 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
... | 6.887658 |
module dpram_256x32 (
aclr,
clock,
data,
enable,
rdaddress,
wraddress,
wren,
q
);
input aclr;
input clock;
input [31:0] data;
input enable;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
... | 6.887658 |
module dpram_256x8 (
data,
wren,
wraddress,
rdaddress,
wrclock,
wrclocken,
rdclock,
rdclocken,
q
);
input [7:0] data;
input wren;
input [7:0] wraddress;
input [7:0] rdaddress;
input wrclock;
input wrclocken;
input rdclock;
input rdclocken;
output [7:0] q;
dpram... | 6.627136 |
module
KEYWORDS: dpram
MODIFICATION HISTORY:
$Log$
Xudong 18/6/20 original version
\*-------------------------------------------------------------------------*/
module dpram_2p
#(
parameter LOG2N = 6, // 这是FIFO深度的对数值
parameter N = (1<<LOG2N), // FIFO的深度
parameter DATA_WIDTH = 32, // 数据宽度
parameter AD... | 7.592673 |
module dpram_32x32 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock_a,
enable_a,
clock_b,
enable_b,
q_a,
q_b
);
input [31:0] data_a;
input wren_a;
input [5:0] address_a;
input [31:0] data_b;
input [5:0] address_b;
input wren_b;
input clock_a;
... | 7.422458 |
module dpram_32x32_bb (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock_a,
enable_a,
clock_b,
enable_b,
q_a,
q_b);
input [31:0] data_a;
input wren_a;
input [5:0] address_a;
input [31:0] data_b;
input [5:0] address_b;
input wren_b;
input clock_a;
input enable_a;
input cloc... | 6.759906 |
module dpram_4096x32 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input rden_a;
input rden_b;
input wren_a;
... | 6.768223 |
module dpram_4096x32 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input rden_a;
... | 6.768223 |
module dpram_4096_40bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 7.233774 |
module dpram_4096_60bit (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
inpu... | 7.134998 |
module dpram_altera #(
parameter ADDR_WIDTH = 3
)
(
input clk_a,
input [ADDR_WIDTH-1:0] addr_a,
input [3:0] we_a,
input [31:0] di_a,
output [31:0] do_a,
input clk_b,
input [ADDR_WIDTH-1:0] addr_b,
input [3:0] we_b,
input [31:0] di_b,
output [31:0] do_b
);
altsyncram altsyncram_component (
... | 7.442084 |
module dpram_async #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter CLEAR_ON_INIT = 1,
parameter ENABLE_BYPASS = 1
) (
clk,
rst,
raddr,
re,
waddr,
we,
din,
dout
);
/*
Ports
*/
input clk;
input rst;
input [ADDR_WIDTH-1:0] raddr;
input re;
i... | 7.624209 |
module DPRAM (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [11:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifnd... | 7.9191 |
module dpram_bbs #(
parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter BYPS = 1, // bypass? 0:none; 1: single-stage; 2: two-stage
parameter ZERO = 0, // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization hex file (don... | 9.803698 |
module dpram #(parameter ADDR_WIDTH=6 ,DATA_WIDTH=8) (
02 input [(DATA_WIDTH-1):0] data,
03 input [(ADDR_WIDTH-1):0] read_addr,
04 input [(ADDR_WIDTH-1):0] write_addr,
05 input we,
06 input clk,
07 output [(DATA_WIDTH-1):0] q );
08 reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
09 `ifdef DPRAM_OLD_DATA
10 ... | 7.91975 |
module dpram_generic #(
parameter ADDR_WIDTH = 3
) (
input clk_a,
input [ADDR_WIDTH-1:0] addr_a,
input [3:0] we_a,
input [31:0] di_a,
output reg [31:0] do_a,
input clk_b,
input [ADDR_WIDTH-1:0] addr_b,
input [3:0] we_b,
input [31:0] di_b,
output reg [31:0] do_b
);
reg [7:... | 7.903118 |
module dpram_inf_256x32 (
input wire clock,
input wire wren_a,
input wire [ 8-1:0] address_a,
input wire [32-1:0] data_a,
output reg [32-1:0] q_a,
input wire wren_b,
input wire [ 8-1:0] address_b,
input wire [32-1:0] data_b,
output reg [32-1:0] q_b... | 7.358206 |
module dpram_inf_be_1024x16 (
input wire clock,
input wire wren_a,
input wire [ 2-1:0] byteena_a,
input wire [10-1:0] address_a,
input wire [16-1:0] data_a,
output reg [16-1:0] q_a,
input wire wren_b,
input wire [ 2-1:0] byteena_b,
input wire [10-1... | 7.189224 |
module dpram_sclk #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter CLEAR_ON_INIT = 1,
parameter ENABLE_BYPASS = 1
) (
clk,
rst,
raddr,
re,
waddr,
we,
din,
dout
);
/*
Ports
*/
input clk;
input rst;
input [ADDR_WIDTH-1:0] raddr;
input re;
in... | 6.931162 |
module dpram_sim (
/********** Port A: IF Stage **********/
input clock_a, // Clock
input [11:0] address_a, // Address
input [31:0] data_a, // Write data (Not Connected)
input wren_a, // Write enable A (Disable)
output [31:0] q_a, // Read data
/**********... | 7.293782 |
module dpram_small (
input clk,
input [8:0] address_a,
input [8:0] address_b,
input wren_a,
input wren_b,
input [`DATA_WIDTH-1:0] data_a,
input [`DATA_WIDTH-1:0] data_b,
output reg [`DATA_WIDTH-1:0] out_a,
output reg [`DATA_WIDTH-1:0] out_b
);
`ifdef SIMULATION_MEMORY
reg [`DATA... | 7.64722 |
module dpram_sram_controller (
input logic Clock_50,
input logic resetn,
input logic ws_en,
output logic [ 6:0] DP_RAM_Address,
input logic [31:0] DP_RAM_Read_Data,
output logic [15:0] SRAM_write_data,
output logic [17:0] SRAM_address,
output logic SRAM_we
);
// Signals needed for ... | 7.138046 |
module dpram_t (
input clk,
input [5:0] address_a,
input [5:0] address_b,
input wren_a,
input wren_b,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_a,
input [((`NUM_WORDS*`DATA_WIDTH)-1):0] data_b,
output reg [((`NUM_WORDS*`DATA_WIDTH)-1):0] out_a,
output reg [((`NUM_WORDS*`DATA_WIDTH)... | 7.034874 |
module dpram_tb ();
reg clock;
reg [7:0] data;
reg [7:0] rdaddress;
reg [7:0] wraddress;
reg wren;
wire [7:0] q;
reg [7:0] i;
initial clock = 0;
always #(`clk_period / 2) clock = ~clock;
initial begin
data = 8'd0;
rdaddress = 8'd0;
wraddress = 8'd0;
wren ... | 6.945654 |
module dpreg (
input [7:0] data, //data to be written
input [2:0] read_addr, //address for read operation
input [2:0] write_addr, //address for write operation
input we, //write enable signal
input clk,
output reg [7:0] q //read ... | 8.018098 |
module dpregtb ;
reg [7:0] data; //data to be written
reg [2:0] read_addr; //address for read operation
reg [2:0] write_addr; //address for write operation
reg we; //write enable signal
reg clk;
wire reg [7:0] q;
dpreg dp1
(
.data (data), //data to be wri... | 8.367321 |
module dprf
//-------------------------------------------------------------------------------------------------
#(
parameter KB = 0
) (
input wire clock,
input wire ce1,
output reg [ 7:0] q1,
input wire [$clog2(KB*1024)-1:0] a1,
inpu... | 6.752667 |
module dprom #(
parameter MEM_INIT_FILE = "",
parameter DATA_WIDTH = 8,
parameter DEPTH = 16384,
parameter ADDRESS_WIDTH = $clog2(DEPTH)
) (
input clk,
input [ADDRESS_WIDTH-1:0] addr,
output reg [ DATA_WIDTH-1:0] dout,
input we_b,
... | 7.862906 |
module implements a parameterized version of a distributed
// RAM synchronous FIFO. The address width, FIFO width and depth
// are all specified by parameters. Default parameters settings
// describe a 16x16 FIFO with Full (FF), Empty (EF), and Half
// Full (HF) fla... | 6.904081 |
module Dpsk (
rst,
clk,
din,
datai,
dataq,
df
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：32MHz
input signed [7:0] din; //输入数据：4MHz
output signed [27:0] datai; //同相支路输出数据
output signed [27:0] dataq; //正交支路输出数据
output signed [27:0] df; //环路滤波器输出数据
//实例化DDS核
wire reset... | 6.92036 |
module dpsk_jt (
input clk_2,
input clk_20,
input clk_4,
input [7:0] tz_seq,
output reg jt_seq
);
reg pre;
reg now;
always @(posedge clk_2) begin
now <= tz_seq[7];
jt_seq <= ~now ^ pre; //quefanyihuo
pre <= now;
end
endmodule
| 7.484651 |
module dpsk_tz (
input clk_2,
input signed [7:0] cos, //tiaozhihoudejibo
input seq,
output reg [7:0] tz_seq,
output reg [9:0] phase
);
initial phase = 0;
always @(negedge clk_2) begin
if (seq == 1) phase <= phase + 10'b0111111111;
end
always @(*) begin
tz_seq <= cos;
end
endmo... | 6.738232 |
module dpsram #(
parameter DATA_WIDTH = 2,
parameter ADDR_WIDTH = 8,
parameter DEPTH = 196,
MEMFILE = ""
) (
input [ADDR_WIDTH-1:0] i_addr0,
i_addr1,
input [DATA_WIDTH-1:0] i_data0,
i_data1,
input i_write0,
i_write1,
i_clk0,
i_clk1,
output [DATA_WIDTH-1:0] o_data0,
... | 8.880466 |
module DPSRAM_tb ();
parameter N = 4;
parameter W = 256;
parameter M = 8;
reg clk;
reg rst;
wire SLP = 1'b0;
wire DSLP = 1'b0;
wire SD = 1'b0;
reg [ 1:0] WTSEL;
reg [ 1:0] RTSEL;
reg VG;
reg VS;
// Input-Output declarations
r... | 6.510238 |
module DPU (
Abus,
Bbus,
Rbus,
n,
cc,
Kbus,
mData
);
//Inputs
input [3:0] Abus;
input [3:0] Bbus;
input [3:0] Rbus;
input [3:0] n;
input [7:0] mData;
//Outputs
output [23:0] Kbus;
output [3:0] cc;
//Memory Block
reg [ 7:0] regFile[15:0];
//Define I/O
wire [ 3:... | 6.516947 |
module DPWM (
clk,
rst,
intlv_phase,
dpwm_duty,
dpwm_angle,
dpwm_s,
dpwm_sb
);
// dpwm_duty must be fed in at positive clock edge so it is stable at negative clock edge
// reset signal must be inserted at negative clock edge so the ramp initial values are loaded properly
input clk;
... | 7.142728 |
module DPWMUPDOWN (
clk,
rst,
dpwm_duty,
dpwm_angle,
dpwm_angle_s,
shflag,
dpwm_s,
dpwm_sb
);
// dpwm_duty must be fed in at positive clock edge so it is stable at negative clock edge
// reset signal must be inserted at negative clock edge so the ramp initial values are loaded prope... | 7.235099 |
module dpwm_tb ();
reg clk;
reg reset;
reg enable;
wire o_c1, o_c2;
reg [4:0] dt1, dt2;
reg [10:0] ton;
dpwm dut (
.i_clk(clk),
.reset(reset),
.enable(enable),
.i_ton(ton),
.i_dt1(dt1),
.i_dt2(dt2),
.c1(o_c1),
.c2(o_c2)
);
initial begin
#1 clk = ... | 6.537396 |
module dp_block_read_first_ram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input wea,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [DATA_WIDTH-1:0] dia,
output [DATA_WIDTH-1:0] dob
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam DAT... | 7.754286 |
module dp_block_write_first_ram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input wea,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [DATA_WIDTH-1:0] dia,
output [DATA_WIDTH-1:0] dob
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam DA... | 7.966768 |
module DP_BRAM #(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 8
) (
input clk,
input [ADDR_WIDTH-1:0] raddr,
input [ADDR_WIDTH-1:0] waddr,
input wr_en,
input [DATA_WIDTH-1:0] data_in,
output reg [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] mem[2**ADDR_WIDTH-1:0];
always ... | 8.14847 |
module PREPDATA (
START,
MEI,
DFLOAT,
BWD,
SRC1,
SRC2,
MSD_1,
MSD_2,
LSD_1,
LSD_2,
LOAD_MSD,
LOAD_LSD1,
LOAD_LSD2
);
input [1:0] START;
input MEI, DFLOAT;
input [1:0] BWD;
input [31:0] SRC1, SRC2;
output [52:32] MSD_1, MSD_2;
output [31:0] LSD_1, LSD_2;
... | 6.757276 |
module DFPU_MUL (
BCLK,
SRC1,
SRC2,
START,
MRESULT,
SRCFLAGS,
OUT
);
input BCLK;
input [31:0] SRC1, SRC2;
input START; // that is START[0]
input [105:0] MRESULT;
input [5:0] SRCFLAGS; // NAN and ZERO flags
output [69:0] OUT; // The result
reg [69:0] OUT;
reg [12:0] expon... | 6.672765 |
module SCANDIG (
DIN,
MBIT,
LBIT,
NONZ
);
input [3:0] DIN;
output MBIT, LBIT, NONZ;
assign MBIT = DIN[3] | DIN[2]; // 1xxx = 11
assign LBIT = DIN[3] | (DIN[3:1] == 3'b001); // 01xx = 10
assign NONZ = (DIN != 4'd0); // 001x = 01
endmodule
| 6.540656 |
module DIVI_PREP (
SRC,
BWD,
NOT_DEI,
EXTDATA,
DOUT,
MSB,
NULL,
MINUS
);
input [31:0] SRC;
input [1:0] BWD;
input NOT_DEI;
input EXTDATA;
output [31:0] DOUT;
output [4:0] MSB;
output NULL;
output MINUS;
reg [31:0] double;
reg [ 2:0] select;
wire [ 1:0] modus;
... | 7.006086 |
module DP_FPU (
BCLK,
FL,
BRESET,
LD_OUT,
WR_REG,
BWD,
FSR,
OPCODE,
SRC1,
SRC2,
START,
CY_IN,
COP_DONE,
COP_OP,
COP_IN,
DONE,
UP_DP,
WREN_L,
CLR_LSB,
DVZ_TRAP,
DP_CMP,
DP_OUT,
DP_Q,
TT_DP,
OVF_BCD,
COP_GO,
COP_OU... | 7.111771 |
module dp_mem (
input clk,
input [63:0] data_in,
input [6:0] wr_adr,
input wr_en,
input [6:0] rd_adr,
output reg [63:0] dat_out
);
reg [63:0] mem[0:127];
always @(posedge clk) begin
if (wr_en) mem[wr_adr] <= data_in;
dat_out <= mem[rd_adr];
end
endmodule
| 7.270943 |
module dp_memory (
input wire clk, // 28MHz
input wire [18:0] a1,
input wire [18:0] a2,
input wire oe1_n,
input wire oe2_n,
input wire we1_n,
input wire we2_n,
input wire [7:0] din1,
input wire [7:0] din2,
output wire [7:0] dout1,
output wire [7:0] dout2,
output reg [18... | 8.380333 |
module contains a flip flop based dual port memory array.
pipelined output
* Its width, depth and address width are configurable.
==============================================================================*/
`timescale 1ns/1ps
module dp_mem_1clk_p #( parameter DATA_WIDTH = 16, ADDR_WIDTH =... | 7.925093 |
module dp_mem_32x16 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [15:0] data;
input [4:0] rdaddress;
input rden;
input [4:0] wraddress;
input wren;
output [15:0] q;
wire [15:0] q0;
reg [15:0] q_reg;
assign q = q_reg;... | 6.899873 |
module dp_mem_32x16 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [15:0] data;
input [4:0] rdaddress;
input rden;
input [4:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`end... | 6.899873 |
module dp_mem_32x32 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input rden;
input [4:0] wraddress;
input wren;
output [31:0] q;
wire [31:0] q0;
reg [31:0] q_reg;
assign q = q_reg;... | 7.20111 |
module dp_mem_32x32 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input rden;
input [4:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`end... | 7.20111 |
module dp_mem_64x16 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [15:0] data;
input [5:0] rdaddress;
input rden;
input [5:0] wraddress;
input wren;
output [15:0] q;
dp_mem #(64, 6, 16) i_dp_mem (
.clk (clock),
... | 7.088482 |
module dp_mem_64x16 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [15:0] data;
input [5:0] rdaddress;
input rden;
input [5:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`end... | 7.088482 |
module dp_ram_256x8_swsr (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren... | 6.795339 |
module dp_ram_256x8_swsr (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [7:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 w... | 6.795339 |
module dp_ram (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q
);
input [7:0] data;
input [5:0] rdaddress;
input rdclock;
input rden;
input [6:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`... | 7.068624 |
module dp_ram (
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
axis_data_count
);
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [7 : 0] s_axis_tdata;
output m_axis_tvalid;
inp... | 7.068624 |
module dp_ram_display #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] rdaddress,
wraddress,
input wren,
rdclock,
wrclock,
output reg [DATA_WIDTH-1:0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(pos... | 7.253487 |
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