code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module is dual port ram with 2 I/O ports
* this ram can read / write data to ports 0 and 1 simulataniously
*
* Author: Kimi
*/
`ifndef _dp_ram_duo
`define _dp_ram_duo
`timescale 1ns /1ps
////////////////////////////////////////////
// start of behavioral RAM implemintation //
////////////////////////////////////... | 8.982457 |
module iob_2p_mem_tb;
// Inputs
reg clk;
//write signals
reg w_en;
reg [`DATA_W-1:0] data_in;
reg [`ADDR_W-1:0] w_addr;
//read signals
reg r_en;
reg [`ADDR_W-1:0] r_addr;
wire [`DATA_W-1:0] data_out;
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
c... | 6.665886 |
module dp_ram_wrap #(
parameter ADDR_WIDTH = 8
) (
clk,
en_a_i,
addr_a_i,
wdata_a_i,
rdata_a_o,
we_a_i,
be_a_i,
en_b_i,
addr_b_i,
wdata_b_i,
rdata_b_o,
we_b_i,
be_b_i
);
//parameter ADDR_WIDTH = 8;
input wire clk;
input wire en_a_i;
input wire [ADDR_WIDTH ... | 7.41462 |
module dp_register_decode (
input clk,
input de,
input [7:0] data,
input [7:0] addr,
input invalidate,
output reg valid,
output reg [ 7:0] revision,
output reg link_rate_2_70,
output reg link_rate_1_62,
output reg extended_framing,
output r... | 6.75957 |
module dp_sram
#(parameter DW = `DATA_SZ,
parameter IW = `TAG_SZ,
parameter ENTRIES = (1 << IW)
)
(
input wire clk,
// Port A
input wire [IW-1:0] a_addr,
output wire [DW-1:0] a_dout,
// Port B
input wire [IW-1:0] b_addr,
input wire b_wren,
input wire... | 7.25008 |
module dp_switch #(
parameter DW = 16
) (
input wire pclk,
input wire aresetn,
input wire [4:0] mode,
input wire [DW-1:0] pixel_tdc,
input wire [DW-1:0] pixel_hist,
input wire [DW-1:0] pixel_peak,
output wire [DW-1:0] pixel_dvp //,
//output wire [DW-1:0] pixel_mipi
);
reg [4:0] m... | 8.065589 |
module dp_switch_tb ();
reg pclk, aresetn;
reg [4:0] mode;
reg [15:0] pixel_tdc, pixel_hist, pixel_peak;
wire [15:0] pixel_dvp; //, pixel_mipi;
initial begin
pclk = 0;
aresetn = 0;
#200 aresetn = 1;
end
always #(5) pclk = ~pclk;
initial begin
pixel_tdc = 16'h0123;
pixel_hist = 16... | 6.657469 |
module dp_sync_fifo #(
parameter WIDTH = 64,
parameter DEPTH = 1024,
parameter AWIDTH = `CLOG2(DEPTH)
) (
input rst,
input clk,
input wra,
input rda,
input [WIDTH-1:0] dina,
output [WIDTH-1:0] douta,
input wrb,
input rdb,
input [WIDTH-1:0] dinb,
ou... | 7.838017 |
module DQ #(
parameter WLI = 1,
WLF = 15,
WL = WLI + WLF
) (
input codeWord,
input signed [WL-1:0] delta,
output reg signed [WL-1:0] dq
);
wire [WL-1:0] deltaDiv, deltaAdd;
assign deltaDiv = delta >>> 1;
ADDER_FIXED_POINT #(
.WI1(WLI),
.WF1(WLF),
.WI2(WLI),
.WF2(WLF... | 6.514634 |
module DualPortedMem(
input clock,
input reset,
input [11:0] io_wrData,
output [11:0] io_rdData,
input [5:0] io_readAddr,
input [5:0] io_writeAddr,
input io_wrEna,
input io_rdEna
);
`ifdef RANDOMIZE_MEM_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef R... | 7.664499 |
module DualPortedMem_32(
input clock,
input reset,
input [11:0] io_wrData,
output [11:0] io_rdData,
input [2:0] io_readAddr,
input [2:0] io_writeAddr,
input io_wrEna,
input io_rdEna
);
`ifdef RANDOMIZE_MEM_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifde... | 7.664499 |
module Max4 (
input [11:0] io_in_0,
input [11:0] io_in_1,
input [11:0] io_in_2,
input [11:0] io_in_3,
output [ 1:0] io_index
);
wire [11:0] _io_max_T_1 = $signed(
io_in_0
) > $signed(
io_in_1
) ? $signed(
io_in_0
) : $signed(
io_in_1
); // @[Max.scala 28:43]
... | 8.359253 |
module DelayBoolNCycles (
input clock,
input io_signal2delay,
output io_delayedSignal
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg temp; // @[utils.scala 103:21]
assign io_delayedSignal = temp; // @[utils.scala 107:20]
always @(posedge clock) begin
temp ... | 6.708437 |
module DqpskMod (
rst,
clk,
din,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：8MHz
input din; //输入数据：2MHz
output signed [15:0] dout;
//首先对输入数据进入寄存器输入
reg dint;
always @(posedge clk) dint <= din;
//实例化码形变换模块
wire [1:0] di, dq;
CodeTrans u1 (
.rst(rst),
.clk... | 7.241357 |
module dqpsk_modulator (
clock,
reset,
data_input,
state
);
input clock, reset;
input [1:0] data_input;
output reg [1:0] state;
always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 0;
end else begin
if (data_input == 2'h0) begin
if (state == 2'h0... | 6.877334 |
module DQReg (
input wire En,
input wire [31:0] D,
input wire clk,
output reg [31:0] Q,
input wire rst
);
always @(posedge clk, posedge rst) begin
if (rst) Q <= 0;
else if (En) Q <= D;
else Q <= Q;
end
endmodule
| 7.874078 |
module dqs_iob (
input MCLK,
input ODDRD1,
input ODDRD2,
input preDQSenL,
inout DQS, //The pin signal
inout DQSL
) /* synthesis syn_sharing = off */;
wire dqsOut;
(* syn_preserve=1, syn_useioff = 1 *)reg DQSenL;
always @(negedge MCLK) DQSenL <= preDQSenL; //Tristate enable
ODDR #(... | 7.148288 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module DR (
input clk,
input [15:0] DR_IN,
output [15:0] DR_OUT
);
reg [15:0] DR_reg = 0;
always @(posedge clk) DR_reg <= DR_IN;
assign DR_OUT = DR_reg;
endmodule
| 7.651054 |
module dr2 (
clk,
rst,
phase,
dr2_in,
dr2_out
);
`include "defines.vh"
input clk, rst;
input [`phase_h:0] phase;
input [31:0] dr2_in;
output reg [31:0] dr2_out;
reg [31:0] dr2_reg;
always @(posedge clk or negedge rst) begin
if (rst == 0) begin
dr2_reg = 32'h00000000;
... | 7.176415 |
module drac_wb_adapter (
// DRAC interface
output drac_srd_o,
output drac_swr_o,
output [ 33:5] drac_sa_o,
output [255:0] drac_swdat_o,
output [ 31:0] drac_smsk_o,
input [255:0] drac_srdat_i,
input drac_srdy_i,
input clk150,
// Wishbone slave
... | 6.8461 |
module dragonball_wbmaster (
clk,
reset_n,
a,
cs_n,
d,
lwe_n,
uwe_n,
oe_n,
dtack_n,
berr,
clk_o,
rst_o,
cyc_o,
stb_o,
adr_o,
sel_o,
we_o,
dat_o,
dat_i,
ack_i,
err_i
);
//
// Parameters
//
parameter adr_hi = 9;
//
// Input... | 8.574483 |
module DragonCapture (
input InternalClock,
output [1:0] LED
);
DragonCore Core (
.Clock(InternalClock),
.LED (LED)
);
endmodule
| 6.675807 |
module DragonRAM (
input Clock,
WriteEnable0,
WriteEnable1,
input [AddressWidth - 1:0] Address0,
Address1,
input [35:0] Data0Write,
Data1Write,
output reg [35:0] Data0Read,
output reg [35:0] Data1Read
);
parameter AddressWidth = 10;
parameter WordCount = 1024;
parameter Source... | 7.1954 |
module DragonCaptureTB;
reg Clock = 0;
wire [1:0] LED;
always #20 Clock = !Clock;
DragonCapture CaptureDevice (
.InternalClock(Clock),
.LED(LED)
);
initial $monitor("T: %t, [%h, %h]", $time, LED[0], LED[1]);
endmodule
| 6.675807 |
module DRALM_W4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:... | 7.101238 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
... | 7.500498 |
module Barrel32L (
input [3:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module DRALM_W5 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// Generate abs values
wire [15:0] x_abs;
wire [15:0] y_abs;
// Going for X_abs
assign x_abs = x ^ {16{x[15]}};
// Going for Y_abs
assign y_abs = y ^ {16{y[15]}};
// LOD x
wire [15:0] kx;
wire zero_x;
wire [3:... | 6.684385 |
module PriorityEncoder_16_old (
input [15:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
16'b0000000000000001: code_o = 4'b0000;
16'b0000000000000010: code_o = 4'b0001;
16'b0000000000000100: code_o = 4'b0010;
16'b0000000000001000: code_o = 4'b0011;
16'b0000000... | 6.599169 |
module PriorityEncoder_16 (
input [15:0] data_i,
output [ 3:0] code_o
);
wire [7:0] tmp0;
assign tmp0 = {
data_i[15], data_i[13], data_i[11], data_i[9], data_i[7], data_i[5], data_i[3], data_i[1]
};
OR_tree code0 (
tmp0,
code_o[0]
);
wire [7:0] tmp1;
assign tmp1 = {
data_i[1... | 6.599169 |
module OR_tree (
input [7:0] data_i,
output data_o
);
wire [3:0] tmp1;
wire [1:0] tmp2;
assign tmp1 = data_i[3:0] | data_i[7:4];
assign tmp2 = tmp1[1:0] | tmp1[3:2];
assign data_o = tmp2[0] | tmp2[1];
endmodule
| 7.726839 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LOD16 (
input [15:0] data_i,
output zero_o,
output [15:0] data_o
);
wire [15:0] z;
wire [ 3:0] select;
wire [ 3:0] zdet;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = data_i[15] | data_i[14] | data... | 7.892753 |
module Barrel16L (
input [15:0] data_i,
input [3:0] shift_i,
output reg [15:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
... | 7.500498 |
module Barrel32L (
input [4:0] data_i,
input [4:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
5'b00000: data_o = data_i;
5'b00001: data_o = data_i << 1;
5'b00010: data_o = data_i << 2;
5'b00011: data_o = data_i << 3;
5'b00100: data_o = data_i << 4;
... | 7.342303 |
module DRAM (
Q,
RST,
CSn,
WEn,
RASn,
CASn,
A,
D
);
parameter word_size = 32; //Word Size
parameter row_size = 11; //Row Size
parameter col_size = 10; //Column Size
parameter addr_size = (row_size > col_size) ? row_size : col_size; //Address Size
parameter addr_size_to... | 8.36472 |
module DRAM16XN #(
parameter data_width = 20
) (
DATA_IN,
ADDRESS,
ADDRESS_DP,
WRITE_EN,
CLK,
O_DATA_OUT,
O_DATA_OUT_DP
);
input [data_width-1:0] DATA_IN;
input [3:0] ADDRESS;
input [3:0] ADDRESS_DP;
input WRITE_EN;
input CLK;
output [data_width-1:0] O_DATA_OUT_DP;
output... | 8.319872 |
module dram16_256 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`if... | 7.136037 |
module dram16_256 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrcloc... | 7.136037 |
module drammem (
input [9:0] ma,
inout [15:0] d,
input ras_n,
input ucas_n,
input lcas_n,
input we_n
);
parameter _verbose_ = 1;
parameter _add_to_addr_ = 0;
parameter _filter_out_ = 32'h91;
parameter _init_ = 1;
reg [15:0] array[0:1048575];
reg [15:0] dout;
reg [19:0] addr;
... | 7.702815 |
module DramReader (
input fclk,
input rst_n,
//AXI port
output M2S_AXI_ACLK,
//
output reg M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output reg [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_A... | 7.648151 |
module DramWriter (
input fclk,
input rst_n,
//AXI port
output M2S_AXI_ACLK,
output reg [31:0] M2S_AXI_AWADDR,
input M2S_AXI_AWREADY,
output reg M2S_AXI_AWVALID,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
input M2S_AXI_WREADY,
output M2S_AXI_WVALID,
outpu... | 6.719503 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM128X1D #(
.INIT(128'b10)
) ram0 (
.WCLK(clk),
.A (sw[6:0]),
.DPRA(sw[13:7]),
.SPO (led[0]),
.DPO (led[1]),
.D (sw[14]),
.WE (sw[... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM256X1D #(
.INIT(256'b10)
) ram0 (
.WCLK(clk),
.A (sw[7:0]),
.DPRA(sw[15:8]),
.SPO (led[0]),
.DPO (led[1]),
.D (sw[14]),
.WE (sw[... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM256X1S #(
.INIT(128'b10)
) ram0 (
.WCLK(clk),
.A (sw[7:0]),
.O (led[0]),
.D (sw[14]),
.WE (sw[15])
);
assign led[15:1] = sw[15:1];
... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32M #(
.INIT_A(64'b10),
.INIT_B(64'b100),
.INIT_C(64'b1000),
.INIT_D(64'b10000)
) ram0 (
.WCLK (clk),
.ADDRA(sw[4:0]),
.ADDRB(sw[4:0]),
... | 7.233807 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32M16 #(
// FIXME: python-fpga_interchange seems to be unable to parse any literal wider than 64-bit
//.INIT_A(128'b00_00_00_00_00_00_00_00_00_00_00_00_00_00_10_11_11_11_0... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X16DR8 #(
.INIT_A(64'b00_00_00_00_00_00_00_00_00_00_00_00_00_00_10_11_01_00_00_00_00_00_00_00_00_00_00_00_00_00_10_01),
.INIT_B(64'b00_00_00_00_00_00_00_00_00_00_00_00_1... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM512X1S #(
.INIT(512'b10)
) ram0 (
.WCLK(clk),
.A (sw[8:0]),
.O (led[0]),
.D (sw[14]),
.WE (sw[15])
);
assign led[15:1] = sw[15:1];
... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64M #(
.INIT_A(64'b10),
.INIT_B(64'b100),
.INIT_C(64'b1000),
.INIT_D(64'b10000)
) ram0 (
.WCLK (clk),
.ADDRA(sw[5:0]),
.ADDRB(sw[5:0]),
... | 7.233807 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64M8 #(
// FIXME: python-fpga_interchange seems to be unable to parse any literal wider than 64-bit
//.INIT_A(128'b10101010101010101010101010101010101010101010101010101010... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X8SW #(
.INIT_A(64'b0000000111111111111111011111100111110001111000011100000110000001),
.INIT_B(64'b0000001111111111111110111111001111100011110000111000001100000010),
... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module dram_2port #(
parameter DWIDTH = 32,
parameter AWIDTH = 9
) (
input clk,
input write,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input [DWIDTH-1:0] wdata,
output [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] ram[(1<<AWIDTH)-1:0];
integer i;
initial for (i... | 7.400069 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM128X1S #(
.INIT(128'b10)
) ram0 (
.WCLK(clk),
.A6 (sw[6]),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1D #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X1D #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module DRAM_32 (
clk,
address,
read,
enable_RW,
size,
data_in,
data_out
);
input clk;
input address;
input read;
RAM_Module RAM[3:0] (
clk,
read,
enable_RW,
address,
data_in,
data_out
);
endmodule
| 6.7928 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK(clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : slice
RAM32X2S #(
.INIT_00(32'b10),
.INIT_01(32'b100)
) ram (
.WCLK(clk),
... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X1S #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram3 (
.WCLK(clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module dram_512 (
address,
clock,
data,
wren,
q
);
input [17:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
wire [1:0] selector;
wire [7:0] q1, q2, q3, q4;
reg wren1 = 0;
reg wren2 = 0;
reg wren3 = 0;
reg wren4 = 0;
parameter DM1 = 2'b00;
paramete... | 7.820773 |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram7 (
.WCLK(clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (... | 7.233807 |
module top_diff (
input wire clk_p,
input wire clk_n,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
wire clk;
IBUFDS ibuf_ds (
.I (clk_p),
.IB(clk_n),
.O (clk)
);
top top_ (
.rx (rx),
.tx (tx),
.sw (sw),
.led(led)... | 7.100684 |
module DRAM_address_mux (
output wire [15:0] outputmux,
input wire [15:0] inputmux1,
input wire [15:0] inputmux2,
input wire start_Tx,
input wire Rx_done
);
assign outputmux = start_Tx ? (Rx_done ? inputmux2 : inputmux2) : (Rx_done ? inputmux1 : inputmux2);
endmodule
| 8.461855 |
module DRAM_Addr_Gen_tb;
reg clk;
reg rst_n;
reg DRAM_Wait_Request;
wire [255:0] DRAM_Write_Data;
wire DRAM_Write_Enable;
wire [4:0] DRAM_Write_Burst_Count;
wire DRAM_Write_Burst_Begin;
wire [24:0] DRAM_Write_Addr;
reg [7:0] BRAM_ready_mask;
reg [255:0] BRAM_rd_data;
wire [7:0] BRAM_rd_request;... | 6.560793 |
module dram (
address,
clock,
data,
wren,
q
);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.54321 |
module dram_bus2 (
i_rstn,
i_ck,
o_rw,
o_csn,
o_address,
i_data,
o_data
);
input i_rstn;
input i_ck;
output reg o_rw; //0:write, 1:read
output reg o_csn; //0:chip select, 1:chip deselect
output reg [3:0] o_address;
input [7:0] i_data;
output [7:0] o_data;
reg [7:0] o_data... | 7.589048 |
module acts as a simple Dual port DRAM with a single BIT width and 8 BIT depth.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Initial Design
//////////////////////////////////////////////////////////////////////////////////
module dram_dp
(
input clk_i,
input rstn_i,
input wr_data_i,
output data_o... | 7.787903 |
module dram_if (
memaddr,
memwr,
memrd,
xram_wdata,
xram_rdata,
dram_rdata,
dram_wr,
dram_rd,
dram_addr,
dram_wdata,
mcu_rab_ack,
mcu_rab_rdata,
mcu_rab_wdata,
mcu_rab_write,
mcu_rab_read,
mcu_rab_addr
);
////////////////////////
// parameters
///... | 8.17631 |
module dram_infrastructure (
reset,
clk_in, //200MHz
clk_in_locked,
dram_clk_0,
dram_clk_90,
dram_clk_div,
dram_rst_0,
dram_rst_90,
dram_rst_div,
clk_out
);
parameter CLK_FREQ = 266;
input reset, clk_in, clk_in_locked;
output dram_clk_0, dram_clk_90, dram_clk_div;
output... | 6.761027 |
module dram_prefetch
#( parameter WIDTH = 24,
parameter MSB = WIDTH-1,
parameter DELAY = 3)
( // DRAM and bus clock
input clock_i,
input reset_i,
// Streaming data interface
// NOTE: Doesn't need to initiate transfers, but data is valid whenever
// ... | 9.755051 |
module dram_read_controller #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 13
) (
input clk,
input rst_n,
input enable,
output reg valid,
output [DATA_WIDTH-1:0] out,
// connect dram
input [DATA_WIDTH-1:0] dram_out,
output dram_read_en,
output [ADDR_WIDTH-1:0] dram_addr... | 9.521755 |
module DRAM_read_data_splitter (
output wire [7:0] output1,
output wire [7:0] output2,
input wire [7:0] inputsplitter
);
assign output1 = inputsplitter;
assign output2 = inputsplitter;
endmodule
| 7.068348 |
module dram_reg_wb_attach (
//memory wb slave IF
wb_clk_i,
wb_rst_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_sel_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
phy_ready,
cal_fail,
dram_reset,
arb_grant
);
parameter CLK_FREQ = 0;
input wb_clk_i;
input wb_rst_i;
in... | 8.445828 |
module dram
(a,
d,
clk,
we,
spo);
input [13:0]a;
input [31:0]d;
input clk;
input we;
output [31:0]spo;
wire [13:0]a;
wire clk;
wire [31:0]d;
wire [31:0]spo;
wire we;
wire [31:0]NLW_U0_dpo_UNCONNECTED;
wire [31:0]NLW_U0_qdpo_UNCONNECTED;
wire [31:0]NLW_U0_qspo_UNCONNECTED;
... | 6.684442 |
module dram_syn_test (
a,
dpra,
clk,
din,
we,
qdpo_ce,
qdpo,
reset_n
);
parameter ADDRESSWIDTH = 6;
parameter BITWIDTH = 1;
parameter DEPTH = 34;
input clk, we, qdpo_ce;
input reset_n;
input [BITWIDTH-1:0] din;
input [ADDRESSWIDTH-1:0] a, dpra;
output [BITWIDTH-1:0] qd... | 7.010821 |
module dram_tb ();
// parameter
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 8;
parameter PERIOD = 10;
// reg
reg clk;
reg we;
reg [DATA_WIDTH-1:0] data;
reg [ADDR_WIDTH-1:0] addr;
// wire
wire [DATA_WIDTH-1:0] q;
// clock
initial begin
clk = 1;... | 7.50952 |
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