code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dram_tester_tb ();
vlog_tb_utils vlog_tb_utils0 ();
reg rst_n, clk;
initial begin
rst_n = 1;
clk = 0;
end
always #5000 clk <= ~clk;
initial begin
#20000 rst_n = 0;
#20000 rst_n = 1;
#50_000_000 $finish;
end
wire [23:0] addr;
wire [15:0] wr_data;
wire wr_en... | 7.077604 |
module DRAM_write_data_mux (
output wire [7:0] outputmux,
input wire [7:0] inputmux1,
input wire [7:0] inputmux2,
input wire select
);
assign outputmux = select ? inputmux1 : inputmux2;
endmodule
| 8.590122 |
module DRAM_write_enable_mux (
output wire outputmux,
input wire inputmux1,
input wire inputmux2,
input wire select
);
assign outputmux = select ? inputmux1 : 0;
endmodule
| 8.187156 |
module draw (
input [7:0] x_in,
input [6:0] y_in,
input [4:0] width,
height,
input [2:0] c_in,
input clk,
reset,
enableDraw,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] c_out,
output done,
input inEraseStateMain
);
reg [7:0] counterX, xOut; //placeholder ... | 7.396902 |
module drawable (
clock,
enable,
reset_n,
height,
width,
x_pos,
y_pos,
colour,
x_out,
y_out,
colour_out,
enable_fcounter,
y_count_done
);
input clock, reset_n, enable, enable_fcounter;
input [10:0] width;
input [10:0] height;
input [10:0] x_pos;
input [10:0]... | 7.664196 |
module boundaries (
signal_go,
clock,
reset_n,
x_out,
y_out,
colour_out,
writeEn
);
input clock, reset_n, signal_go;
wire enable;
output [10:0] x_out;
output [10:0] y_out;
output [2:0] colour_out;
output writeEn;
wire [10:0] width;
wire [10:0] height;
wire [10:0] x_pos;
... | 7.735282 |
module control_boundaries (
colour,
signal_go,
reset_draw,
clock,
reset_n,
width,
height,
x_pos,
y_pos,
draw_done,
enable,
writeEn
);
input clock, reset_n, signal_go;
output reg enable, writeEn, reset_draw;
output reg [10:0] width;
output reg [10:0] height;
outp... | 8.303468 |
module drawBox (
SW,
CLOCK_50, // On Board 50 MHz
KEY, // On Board Keys
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
... | 8.787791 |
module datapath (
input clk,
input resetn,
input [6:0] data_in,
input ld_x,
ld_y,
output reg [6:0] data_x,
data_y
);
reg [6:0] x, y;
// Registers a, b, c, x with respective input logic
always @(posedge clk) begin
if (!resetn) begin
x <= 0;
y <= 0;
end else begin
... | 6.91752 |
module control (
input clk,
input resetn,
input go,
output reg ld_x,
ld_y
);
reg [5:0] current_state, next_state;
localparam S_LOAD_X = 5'd0, S_LOAD_X_WAIT = 5'd1, S_LOAD_Y = 5'd2, S_LOAD_Y_WAIT = 5'd3;
//state table
always @(*) begin : state_table
case (current_state)
S_LOAD_X:... | 7.715617 |
module drawbuf (
clk,
X,
Y,
out_R,
out_G,
out_B,
ram_addr,
ram_in
);
input clk;
input [10:0] X, Y;
output wire out_R, out_G, out_B;
input ram_in;
output wire [11:0] ram_addr;
wire [5:0] ramX, ramY;
/* trying to map a 1280x1024 screen to 64x64 RAM.
* our original formula... | 7.742174 |
module Draw_circle (
x_in,
y_in,
color,
CLOCK_50,
x_out,
y_out,
color_out
);
input CLOCK_50;
input [7:0] x_in;
input [6:0] y_in;
input [2:0] color;
output reg [7:0] x_out;
output reg [6:0] y_out;
output reg [2:0] color_out;
reg [2:0] count_x;
reg [2:0] count_y;
reg [1:0]... | 7.68104 |
module usermode (
clk25m,
clk100hz,
hpos,
vpos,
button,
usercolors
);
//inputs
input clk25m;
input clk100hz;
input [9:0] hpos;
input [9:0] vpos;
input [4:0] button;
//outputs
output [11:0] usercolors;
reg [11:0] usercolors;
reg [ 9:0] hmov;
reg [ 9:0] vmov;
reg [ 9:0] h... | 6.87871 |
module drawGameOverScreen (
clk,
resetn,
enableDraw,
x_out,
y_out,
c_out
);
input clk, resetn, enableDraw;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] c_out;
localparam width = 8'd160, height = 7'd120, x_in = 8'b0, y_in = 7'b0;
reg [7:0] counterX, xOut; //placeholder for... | 8.333042 |
module toplevel (
SW,
CLOCK_50,
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B,
LEDG,
PS2_CLK,
PS2_DAT,
HEX0,
HEX1,
HEX2,
HEX3... | 8.460384 |
module enablercount (
CLOCK_50,
reset,
enable,
divider,
enabledelay1,
enabledelay2,
enabledelay3,
enabledelay4,
enabledelay5
);
input CLOCK_50, reset;
input [2:0] divider;
output reg enable;
output reg enabledelay1;
output reg enabledelay2;
output reg enabledelay3;
o... | 6.922756 |
module modulox (
xpositionW,
is0,
enable,
CLOCK_50
);
input [7:0] xpositionW;
input CLOCK_50;
input enable;
output reg is0;
always @(CLOCK_50)
if (enable == 1'b1) begin
if (xpositionW % 10 == 0) is0 = 1;
else is0 = 0;
end
endmodule
| 6.994745 |
module PS2_Demo (
// Inputs
CLOCK_50,
KEY,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
/*****************************************************************************
* Paramet... | 8.682108 |
module DrawingStateHandler (
clk,
startGameFlag,
drawingState,
accessControlState,
gameOverFlag,
gameControllerState
);
//states for DrawingStateHandler controller
parameter ENTERING_CREDENTIALS=4'd1,
ENTERING_TIME=4'd2,
PLAYING_GAME=4'd3,
PLAYER_DEAD = 4'd4;
//states taken fro... | 7.926928 |
module DrawPlayerWin (
iCLOCK_50,
iresetn,
iPlayer1Win,
iPlayer2Win,
ocolor_out,
ox,
oy,
owriteEn
);
input iCLOCK_50, iresetn;
input iPlayer1Win, iPlayer2Win;
output [2:0] ocolor_out;
output reg [8:0] ox;
output reg [7:0] oy;
output reg owriteEn;
reg [7:0] ix_pos = 110;
... | 8.456128 |
module DrawBlack (
input clk,
input rst,
input showTitle,
input showBlack,
input showGameOver,
input flash,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] colourOut
);
wire [2:0] red, black, title_ram_out, gameover_ram_out;
reg [14:0] address;
assign red = 3'b10... | 6.666249 |
module drawSprite (
Xin,
Yin,
Sprite,
AnimStep,
Width,
Height,
DataIn,
Enable,
Resetn,
Clock,
MemSel,
Address,
Xout,
Yout,
Color,
Done,
VGA_Draw
);
input [7:0] Xin;
input [6:0] Yin;
input [4:0] Width, Height;
input Enable, Clock, Resetn;
inpu... | 9.031336 |
module drawStartGameScreen (
clk,
resetn,
enableDraw,
x_out,
y_out,
c_out
);
input clk, resetn, enableDraw;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] c_out;
localparam width = 8'd160, height = 7'd120, x_in = 8'b0, y_in = 7'b0;
reg [7:0] counterX, xOut; //placeholder fo... | 8.557412 |
module drawTile (
draw,
drawDone,
plot,
clock,
resetn,
draw_x,
draw_y,
y_D,
y_Q
);
input draw, clock, resetn;
output [7:0] draw_x;
output [6:0] draw_y;
output drawDone, plot;
output [1:0] y_D, y_Q;
// X drawing counter - 0-7
reg draw_cnt_en_x, draw_cnt_reset_x;
wire ... | 8.676301 |
module DrawTotalRounds
(
iCLOCK_50,
iresetn,
idrawEn,
NumSelect,
ocolor_out,
ox,
oy,
owriteEn,
oDoneSignal,
);
input iCLOCK_50, iresetn, idrawEn;
input [2:0]NumSelect;
output [2:0]ocolor_out;
output reg [8:0]ox;
output reg [7:0]oy;
output reg owriteEn;
output reg oDoneSignal;
reg [7:0]ix_pos = ... | 8.198924 |
module draw_back (
input [10:0] vcounter,
input [11:0] hcounter,
input dead,
init,
win,
output reg [3:0] out
);
`include "def.v"
localparam WIDTH = 72;
wire draw;
wire [4:0] x, y;
reg [1:0] kind;
assign x = (hcounter - LEFT) / 16;
assign y = (vcounter - TOP) / 16;
word stg (
... | 7.293031 |
module draw_ball (
input [10:0] vcounter,
input [11:0] hcounter,
input visible,
input [10:0] ball_x,
ball_y,
output reg VGA_R,
output reg VGA_G,
output reg VGA_B
);
always @(*) begin : circle
integer dx, dy;
dy = vcounter;
dx = hcounter;
dx = dx - ball_x;
dy = dy -... | 7.256718 |
module draw_black (
enable,
clock,
resetn,
vga_x,
vga_y,
colour,
done
);
input clock;
input enable;
input resetn;
output [7:0] vga_x;
output [6:0] vga_y;
output reg done = 0;
output [2:0] colour;
wire [14:0] address;
reg [ 7:0] count_x = 0;
reg [ 6:0] count_y = 0;
... | 6.917493 |
module draw_block (
input clock,
input [10:0] vcounter,
input [11:0] hcounter,
input [2:0] block,
output [4:0] sel_row,
sel_col,
output reg [3:0] out
);
parameter LEFT = 160;
parameter TOP = 0;
parameter MAXX = 320;
parameter MAXY = 480;
wire range;
assign range = hcounter >= L... | 7.332975 |
module draw_border (
input clk,
resetn,
go,
go2,
output reg writeEn,
output reg done,
output reg [7:0] x_out,
output reg [6:0] y_out,
output reg [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] current_state, next_state;
always @(posedge clk) begin
if (!resetn) c... | 7.993763 |
module draw_boxes (
input advanced_sw,
input [11:0] VGA_HORZ_COORD,
input [11:0] VGA_VERT_COORD,
output reg [3:0] VGA_Red_Grid,
output reg [3:0] VGA_Green_Grid,
output reg [3:0] VGA_Blue_Grid
);
//scaled wave properties
parameter scale = 6;
parameter xadjust = 30;
parameter yadjust = 75... | 7.286268 |
module draw_distance_char (
output reg [11:0] rgb_out,
output wire [ 3:0] char_line,
output wire [ 4:0] char_xy,
input wire [7:0] char_pixels,
input wire [10:0] hcount_in,
input wire [10:0] vcount_in,
input wire [11:0] rgb_in,
input wire pclk,
input wire rst
);
wire [10:0] hcou... | 7.097395 |
module draw_dstbuf (
input CLK,
input RST_X,
input INIT,
input [63:0] VIF_RDATA,
input VIF_DRWRDATAVLD,
input DSTSEL,
input BUF_RD,
output [63:0] DATA,
output DATAVALID,
output EMPTY_PIXEL,
output EMPTY_VRA... | 6.892689 |
module draws a rectangle starting at (x_pos, y_pos) and goes right and down to reach HEIGHT and WIDTH set by the prameters.
// Its coulour may be changed by modifying RGB value which is by default set to yellow (R=255, G=255, B=0).
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comment... | 8.345197 |
module draw_egg (
x,
y,
startx,
starty,
color,
clock,
writeEn,
reset,
done_print
);
input clock;
input writeEn;
input reset;
input [7:0] startx;
input [6:0] starty;
output [7:0] x;
output [6:0] y;
output done_print;
output [2:0] color;
assign x = startx + 8'b0;
... | 6.990894 |
module draw_enemy (
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0] xpos,
input wire [10:0] ypos,
input wire on,
input wire [10:0] vcount_in, // input vertical count
input wire vsync_in, // input vertical sync
input wire vbl... | 7.805426 |
module Draw_Ex(
input clk,
input [12:0] pixel_index,
input reset,
input left,
input right,
input EX,
output reg [15:0] pixel_ex,
output reg GAME1
);
reg [15:0] ex1 [0:6143];
reg [15:0] ex2 [0:6143];
reg [15:0] ex3 [0:6143];
reg [15:0] ex4 [0:6143];
reg [15:0... | 6.896695 |
module draw_gameover (
enable,
clock,
resetn,
vga_x,
vga_y,
colour,
done
);
input clock;
input enable;
input resetn;
output [7:0] vga_x;
output [6:0] vga_y;
output reg done = 0;
output [2:0] colour;
wire [14:0] address;
reg [ 7:0] count_x = 0;
reg [ 6:0] count_y = 0;... | 6.711103 |
module draw_gift (
input [10:0] vcounter,
input [11:0] hcounter,
input [9:0] x,
y,
input [2:0] kind,
input active,
output reg [3:0] out
);
`include "def.v"
wire range;
assign range = hcounter >= LEFT && hcounter < LEFT+MAXX && vcounter >= TOP && vcounter < TOP+MAXY;
always @(*) begi... | 7.939251 |
module draw_gold (
clk,
resetn,
x_init,
y_init,
resetn_c_gold,
enable_c_gold,
load_x_gold,
load_y_gold,
enable_x_adder_gold,
enable_y_adder_gold,
enable_gold_count,
resetn_gold_stone,
X_out_gold,
Y_out_gold,
Color_out_gold,
gold_count,
gold_pix... | 6.627311 |
module draw_stone (
clk,
resetn,
x_init,
y_init,
resetn_c_stone,
enable_c_stone,
load_x_stone,
load_y_stone,
enable_x_adder_stone,
enable_y_adder_stone,
enable_stone_count,
resetn_gold_stone,
X_out_stone,
Y_out_stone,
Color_out_stone,
stone_count,
... | 7.350478 |
module draw_background (
clk,
resetn,
enable_x_adder_background,
enable_y_adder_background,
enable_c_stone_background,
X_out_background,
Y_out_background,
Color_out_background,
background_cout,
resetn_gold_stone_diamond
);
input clk;
input resetn;
input enable_x_adder_... | 6.849836 |
module draw_gold_FSM (
clk,
resetn,
enable_draw_gold,
gold_pixel_cout,
enable_c_gold,
load_x_gold,
load_y_gold,
enable_x_adder_gold,
enable_y_adder_gold,
enable_gold_count,
resetn_c_gold,
writeEn_gold,
draw_gold_done
);
input clk;
input resetn;
input enable_d... | 7.180715 |
module draw_stone_FSM (
clk,
resetn,
enable_draw_stone,
stone_pixel_cout,
enable_c_stone,
load_x_stone,
load_y_stone,
enable_x_adder_stone,
enable_y_adder_stone,
enable_stone_count,
resetn_c_stone,
writeEn_stone,
draw_stone_done
);
input clk;
input resetn;
in... | 8.013054 |
module draw_background_FSM (
clk,
resetn,
enable_draw_background,
background_cout,
enable_x_adder_background,
enable_y_adder_background,
enable_c_stone_background,
writeEn_background,
draw_background_done
);
input clk;
input resetn;
input enable_draw_background;
input [1... | 6.849836 |
module draw_img #(
parameter RECT_WIDTH = 128,
RECT_LENGTH = 128,
ADDR_WIDTH = 14
) (
input wire [10:0] hcount_in,
input wire hsync_in,
input wire hblnk_in,
input wire [10:0] vcount_in,
input wire vsync_in,
input wire vblnk_in,
input wire pclk,
input wire rst,
input wire ... | 7.700663 |
module Draw_Kirby (
input CLK,
input [12:0] pixel_index,
input reset,
input right,
input [3:0] level,
input GAME2,
output reg [15:0] pixel_kirby,
output reg GAME3
);
// Implement delay for win animation. Sort out GAME1, GAME2, GAME3 (GAME3 doesn't work). Implement reset.
reg [31:0]... | 6.769108 |
module: draw_lines
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module draw_lines_tb;
// Inputs
reg i_clk;
reg i_reset;
reg [10:0] i_x0;
reg [10:0] i_x1;
reg [10:0] i_y0;
reg [10... | 7.391812 |
module draw_lines_top (
input clk,
input [7:0] sw,
input btns,
input btnu,
input btnl,
input btnd,
input btnr,
output [7:0] seg,
output [3:0] an,
output [7:0] Led,
output [2:0] vgaRed,
output [2:0] vgaGreen,
output [2:1] vgaBlue,
output Hsync,
output Vsync
);
... | 6.622397 |
module draw_live #(
parameter N = 1,
parameter XPOS = 20,
parameter YPOS = 50,
parameter WIDTH_RECT = 30,
parameter HEIGHT_RECT = 31
) (
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [3:0] dead_count,
input wire [10:0] vcount_in, // input ve... | 7.839983 |
module draw_logic (
clk,
rst,
pixel_x,
pixel_y,
pixel_r,
pixel_g,
pixel_b,
multiplier,
multiplicand,
product
);
input clk;
input rst;
input [9:0] pixel_x;
input [9:0] pixel_y;
output reg [7:0] pixel_r;
output reg [7:0] pixel_g;
output reg [7:0] pixel_b;
wire [11... | 6.845052 |
module draw_map0 (
input clk,
input [10:0] x,
input [10:0] y,
output reg [11:0] color
);
reg [11:0] color_out_x;
reg [11:0] color_out_y;
wire out;
assign out = (x[10] == 1'b1 || y[10] == 1'b1) ? 1'b1 : 1'b0;
// min unit : 16
// program wall in 16*16 block
always @(posedge clk) begin
... | 7.128908 |
module draw_map1 (
input clk,
input [10:0] x,
input [10:0] y,
output reg [11:0] color
);
wire [15:0] addr;
// convert addr
assign addr = {6'b0, y[10:1]} * 16'd240 + {6'b0, x[10:1]};
wire [11:0] rom_color;
map1_rom map1 (
.a (addr),
.spo(rom_color)
);
always @(*) begin
if ... | 7.208266 |
module draw_mask (
input [1:0] enable,
input [11:0] pri_color,
input [11:0] dim_color,
input [11:0] select_color,
input [11:0] result_color,
output reg [11:0] color
);
// composite color
always @(*) begin
case (enable)
// select
2'b1: begin
color = (select_color == `... | 7.130294 |
module is drawing missile of ship
`timescale 1 ns / 1 ps
module draw_missile(
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0] xpos,
input wire [10:0] ypos,
input wire on,
input wire ... | 7.566658 |
module draw_missile_en (
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0] xpos,
input wire [10:0] ypos,
input wire on,
input wire [10:0] vcount_in, // input vertical count
input wire vsync_in, // input vertical sync
input wire ... | 7.591005 |
module Draw_Nyan (
input CLK,
input [12:0] pixel_index,
input reset,
input right,
input [3:0] level,
input GAME1,
output reg [15:0] pixel_nyan,
output reg GAME2
);
reg [31:0] FRAME = 32'd900000;
reg [31:0] start_count = 32'd0;
reg [31:0] dead_count = 32'd0;
reg dead = 0;
reg [... | 6.870874 |
module dynamic_obst_ctl (
input wire clk, //100 Hz
input wire rst,
output reg [11:0] xpos,
output reg [11:0] ypos
);
localparam VER_PIXELS = 600;
localparam RECT_HEIGHT = 50;
localparam XPOS_INIT = 600;
localparam YPOS_INIT = 1;
localparam DOWN = 2'b01, UP = 2'b10, CHANG... | 8.272677 |
module Draw_OLED (
input CLK,
input [3:0] level,
input [12:0] pixel_index,
input borderSW,
input colorSW,
input onSW,
input sw5,
input reset,
input left,
input right,
output [15:0] pixel_data
);
wire END;
// reg [3:0] state;
// reg [3:0] next_state;
// parame... | 6.797729 |
module draw_paddle (
input [10:0] vcounter,
input [11:0] hcounter,
input [9:0] x,
y,
input [5:0] radius,
output reg [3:0] out
);
localparam PD_H = 8;
localparam LEFT = 160;
localparam TOP = 0;
localparam MAXX = 320;
localparam MAXY = 480;
wire range;
assign range = hcounter >= x-... | 8.695333 |
module draw_player(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input [10:0] position_x,
input [10:0] position_y,
output [11:0] player_color,
output in_player,
output near_player
);
// assert(x,y>0 posx,y>0)
assign dist_out = dist;
reg [31:0] dist = 32'hfffffff... | 8.136412 |
module draw_plyr (
x,
y,
startx,
starty,
color,
clock,
writeEn,
reset,
done_print
);
input clock;
input writeEn;
input reset;
input [7:0] startx;
input [6:0] starty;
output [7:0] x;
output [6:0] y;
output reg done_print;
output [2:0] color;
wire [8:0] address;
... | 6.973081 |
module is drawing react (ship)
`timescale 1 ns / 1 ps
// Declare the module and its ports. This is
// using Verilog-2001 syntax.
module draw_react(
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0... | 6.973879 |
module and its ports. This is
// using Verilog-2001 syntax.
module draw_rect_char (
output reg [11:0] rgb_out,
output reg [10:0] hcount_out,
output reg [10:0] vcount_out,
output wire [3:0] char_line,
output wire [4:0] char_xy,
input wire [7:0] char_pixels,
input wire [10:0] hcount_in,
input wire ... | 6.630177 |
module generate the backround for vga
// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here).
`timescale 1 ns / 1 ps
// Declare the module and its ports. This is
// using Verilog-2001 syntax.
module draw_rect_ctl_tb (
input... | 7.972229 |
module draw_rect_ctl_test;
reg pclk;
reg rst;
wire mouse_left;
wire [11:0] mouse_xpos;
wire [11:0] mouse_ypos;
wire [11:0] xpos_out_ctl;
wire [11:0] ypos_out_ctl;
draw_rect_ctl_tb my_draw_rect_ctl_tb (
.pclk(pclk),
.rst (rst),
.mouse_left(mouse_left),
.mouse_xpos(mouse_xpos)... | 7.680529 |
module draw_rect_game_over (
input wire pclk, // Peripheral Clock
input wire rst, // Synchrous reset
input wire [10:0] vcount_in, // input vertical count
input wire vsync_in, // input vertical sync
input wire vblnk_in, // input vertical blink
in... | 7.576702 |
module draw_regctrl_buf (
input CLK,
input RST_X,
input INIT,
input [31:0] INDATA,
input BUF_WR,
input BUF_RD,
output [31:0] OUTDATA,
output DATAVALID,
output FULL_REG,
output EMPTY_REG,
output [10:0] WCOUNT,
o... | 6.773793 |
module draw_score(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input mode,
input [10:0] score_x,
input [10:0] score_y,
input [11:0] score_color,
output [11:0] color
);
// assert(x,y>0 posx,y>0)
assign dist_out = dist;
reg [31:0] dist = 32'hffffffff;
alway... | 6.987531 |
module draw_shape #(
parameter WIDTH = 16, // default width: 16 pixels
HEIGHT = 128
) ( // default height: 128 pixels
x,
hcount,
y,
vcount,
clk,
pixel
);
// ====================================================================================
// Port Declarations
// =... | 8.307206 |
module draw_symbols (
input reset,
input [10:0] vcounter,
input [11:0] hcounter,
input visible,
input [8:0] occupied,
input [8:0] symbol,
output reg VGA_R,
output reg VGA_G,
output reg VGA_B
);
//upper left position of tic-tac-toe
wire [10:0] down;
wire [11:0] left;
assign d... | 7.661721 |
module draw_triangle #(
// // Video resolution parameters for 800x600 @60Hz -- pixel_freq = 40 MHz
// parameter H_ACTIVE_VIDEO = 800,
// parameter H_FRONT_PORCH = 40,
// parameter H_SYNC_WIDTH = 128,
// parameter H_BACK_PORCH = 88,
//
// parameter V_ACTIVE_VIDEO = 600,... | 9.458384 |
module draws a rectangle starting at (X_POS,Y_POS) and goes right and down to reach HEIGHT and WIDTH set by the prameters.
// Its coulour may be changed by modifying RGB value which is by default set to yellow (R=255, G=255, B=0).
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments... | 8.345197 |
module draw_wrbuf (
input CLK,
input RST_X,
input INIT,
input [63:0] PIXEL_DATA,
input WRSEL,
input BUF_WR,
input BUF_RD,
output [63:0] DRW_VRAMWDATA,
output DATAVALID,
output EMPTY_PIXEL,
output EMPTY_VRAM... | 6.91211 |
module interfaces with Buttons, ADC, DAC and SDRAM
The buttons allow the recorded to switch states
- Standby
- Record
- Play
In `Record` mode the controller reads data from the ADC and writes it
to SDRAM
In `Play` mode the controller reads data from the SDRAM and writes to the ... | 7.895179 |
module dreg #(
parameter WIDTH = 32
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk, posedge rst) begin
if (rst) q <= 0;
else q <= d;
end
endmodule
| 8.777901 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
)... | 7.403606 |
module Register4CE (
input [3:0] I,
output [3:0] O,
input CLK,
input CE
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(CE),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.... | 7.000284 |
module DRegister #(
parameter DATA_BITS = 32
) (
input wire clk, //系统时钟
input wire rst, //同步清零信号
input wire enable, //D寄存器使能信号
input wire [DATA_BITS - 1:0] data_in, //输入数据
output wire [DATA_BITS - 1:0] data_out //输出数据
);
reg [DATA_BITS - 1:0] REG;
assign data_out = REG;
always @(posed... | 7.90568 |
module drink_machine_top (
dime_out,
dispense,
empty,
exact_change,
nickel_out,
two_dime_out,
cans,
clk,
dimes,
dime_in,
load,
nickels,
nickel_in,
quarter_in,
reset
);
input clk, dime_in, load, nickel_in, quarter_in, reset;
output dime_out, dispense, empt... | 6.79605 |
module drink_machine_top (
dime_out,
dispense,
empty,
exact_change,
nickel_out,
two_dime_out,
cans,
clk,
dimes,
dime_in,
load,
nickels,
nickel_in,
quarter_in,
reset
);
input clk, dime_in, load, nickel_in, quarter_in, reset;
output dime_out, dispense, empt... | 6.79605 |
module Driver (
clk,
rstn,
start_i,
// addr_o,
data_i,
db_o,
dori_o,
cs_o,
en_o,
rw_o,
rst_o,
state
);
input clk;
input rstn;
input start_i;
reg [1:0] start_history;
// output [10:0]addr_o;//one LCD_Graphic
input [7:0] data_i;
// wire [7:0]data_i;//debug
... | 6.846844 |
module Driver (
clk,
rstn,
start_i,
addr_o,
data_i,
db_o,
dori_o,
cs_o,
en_o,
rw_o,
rst_o,
state
);
input clk;
input rstn;
input start_i;
reg [1:0] start_history;
output [9:0] addr_o; //one LCD_Graphic
input [7:0] data_i;
// wire [7:0]data_i;//debug
//... | 6.846844 |
module driver7seg (
input [3:0] b,
output reg [6:0] d
);
always @* begin
case (b)
4'b0000: d = 7'b1000000; // 0
4'b0001: d = 7'b1111001; // 1
4'b0010: d = 7'b0100100; // 2
4'b0011: d = 7'b0110000; // 3
4'b0100: d = 7'b0011001; // 4
4'b0101: d = 7'b0010010; // 5
... | 6.588562 |
module driver_controller (
input wire rst,
input wire direction, //sw1: 0 for counter clockwise, 1 for clockwise
input wire step_size, //sw3: 0 for half a step, 1 for a full step
input wire step_pulse, // a pulse from the clock
input wire zero_state,
output reg [3:0] phase_out
);
reg [3:... | 7.056215 |
module driver_dipswitch (
output [31:0] RD,
input [4:2] Addr,
input reset,
input [7:0] dip_switch0,
input [7:0] dip_switch1,
input [7:0] dip_switch2,
input [7:0] dip_switch3,
input [7:0] dip_switch4,
input [7:0] dip_switch5,
input [7:0] dip_switch6,
input [7:0] dip_switch7
);... | 6.846567 |
module lcd_driver (
dataa,
datab,
result,
clk,
clk_en,
start,
reset,
done,
rs,
rw,
en,
db
);
input [31:0] dataa;
input [31:0] datab;
input clk;
input clk_en;
input start;
input reset;
output reg [31:0] result;
output reg done;
output reg rs;
output ... | 7.167809 |
module driver_lights (
input [31:0] DIn,
input WE,
output [31:0] RD,
input clk,
input reset,
output reg [31:0] led_light
);
assign RD = (reset) ? 0 : led_light;
always @(posedge clk) begin
if (reset) led_light <= 0;
else if (WE) led_light <= DIn;
end
endmodule
| 6.518081 |
module driver_seg (
input [15:0] data,
input clk,
input clr,
output reg [6:0] a_to_g,
output reg [3:0] an,
output wire dp
);
wire [ 1:0] s;
reg [ 3:0] digit;
wire [ 3:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:18];
assign aen = 4'b1111; // all turned o... | 7.559671 |
module driver_top (
A1,
A2,
A3,
A4,
EN12,
clk,
Trig_l,
Trig_r,
Trig_f1,
Trig_f2,
Echo_l,
Echo_r,
Echo_f1,
Echo_f2,
serial
);
output A1, A2, A3, A4, EN12;
input clk;
input Echo_l, Echo_r, Echo_f1, Echo_f2;
output Trig_l, Trig_r, Trig_f1, Trig_f2;
w... | 7.138199 |
module Driver_UART (
input clk_100MHz,
input Rst,
input En_Rx,
input En_Tx,
input [30:0] Baud_Rate,
input Rx,
input [7:0] Tx_Data,
output Tx,
output [7:0] Rx_Data,
output Rx_ACK,
output clk_UART,
output Tx_ACK
);
//UART clock
//wire clk_UART;
wire [30:0] clk_mode;
... | 6.851673 |
module
module UART_Rx(
input clk_UART, //Clock signal
input nRst, //Reset signal, low reset
input En, //Enable signal, active high
input Rx, //Rx
output Ack, //... | 7.032328 |
module
module UART_Tx(
input clk_100MHz, //Detect clock for trigger detection
input clk_UART, //Clock signal
input Rst, //Reset signal, low reset
input En, //Enable signal, valid on rising edge
i... | 7.338271 |
module driver_vga_640x480 (
clk_vga,
hs,
vs,
hc_visible,
vc_visible
);
input clk_vga; // 25 MHz !
output hs, vs;
output [9:0] hc_visible;
output [9:0] vc_visible;
//640x480 original
parameter hpixels = 10'd800; // --Value of pixels in a horizontal line
parameter vlines = 10'd500; /... | 8.067383 |
module driver_vga_1024x768(clk_vga, hs, vs,hc_visible,vc_visible);
// input clk_vga; // 82 MHz !
// output hs, vs;
//FILL HERE
//endmodule
| 6.727966 |
module Drive_ADC (
input in_rst
, input in_clk
, input [9:0] in_ADC_data
, output reg out_OE_n
, output reg [9:0] out_ADC_data
);
always @(negedge in_rst or posedge in_clk) begin
if (in_rst == 0) begin
out_ADC_data <= 10'b0;
out_OE_n <= 1;
end else begin
out_OE_n <= 0... | 6.566037 |
module Drive_Freq (
input Freq_clk
, input in_clk_50M
, input in_clr //复位
, input Sig_in //被测信号
, output reg [31:0] data_fx
);
parameter T_1s = 28'd49_999_999;
//————————————————————————
// 预置闸门 产生一个1S的方波
reg [27:0] TCount; //预置阀门记数值
always @(posedge in_clk_50M or negedge ... | 8.120935 |
module drive_tube (
clk,
enable,
number,
sign,
duan_reg,
wei_reg
);
input clk;
output enable;
output reg [7:0] duan_reg;
output [2:0] wei_reg;
input [19:0] number;
input [2:0] sign;
wire [23:0] num_4_digit;
reg [ 3:0] duan_statu = 4'd0;
reg sign_or_number_key;
reg ... | 6.815303 |
module Drive_Usart_Bsp (
input in_clr
, input in_clk_us
, input in_rx
, input in_send_update
, input [7:0] in_send_byte
, output out_tx
, output out_receive_update
, output [7:0] out_receive_byte
);
//parameter define
parameter CLK_FREQ = 1000000; //定义系统时钟频率
parameter UART_BPS = ... | 7.631598 |
module Drive_Usart_Top (
input in_clr,
input in_clk_us,
input in_rx,
input in_key,
output out_tx,
output [4:2] out_led,
input [31:0] out_set_freq //设置频率
);
wire w_send_update;
wire [7:0] w_send_byte;
Drive_Usart_Handle Drive_Usart_Handle (
.in_clr(in_clr),
.in_clk_us(... | 8.381854 |
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