code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dri_vga (
input wire clk,
input wire rst,
input wire en_i,
output wire h_sync_o,
output wire v_sync_o,
output wire disp_o,
output wire [`H_DISP_LEN-1:0] req_x_addr_o,
output wire [`V_DISP_LEN-1:0] req_y_addr_o
);
reg [ `H_... | 7.285964 |
module DRMUX (
input [2:0] IR11to9,
input DRMUX,
output reg [2:0] DR
);
initial DR = 0;
always @(*) begin
case (DRMUX)
2'b00: DR = IR11to9;
2'b01: DR = 3'b111;
2'b10: DR = 3'b110;
default: DR = 3'b000;
endcase
end
endmodule
| 6.643041 |
module drom (
addr,
sel_fpga_byte,
sel_ver_bytes,
sel_penc_byte,
sel_cntr_bytes,
sel_dac_byte
);
input [4:0] addr;
output sel_fpga_byte;
output [4:0] sel_ver_bytes;
output sel_penc_byte;
output [15:0] sel_cntr_bytes;
output sel_dac_byte;
reg [31:0] sel_out;
always @(addr)
... | 6.958818 |
module drom_unit #(
parameter INIT_FILE_NAME = "none", //Instruction memory file name
ADDR_DEPTH = 256 * 3,
ADDR_WIDTH = 10,
CONFIG_LOAD = 0
) (
input clk_i, //Input Clock
input [ADDR_WIDTH+1:0] raddr_i, //Read Address
... | 8.631965 |
module Mult_32b (
dataa,
datab,
result
); //now signed version!
input [31:0] dataa;
input [31:0] datab;
output [63:0] result;
// assign result = dataa * datab;
wire [31:0] a;
wire [31:0] b;
assign a = dataa;
assign b = datab;
reg [63:0] c;
assign result = c;
reg is_neg_a;
reg ... | 6.700776 |
module sub_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa - datab;
assign overflow = computation[32];
assign result = co... | 7.033184 |
module add_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa + datab;
assign overflow = computation[32];
assign result = co... | 7.951311 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module lab2_proc_DropUnit #(
parameter p_msg_nbits = 1
) (
input logic clk,
input logic reset,
// the drop signal will drop the next arriving packet
input logic drop,
input logic [p_msg_nbits-1:0] istream_msg,
input logic istream_val,
output logic ... | 8.81301 |
module vc_DropUnit #(
parameter p_msg_nbits = 1
) (
input logic clk,
input logic reset,
// the drop signal will drop the next arriving packet
input logic drop,
input logic [p_msg_nbits-1:0] in_msg,
input logic in_val,
output logic in_rdy,
out... | 9.209376 |
module drop_arbiter #(
parameter MAX_DEPTH_BITS_BLACKLIST = 14
) (
//-- interface to modifidied header parser
input [ 31:0] src_ip,
input hash2_vld,
input [MAX_DEPTH_BITS_BLACKLIST-1:0] addr2_hash,
input is_pkt_... | 7.671959 |
module drp_other_registers #(
parameter DRP_ABITS = 8,
parameter DRP_REG0 = 8,
parameter DRP_REG1 = 9,
parameter DRP_REG2 = 10,
parameter DRP_REG3 = 11
) (
input drp_rst,
input drp_clk,
input drp_en, // @aclk stro... | 7.689812 |
module DRU (
fb_data,
up_reg32_odata,
lo_reg32_odata,
reg64_odata1,
reg64_odata2,
mem_data,
up_reg32_enable,
lo_reg32_enable,
reg64_enable1,
reg64_enable2,
sys_clk,
clear_data_regs
);
input sys_clk;
input clear_data_regs;
input up_reg32_enable, lo_reg32_enable;
i... | 6.555692 |
module LINEBUF_DOUBLE (
CLK,
EN,
SIDE1,
CLK2,
WEN,
ADRSW,
IN,
ADRSR,
OUT
);
input CLK;
input EN;
input SIDE1;
input CLK2;
input WEN;
input [8:0] ADRSW;
input [3:0] IN;
input [8:0] ADRSR;
output [3:0] OUT;
wire [3:0] OUT0, OUT1;
wire SIDE0 = ~SIDE1;
wire OPA... | 7.205266 |
module P_Encoder (
in_a,
out_a
);
input [15:0] in_a;
output reg [3:0] out_a;
always @(*) begin
case (in_a)
16'h0001: out_a = 4'h0;
16'h0002: out_a = 4'h1;
16'h0004: out_a = 4'h2;
16'h0008: out_a = 4'h3;
16'h0010: out_a = 4'h4;
16'h0020: out_a = 4'h5;
16'h0040... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [4:0] count;
input [7:0] in_a;
output [31:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [3:0] select;
input [15:0] in_a;
output reg [1:0] out;
always @(*) begin
case (select)
4'h4: begin
out = {in_a[3], in_a[2]};
end
4'h5: begin
out = {in_a[4], in_a[3]};
end
4'h6: begin
out = {in_a[5... | 7.043002 |
module P_Encoder (
in_a,
out_a
);
input [15:0] in_a;
output reg [3:0] out_a;
always @(*) begin
case (in_a)
16'h0001: out_a = 4'h0;
16'h0002: out_a = 4'h1;
16'h0004: out_a = 4'h2;
16'h0008: out_a = 4'h3;
16'h0010: out_a = 4'h4;
16'h0020: out_a = 4'h5;
16'h0040... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [4:0] count;
input [9:0] in_a;
output [31:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [3:0] select;
input [15:0] in_a;
output reg [2:0] out;
always @(*) begin
case (select)
4'h5: begin
out = {in_a[4], in_a[3], in_a[2]};
end
4'h6: begin
out = {in_a[5], in_a[4], in_a[3]};
end
4'h7: begin
... | 7.043002 |
module P_Encoder (
in_a,
out_a
);
input [15:0] in_a;
output reg [3:0] out_a;
always @(*) begin
case (in_a)
16'h0001: out_a = 4'h0;
16'h0002: out_a = 4'h1;
16'h0004: out_a = 4'h2;
16'h0008: out_a = 4'h3;
16'h0010: out_a = 4'h4;
16'h0020: out_a = 4'h5;
16'h0040... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [4:0] count;
input [11:0] in_a;
output [31:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [3:0] select;
input [15:0] in_a;
output reg [3:0] out;
always @(*) begin
case (select)
4'h6: begin
out = {in_a[5], in_a[4], in_a[3], in_a[2]};
end
4'h7: begin
out = {in_a[6], in_a[5], in_a[4], in_a[3]};
end
... | 7.043002 |
module P_Encoder (
in_a,
out_a
);
input [15:0] in_a;
output reg [3:0] out_a;
always @(*) begin
case (in_a)
16'h0001: out_a = 4'h0;
16'h0002: out_a = 4'h1;
16'h0004: out_a = 4'h2;
16'h0008: out_a = 4'h3;
16'h0010: out_a = 4'h4;
16'h0020: out_a = 4'h5;
16'h0040... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [4:0] count;
input [11:0] in_a;
output [31:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [3:0] select;
input [15:0] in_a;
output reg [3:0] out;
always @(*) begin
case (select)
4'h6: begin
out = {in_a[5], in_a[4], in_a[3], in_a[2]};
end
4'h7: begin
out = {in_a[6], in_a[5], in_a[4], in_a[3]};
end
... | 7.043002 |
module P_Encoder (
in_a,
out_a
);
input [31:0] in_a;
output reg [4:0] out_a;
always @(*) begin
case (in_a)
32'h00000001: out_a = 5'h00;
32'h00000002: out_a = 5'h01;
32'h00000004: out_a = 5'h02;
32'h00000008: out_a = 5'h03;
32'h00000010: out_a = 5'h04;
32'h00000020:... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [5:0] count;
input [11:0] in_a;
output [63:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [4:0] select;
input [31:0] in_a;
output reg [3:0] out;
always @(*) begin
case (select)
5'h06: begin
out = {in_a[5], in_a[4], in_a[3], in_a[2]};
end
5'h07: begin
out = {in_a[6], in_a[5], in_a[4], in_a[3]};
end
... | 7.043002 |
module P_Encoder (
in_a,
out_a
);
input [15:0] in_a;
output reg [3:0] out_a;
always @(*) begin
case (in_a)
16'h0001: out_a = 4'h0;
16'h0002: out_a = 4'h1;
16'h0004: out_a = 4'h2;
16'h0008: out_a = 4'h3;
16'h0010: out_a = 4'h4;
16'h0020: out_a = 4'h5;
16'h0040... | 6.736855 |
module Barrel_Shifter (
in_a,
count,
out_a
);
input [4:0] count;
input [13:0] in_a;
output [31:0] out_a;
assign out_a = (in_a << count);
endmodule
| 7.114978 |
module Mux_16_3 (
in_a,
select,
out
);
input [3:0] select;
input [15:0] in_a;
output reg [4:0] out;
always @(*) begin
case (select)
4'h7: begin
out = {in_a[6], in_a[5], in_a[4], in_a[3], in_a[2]};
end
4'h8: begin
out = {in_a[7], in_a[6], in_a[5], in_a[4], in_a[... | 7.043002 |
module dsmk_mn (
a,
b,
r
);
parameter k_in = 6;
parameter n_in = 16;
parameter m_in = 16;
input [n_in-1:0] a;
input [m_in-1:0] b;
output [(n_in+m_in)-1:0] r;
wire [$clog2(n_in)-1:0] k1;
wire [$clog2(m_in)-1:0] k2;
wire [k_in-3:0] m, n;
wire [n_in-1:0] l1;
wire [m_in-1:0] l2;
wire ... | 7.348945 |
module LOD_k (
in_a,
out_a
);
input [n_in-1:0] in_a;
output reg [n_in-1:0] out_a;
parameter k_in = 6;
parameter n_in = 16;
integer k, j;
reg [n_in-1:0] w;
always @(*) begin
out_a[n_in-1] = in_a[n_in-1];
w[n_in-1] = in_a[n_in-1] ? 0 : 1;
for (k = n_in - 2; k >= 0; k = k - 1) begin
... | 6.611599 |
module P_Encoder_k (
in_a,
out_a
);
input [n_in-1:0] in_a;
output reg [$clog2(n_in)-1:0] out_a;
parameter k_in = 6;
parameter n_in = 16;
integer i;
always @* begin
out_a = 0;
for (i = n_in - 1; i >= 0; i = i - 1) if (in_a[i]) out_a = i[$clog2(n_in)-1:0];
end
endmodule
| 6.90615 |
module Barrel_Shifter_k_mn (
in_a,
count,
out_a
);
input [$clog2(m_in):0] count;
input [(k_in*2)-1:0] in_a;
output [(n_in+m_in)-1:0] out_a;
parameter k_in = 6;
parameter n_in = 16;
parameter m_in = 16;
wire [(n_in + m_in)-1:0] tmp;
assign tmp = {{((n_in + m_in) - (k_in * 2)) {1'b0}}, in_... | 7.114978 |
module Mux_16_3_k (
in_a,
select,
out
);
input [$clog2(n_in)-1:0] select;
input [n_in-1:0] in_a;
output reg [k_in-3:0] out;
parameter k_in = 6;
parameter n_in = 16;
integer i;
always @(*) begin
out = 0;
for (i = k_in; i < (n_in); i = i + 1) begin : mux_gen_block
if (select == i... | 7.469208 |
module drv_bus_req (
input clk_sys,
input ready,
input r,
input w,
input in,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3,
input zw,
output reg zg,
input ans_any,
output dw,
output dr,
output din,
output dpn,
output [0:3] dnb,
output [0:15] dad,
... | 6.574457 |
module drv_bus_resp (
input clk_sys,
input ready,
input ok,
input en,
input pe,
input [0:15] a3,
input req,
output reg dok,
output reg den,
output reg dpe,
output reg [0:15] ddt
);
// response trigger: any response for an active request
wire resp = req & ready & (ok | en... | 7.459948 |
module drv_cp_in (
input ready,
input cpd,
input cpr,
input cpf,
input [0:7] a1,
input [0:15] a3,
output [0:3] rotary_out,
output rotary_trig,
output [0:15] keys,
output keys_trig,
output [0:3] fn,
output fn_v,
output fn_trig
);
assign keys = a3;
assign rotary_ou... | 7.280538 |
module dr (
clk,
dmout,
drout,
islb
);
input clk;
input islb;
input [31:0] dmout;
output reg [31:0] drout;
always @(posedge clk) begin
if (islb == 1) begin
drout <= {{24{dmout[7]}}, dmout[7:0]};
end else begin
drout <= dmout;
end
end
endmodule
| 7.260647 |
module DR_ext (
input [ 1:0] addr_B,
input [31:0] Din,
input [ 2:0] op,
output [31:0] Dout
);
assign Dout=(op==`LB)?(addr_B==2'b00)?{{24{Din[7]}},{Din[7:0]}}:
(addr_B==2'b01)?{{24{Din[15]}},{Din[15:8]}}:
(addr_B==2'b10)?{{24{Din[23]}},{Din[23:16]}}:
(addr_B==2'b11)?{{24{Din... | 6.631659 |
module DR_LUT_tb ();
reg clk;
reg rst_n;
reg [2:0] baud_set;
wire [15:0] bps_DR;
initial begin
clk = 1;
rst_n = 1'b1;
baud_set = 3'd4;
#(`clk_period * 10);
baud_set = 3'd2;
#(`clk_period * 10);
$stop;
end
always #(`clk_period / 2) clk = ~clk;
DR_LUT tb1 (
.clk(clk)... | 6.514468 |
module DR_module (
clk,
dm_in,
dr_out
);
input clk;
input [31:0] dm_in;
output [31:0] dr_out;
reg [31:0] dr_out;
always @(posedge clk) dr_out <= dm_in;
endmodule
| 7.023059 |
module DR_reg (
clk,
rst,
data_on_dr,
bus_2_dr,
dr_2_bus
);
input clk;
input rst;
input data_on_dr;
input [7:0] bus_2_dr;
output [7:0] dr_2_bus;
reg [7:0] dr_2_bus;
always @(posedge clk) begin
if (rst) begin
dr_2_bus <= 8'b0;
end
if (data_on_dr) begin
dr_2_bu... | 6.921152 |
module DS128_sel (
clk,
rst_n,
din,
dout,
write_en
);
input clk;
input rst_n;
input [7:0] din;
output reg [7:0] dout;
output write_en;
reg xcnt;
reg ycnt;
reg [7:0] fx;
reg [7:0] mem [127:0];
reg [6:0] mem_addr;
assign write_en = ycnt & xcnt;
// specify re... | 7.208829 |
module ds1302_io (
input clk,
input rst,
output ds1302_ce,
output ds1302_sclk,
inout ds1302_io,
input cmd_read,
input cmd_write,
output cmd_read_ack,
output cmd_write_ack,
input [7... | 8.148136 |
module ds1302_test (
input rst,
input clk,
output ds1302_ce,
output ds1302_sclk,
inout ds1302_io,
output [7:0] read_second,
output [7:0] read_minute,
output [7:0] read_hour,
output [7:0] read_date,
output [7:0] read_month,
output [7:0] read_we... | 7.420118 |
module handles the bit timing of the 1-Wire interface, and
// instantiates ds1822_state.v to handle the command/response layer.
// So this module is (I hope) completely part-independent.
// Pulse widths from DS2401 data sheet:
// Initialization Procedure "reset and presence pulses" Figure 5
// t_RSTL 480 us to i... | 7.494922 |
module is the command/response layer, and currently only handles
// reset, the Read ROM command, and the Skip ROM/Read Scratchpad command
// pair. It might be interesting to add other commands, like Search ROM
// and Match ROM.
//
// This model responds to both 0x0f and 0x33 variants of the "Read ROM"
// command, like... | 7.320188 |
module ds1822_tb ();
reg clk, rst;
integer cc;
integer errors = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("ds1822.vcd");
$dumpvars(5, ds1822_tb);
end
clk = 0;
rst = 1;
#160;
rst = 0;
for (cc = 0; cc < 70000; cc = cc + 1) begin
#250;
clk = 1;... | 6.782133 |
module ds18b20 (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
inout wire dq, //数据总线
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe
);
//***************************************************************... | 8.101107 |
module ds18b20_driver_tb ();
//激励信号定义
reg clk;
reg rst_n;
reg dq_in;
//输出信号定义
wire dq_out;
wire dq_out_en;
wire temp_sign;
wire [23:0] temp_out;
wire temp_out_vld;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
ds18b20_driver u_ds1... | 7.923561 |
module DS192_sel (
clk,
rst_n,
din,
dout,
write_en
);
input clk;
input rst_n;
input [7:0] din;
output reg [7:0] dout;
output write_en;
reg [1:0] xcnt;
reg [1:0] ycnt;
reg [7:0] fx;
reg [7:0] mem [127:0];
reg [6:0] mem_addr;
assign write_en = ycnt != 2'b01 && xcnt != 2'b0... | 7.464088 |
module ds2064 (
input wire [12:0] address, // address pins of the RAM
inout wire [ 7:0] data,
input wire n_ce1,
input wire ce2,
input wire n_we,
input wire n_oe
);
parameter FILE = "sram.txt";
initial $readmemh(FILE, sram);
reg [7:0] sram[0:2**13-1];
assign #200 data = (n_we && !n_o... | 7.247282 |
module UartRx_2480B (
input sys_clk, // sys clk
input uart_rxd, // UART recv port
output reg uart_done, // recv 1 frame over flag
output reg [7:0] uart_data // recv data
);
//parameter define
parameter CLK_FREQ = 49152000; // define sys clk freq
parameter UART_BPS = 9600;... | 7.310826 |
module DS64_sel (
clk,
rst_n,
din,
dout,
write_en
);
input clk;
input rst_n;
input [7:0] din;
output reg [7:0] dout;
output write_en;
reg [1:0] xcnt;
reg [1:0] ycnt;
reg [7:0] fx;
reg [7:0] mem [63:0];
reg [6:0] mem_addr;
assign write_en = (ycnt == 2'b11) & (xcnt == 2'b1... | 7.611305 |
module DS96_sel (
clk,
rst_n,
din,
dout,
write_en
);
input clk;
input rst_n;
input [7:0] din;
output reg [7:0] dout;
output write_en;
reg [2:0] xcnt;
reg [2:0] ycnt;
reg [7:0] fx;
reg [7:0] mem [95:0];
reg [6:0] mem_addr;
assign write_en = (ycnt == 3'b001 || ycnt == 3'b1... | 6.684068 |
module dsa_single #(
parameter dac_bw = 16
) (
input wire clk,
input wire rst_n,
input wire [15 : 0] din,
output wire dout
);
localparam bw_ext = 2;
localparam bw_tot = dac_bw + bw_ext;
reg dout_r;
reg dac_dout;
reg signed [bw_tot... | 7.311586 |
module dsa_two #(
parameter dac_bw = 16,
parameter osr = 6
) (
input wire clk,
input wire rst_n,
input wire [15:0] din,
output wire dout
);
localparam mid_val = 2 ** (dac_bw - 1) + 2 ** (osr + 2);
localparam bw_ext = 2;
localparam bw_tot = dac_bw + bw_ext;
reg ... | 6.788396 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
///////////////////////////////... | 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= #1 opa * opb;
always @(posedge clk) prod <= #1 prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module dsDAC #(
parameter N = 8 // DAC bit width
) (
output reg out, // This is the average output that feeds low pass filter
// for optimum performance, ensure that this ff is in IOB
input [N-1:0] in, // DAC input (excess 2**MSBI)
input clk,
input nco,
input reset
);
reg [N+1:0] Delta... | 6.915158 |
module is a first-order delta-sigma modulator that generates an analog output when
// averaged by an external RC filter.
//
// 20 LUT4s and 42 registers used. 311 MHz maximum clock rate.
//
module dsdac20x1(
input [19:0] din, // data input
input we, // write enable
input clk, // master clock
input rs... | 6.772384 |
module SingleCycle_MIPS (
clk,
rst_n,
IR_addr,
IR,
RF_writedata,
ReadDataMem,
CEN,
WEN,
A,
ReadData2,
OEN
);
//==== in/out declaration =================================
input clk, rst_n;
input [31:0] IR;
output [31:0] IR_addr;
output [31:0] RF_writedata;
input [3... | 7.100802 |
module ALU (
ctrl,
x,
y,
out,
zero
);
input [3:0] ctrl; // the contral signal which decide the operation of alu
input [31:0] x, y; // 32 bit input data from register file or instruction[15:0]
output [31:0] out; // 32 bit output
output zero; // check the overflow
reg [... | 7.821883 |
module ImmGen (
IR,
Imm
);
input [31:0] IR; // instruction from instruction memory
output [31:0] Imm;
reg [31:0] Imm;
always @(*) begin
case (IR[6:2])
5'b00000: Imm = {{21{IR[31]}}, IR[30:25], IR[24:21], IR[20]}; // lw I-type
5'b01000: Imm = {{21{IR[31]}}, IR[30:25], IR[11:8], IR[7]};... | 6.657692 |
module ALU_control (
Func7,
Func3,
OP,
ALUCtrl
);
input Func7;
input [2:0] Func3;
input [1:0] OP;
output [3:0] ALUCtrl;
assign ALUCtrl[0] = (OP[1] & Func3[2] & Func3[1] & (~Func3[0]));
assign ALUCtrl[1] = ~(OP[1] & (~OP[0]) & Func3[1]);
assign ALUCtrl[2] = (((~OP[1]) & (~Func3[1])) | (Fun... | 7.483671 |
module ROM128x32 (
addr,
data
);
input [6:0] addr;
output [31:0] data;
reg [31:0] data;
reg [31:0] mem[0:127];
integer i;
initial begin
// Initialize the instruction memory
$readmemh("instructions.txt", mem);
$display("Reading instruction memory......");
// for ( i=0; i<19; i=i+1 )... | 7.116055 |
module ROM128x32 (
addr,
data
);
input [6:0] addr;
output [31:0] data;
reg [31:0] data;
reg [31:0] mem[0:127];
integer i;
initial begin
// Initialize the instruction memory
$readmemh("instructions.txt", mem);
//$display("Reading instruction memory......");
//
//for ( i=0; i<19; ... | 7.116055 |
module top (
input clock,
input reset, //Active high synchronous reset
input [15:0] value,
input [3:0] dots,
output [7:0] segment,
output [7:0] digit
);
wire [1:0] dig_sel;
wire [3:0] selected_value;
wire [6:0] pattern;
count12 count (
.clock (clock),
.reset (reset),
... | 7.233807 |
module TB_top;
// Inputs to module being verified
reg clock, reset;
reg [15:0] value;
reg [ 3:0] dots;
// Outputs from module being verified
wire [7:0] segment, digit;
// Instantiate module
top uut (
.clock(clock),
.reset(reset),
.value(value),
.dots(dots),
.segment(segment... | 7.012826 |
module dsd_pcm (
input bclk,
input clk_100,
input data_in,
input ws,
input rst_n,
output uart_tx,
output modulator_out_L,
output modulator_out_R
);
// assign data_out_end_L_1=modulator_out_L;
wire en_64, en_32, en_16, en_8;
// wire rst_n;
// assign rst_n=!rst;
// assign cl... | 6.743338 |
module dsg #(
parameter MSBI = 7 // Most significant Bit of DAC input
) (
input wire clock,
input wire reset,
input wire [MSBI:0] d, // DAC input (excess 2**MSBI)
output reg q // This is the average output that feeds low pass filter
); // for optimum perfo... | 6.791807 |
module DSGEN (
input Clock, // 10 MHz
input Reset_n,
input Configure,
input [9:0] Pattern,
input [9:0] PeriodDelay,
output [0:0] SignalOut
);
reg [0:0] Signal_q, Signal_d;
reg [9:0] Pattern_q, Pattern_d;
reg [9:0] PeriodDelay_q, PeriodDelay_d;
reg [9:0] ... | 7.675851 |
module that tightly packs bytes or byte sequences in to an output word of certain
* size.
*/
module dsi_byte_swapper
(
d_i,
size_i,
q_o);
parameter g_num_bytes = 4;
input [g_num_bytes * 8 - 1 : 0] d_i;
output [g_num_bytes * 8 - 1 : 0] q_o;
input [2:0] size_i;
wir... | 6.83232 |
module dsi_byte_shifter (
d_i,
shifted_o,
shift_i
);
parameter g_data_bytes = 4;
parameter g_max_shift = 9;
localparam c_output_width = 8 * (g_data_bytes + g_max_shift);
input [4:0] shift_i;
input [g_data_bytes * 8 - 1:0] d_i;
output [c_output_width - 1:0] shifted_o;
wire [c_output_width -... | 6.689816 |
module dsi_parity (
input [23:0] d_i,
output [ 7:0] p_o
);
assign p_o[0] = ^{d_i[2:0], d_i[5:4], d_i[7], d_i[11:10], d_i[13], d_i[16], d_i[23:20]};
assign p_o[1]=^{d_i[1:0], d_i[4:3], d_i[6], d_i[8], d_i[10], d_i[12], d_i[14], d_i[17], d_i[23:20]};
assign p_o[2] = ^{d_i[0], d_i[3:2], d_i[6:5], d_i[9], d... | 7.016506 |
module dsi_sync_chain #(
parameter length = 2
) (
input clk_i,
input rst_n_i,
input d_i,
output q_o
);
reg [length-1:0] sync;
always @(posedge clk_i) begin
sync[0] <= d_i;
sync[length-1:1] <= sync[length-2:0];
end
assign q_o = sync[length-1];
endmodule
| 6.752786 |
module dsi_wishbone_async_bridge (
input clk_wb_i,
input clk_csr_i,
input rst_n_i,
input [3:0] wb_adr_i,
input [7:0] wb_dat_i,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output wb_stall_o,
ou... | 8.252528 |
module dsm_control (
input clk,
input rst_n,
input signed [15:0] inpsig,
output signed [15:0] outsig,
output ce_out,
output enb_cic8,
output signed [15:0] In1,
output signed [15:0] In2,
output signed [15:0] Out1,
output signed [15:0] Out2,
output enb_hbf1,
output enb_hb... | 6.782791 |
module dsm_order6 #(
parameter FAC1_CGAINA = 6445,
parameter FAC1_CGAINB = 12100,
parameter FAC1_CGAING = 365,
parameter FAC2_CGAINA = 14301,
parameter FAC2_CGAINB = 29435,
parameter FAC2_CGAING = 1265,
parameter FAC3_CGAINA = 36520,
parameter FAC3_CGAINB = 926366,
parameter FAC3_CGA... | 7.074811 |
module
*
* Output
* DATA_O: Integrated Data Output
*
* Parameter
* PCM_Bit_Length: Parallel PCM Data Bit Length
-----------------------------------------------------------------------------*/
module DSM_SIGMA(
BCLK_I,
DATA_I,
DATA_O
);
/* Parameter Definition */
parameter PCM_Bit_Length = 32;
/* Input Defini... | 8.083219 |
module dsm_test ();
reg clk, reset_n;
reg [15:0] data;
wire outsignal, rdreq;
dsm dsm (
.clk(clk),
.reset_n(reset_n),
.data_in(data),
.outsignal(outsignal),
.rdreq(rdreq)
);
parameter CLOCK = 2;
initial begin
clk <= 0;
reset_n <= 0;
data <= 0;
#50 reset_n ... | 7.296351 |
module Add24 (
input [4:0] a,
input [4:0] b,
output [4:0] r
);
wire [5:0] t = a + b;
wire [1:0] u = t[5:3] == 0 ? 0 :
t[5:3] == 1 ? 1 :
t[5:3] == 2 ? 2 :
t[5:3] == 3 ? 0 :
t[5:3] == 4 ? 1 :
t[5:3] == 5 ? 2 :
... | 6.634573 |
module regs (
input clkcpu,
input clkdsp,
input we,
input rd,
input [7:0] wa,
input [31:0] din,
input [7:0] rda,
output reg [31:0] D,
input [7:0] rsa,
output reg [31:0] S,
input [8:0] rra,
output [15:0] dout
);
reg [31:0] r[255:0];
datamem16 RdRegs (
.wrclock(... | 7.379535 |
module DSPBranch (
ALU_result,
flow_mode,
address,
jump_addr,
jump_flag
);
input wire [`REG_WORD_LEN-1:0] ALU_result;
input wire [`FLOW_MODE_LEN-1:0] flow_mode;
input wire [`MEM_ADDR_LEN-1:0] address;
output wire [`MEM_ADDR_LEN-1:0] jump_addr;
output wire jump_flag;
reg [`MEM_ADDR_LEN... | 8.522826 |
module DSPBranch_TB ();
reg [`REG_WORD_LEN-1:0] ALU_result;
reg [`FLOW_MODE_LEN-1:0] flow_mode;
reg [`MEM_ADDR_LEN-1:0] address;
reg [`MEM_ADDR_LEN-1:0] internal_addr;
reg internal_flag;
wire [`MEM_ADDR_LEN-1:0] jump_addr;
wire jump_flag;
DSPBranch testBranch (
.ALU_result(ALU_result),
.fl... | 7.174694 |
module DspComplexExamples (
output [4:0] io_inByJ_real,
output [4:0] io_inByJ_imag,
output [4:0] io_inByJShortcut_real
);
wire [4:0] _T_58 = -5'sh4 - 5'sh7; // @[SIntTypeClass.scala 28:50]
wire [6:0] _T_59 = 5'sh7 * 2'sh1; // @[SIntTypeClass.scala 44:41]
wire [6:0] _T_60 = 5'sh3 * 2'sh1; // @[SIntT... | 7.539715 |
module DSPCTL ( /*AUTOARG*/
// Outputs
dmask,
dc,
dispwr,
dmapbenb,
// Inputs
clk,
reset,
state_fetch,
funct,
ir,
irdisp
);
input clk;
input reset;
input state_fetch;
input [3:0] funct;
input [48:0] ir;
input irdisp;
output [6:0] dmask;
output [9:0] dc... | 7.604018 |
module DSPFetch ( //Gretchen, stop trying to make fetch happen. It's not going to happen!
clk,
rst,
read_addr,
read_data,
instruction_out,
jump_addr,
jump_flag
);
input wire clk;
input wire rst;
input wire [`INST_WORD_LEN-1:0] read_data;
input wire [`MEM_ADDR_LEN-1:0] jump_addr;
... | 7.52528 |
module DSPfetch_tb;
reg rst, clk, jump_flag;
reg [`REG_ADDR_LEN-1:0] jump_addr;
reg [15:0] program_counter;
wire [`MEM_ADDR_LEN-1:0] read_addr;
wire [`INST_WORD_LEN-1:0] read_data, instruction_out;
module fetch DSPFetch(
.clk( clk ),
.rst( rst ),
.read_addr( read_addr ),
.read_data( read_data ),
.instruction_o... | 8.504176 |
module documentation
*/
module dspi_target_bfm(
input reset,
input sck,
input sdio0,
input sdio1,
input csn);
reg sdo_r = 0;
assign sdio0 = (~csn)?sdo_r:1'bz;
assign sdio1 = 1'bz;
reg[7:0] wordsize = 8;
reg[63:0] data = 0;
reg[7:0] bitcount = 0;
reg[7:0] dat_in_r = {8{1'b0}};
r... | 8.406034 |
module dspmac_16_40 (
input clk,
input rst_n,
input [1:0] opcode,
input signed [16-1:0] a_in,
input signed [16-1:0] b_in,
output signed [40-1:0] accu_out
);
reg signed [40-1:0] accu;
parameter [1:0] OP_CLR = 2'b00, OP_MUL = 2'b01, OP_MAC = 2'b10, OP_NOP = 2'b11;
always @(posedge clk or ... | 7.458566 |
module tb;
reg clk = 0;
reg rst_n = 0;
reg [ 1:0] opcode = 2'b11; // nop
reg signed [15:0] a_bus = 0;
reg signed [15:0] b_bus = 0;
wire signed [39:0] result;
// clock generation
always #1 clk = ~clk;
// devices under test
dspmac_16_40 dut (
clk,
... | 7.246752 |
module DSPMemoryLogic (
clk, // INPUT THIS IS A CLOCK IF YOU DONT GET IT GO AWAY
write_addr_2, // OUTPUT address bits for write address for memory bank 2
write_data, // OUTPUT data to be written to memory
write_en, // OUTPUT write enable active HIGH af
read_addr_1, // OUTPUT address bits for ... | 7.299563 |
module dspswitch #(
parameter DW = 32
) (
// {{{
input wire i_clk,
i_areset_n,
i_en,
//
input wire i_ce,
input wire [(DW-1):0] i_sample,
i_bypass,
//
output reg o_ce,
output reg [(DW-1):0] o_sample
// }}}
);
// o_ce
// {{{
initial o_ce = 0;
always @(posedge i... | 8.280823 |
module dsp_chain_2_dsp_chain_2_fp16_sop2_mult_module_8 (
input clk,
input reset,
input [1023:0] inp,
output [255:0] outp
);
dsp_chain_2_dsp_chain_2_fp16_sop2_mult_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[127:0]),
.outp (outp[31:0])
);
dsp_chain_2_dsp_chain_2_... | 7.114522 |
module dsp_chain_2_int_sop_2 (
clk,
reset,
ax1,
ay1,
bx1,
by1,
ax2,
ay2,
bx2,
by2,
result
);
input clk;
input reset;
input [17:0] ax1, bx1, ax2, bx2;
input [18:0] ay1, by1, ay2, by2;
output [36:0] result;
wire [36:0] chainout0, chainout1;
wire [36:0] chainin0,... | 7.466695 |
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