code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dsp_chain_2_int_sop_2_module_8 (
input clk,
input reset,
input [1183:0] inp,
output [295:0] outp
);
dsp_chain_2_int_sop_2_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[147:0]),
.outp (outp[36:0])
);
dsp_chain_2_int_sop_2_module inst1 (
.clk (clk),
... | 7.466695 |
module dsp_chain_3_dsp_chain_3_fp16_sop2_mult_module_8 (
input clk,
input reset,
input [1535:0] inp,
output [255:0] outp
);
dsp_chain_3_dsp_chain_3_fp16_sop2_mult_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[191:0]),
.outp (outp[31:0])
);
dsp_chain_3_dsp_chain_3_... | 6.787582 |
module dsp_chain_3_int_sop_2 (
clk,
reset,
ax1,
ay1,
bx1,
by1,
ax2,
ay2,
bx2,
by2,
ax3,
ay3,
bx3,
by3,
result
);
input clk;
input reset;
input [17:0] ax1, bx1, ax2, bx2, ax3, bx3;
input [18:0] ay1, by1, ay2, by2, ay3, by3;
output [36:0] result;
w... | 6.639386 |
module dsp_chain_3_int_sop_3_module_8 (
input clk,
input reset,
input [1775:0] inp,
output [295:0] outp
);
dsp_chain_3_int_sop_3_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[221:0]),
.outp (outp[36:0])
);
dsp_chain_3_int_sop_3_module inst1 (
.clk (clk),
... | 6.639386 |
module dsp_chain_4_dsp_chain_4_fp16_sop2_mult_module_8 (
input clk,
input reset,
input [2047:0] inp,
output [255:0] outp
);
dsp_chain_4_dsp_chain_4_fp16_sop2_mult_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[255:0]),
.outp (outp[31:0])
);
dsp_chain_4_dsp_chain_4_... | 6.630989 |
module dsp_chain_4_int_sop_2 (
clk,
reset,
ax1,
ay1,
bx1,
by1,
ax2,
ay2,
bx2,
by2,
ax3,
ay3,
bx3,
by3,
ax4,
ay4,
bx4,
by4,
result
);
input clk;
input reset;
input [17:0] ax1, bx1, ax2, bx2, ax3, bx3, ax4, bx4;
input [18:0] ay1, by1, ay... | 6.613307 |
module dsp_chain_4_int_sop_4_module_8 (
input clk,
input reset,
input [2367:0] inp,
output [295:0] outp
);
dsp_chain_4_int_sop_4_module inst0 (
.clk (clk),
.reset(reset),
.inp (inp[295:0]),
.outp (outp[36:0])
);
dsp_chain_4_int_sop_4_module inst1 (
.clk (clk),
... | 6.613307 |
module FPMult_PrepModule_dspchain (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [16-1:0] a; // Input A, a 32-bit floating point number
input [16-1:0] b; // Input B, a 32-bit floating point number
// Output ports
out... | 7.427166 |
module FPMult_NormalizeModule_dspchain (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [23-1:0] NormM; // Normalized 10
input [8:0] NormE; // Normalized 5
// Output Ports
output [8:0] RoundE;
output [8:0] RoundEP;
output [23:0] RoundM;
output [23:0] R... | 7.947312 |
module FPMult_RoundModule_dspchain (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [23:0] RoundM; // Normalized 10
input [23:0] RoundMP; // Normalized 5
input [8:0] RoundE; // Normalized 10 + 1
input [8:0] RoundEP; // Normalized ... | 7.570448 |
module FPAddSub_single_dspchain (
clk,
rst,
a,
b,
operation,
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [31:0] a; // Input A, a 32-bit floating point number
input [31:0] b; ... | 6.626859 |
module FPAddSub_c_dspchain (
SumS_5,
Shift,
CExp,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [32:0] SumS_5; // Smaller mantissa after 16|12|8|4 shift
input [4:0] Shift; // Shift amount
// Input ports
input [7:0] CExp;
// Output ports
outpu... | 6.777897 |
module FPAddSub_d_dspchain (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
NegE,
InputExc,
P,
Flags
);
// Input ports
input ZeroSum; // Sum is zero
input [8:0] NormE; // Normalized exponent
input [22:0] NormM; // Normalized mantissa
input R; ... | 7.649482 |
module dsp_control (
output DSP0_BMODE0,
output DSP0_BMODE1,
output DSP1_BMODE0,
output DSP1_BMODE1,
output DSP0_BYPASS,
output DSP1_BYPASS,
output xBYPASS,
output DSP0_NMI0,
output DSP1_NMI0,
output DSP0_NMI1,
output DSP1_NMI1,
output DSP0_BUS_READY,
output DSP1_BUS... | 6.558264 |
module dsp_core_rx_no_decimation #(
parameter BASE = 160
) (
input clk,
input rst,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [23:0] rx_fe_i,
input [23:0] rx_fe_q,
output [31:0] sample,
output [31:0] debug
);
assign run = 1'b1;
wire [31:0] phase_inc... | 6.797033 |
module ddc_chain_tb ();
reg clk, rst;
initial rst = 1;
initial #1000 rst = 0;
initial clk = 0;
always #5 clk = ~clk;
initial $dumpfile("ddc_chain_tb.vcd");
initial $dumpvars(0, ddc_chain_tb);
reg signed [23:0] adc_in;
wire signed [15:0] adc_out_i, adc_out_q;
always @(posedge clk) begin
$dis... | 7.027538 |
module coeff_bank #(
parameter V1 = 18'd1,
parameter V2 = 18'd2,
parameter V3 = 18'd3,
parameter V4 = 18'd4,
parameter V5 = 18'd5,
parameter V6 = 18'd6,
parameter V7 = 18'd7,
parameter V8 = 18'd8
) (
input [ 2:0] coeff_sel,
output [17:0] value
);
reg [17:0] selected_value;
... | 7.625645 |
module CPA #(
parameter N = 74,
parameter BP1 = 36,
parameter BP2 = 18
) (
input [N-1:0] data_x1,
input [N-1:0] data_x2,
input split1,
input split2,
output [N-1:0] result
);
wire [N-1:0] sum, carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : genFAs
FA FA... | 8.631551 |
module shifter #(
parameter N = 27,
parameter S = 9
) (
input [N-1:0] sum_in,
input [N-1:0] carry_in,
input shift,
input sign,
input enable,
output [N+S-1:0] sum_out,
output [N+S-1:0] carry_out
);
wire [N+S-1:0] sum, carry;
assign sum = (shift == 1'b0)? {{(S){(sum_in[N-1] |... | 6.861293 |
module Kbit_compressor_4to2 #(
parameter K = 18,
parameter BP = 0,
parameter BP2 = 0
) (
input [K-1:0] A,
input [K-1:0] B,
input [K-1:0] C,
input [K-1:0] D,
input split,
input split2,
output [K-1:0] Sum,
output [K-1:0] Carry,
output Cox
);
wire Cout[K-1:0];
wire [... | 7.495709 |
module compressor_4to2_gated (
input A,
input B,
input C,
input D,
input Cin,
input kill,
output Sum,
output Carry,
output Cout
);
wire w0, w1, w2;
assign w0 = A ^ B;
assign w1 = C ^ D;
assign w2 = w0 ^ w1;
assign Cout = kill & ((A & B) | (B & C) | (A & C));
assi... | 7.210439 |
module compressor_4to2 (
input A,
input B,
input C,
input D,
input Cin,
output Sum,
output Carry,
output Cout
);
wire w0, w1, w2;
assign w0 = A ^ B;
assign w1 = C ^ D;
assign w2 = w0 ^ w1;
assign Cout = (A & B) | (B & C) | (A & C);
assign Sum = Cin ^ w2;
assign Carr... | 7.210439 |
module arrayBlock_signed_gated (
input A,
input B,
input signed_ctrl,
input enable,
output mult
);
assign mult = enable & ((A & B) ^ signed_ctrl);
endmodule
| 8.236793 |
module arrayBlock_signed (
input A,
input B,
input signed_ctrl,
output mult
);
assign mult = (A & B) ^ signed_ctrl;
endmodule
| 8.236793 |
module arrayBlock_unsigned_gated (
input A,
input B,
input enable,
output mult
);
assign mult = enable & A & B;
endmodule
| 7.429949 |
module arrayBlock_unsigned (
input A,
input B,
output mult
);
assign mult = A & B;
endmodule
| 7.429949 |
module HA_gated (
input X,
input Y,
input kill,
output S,
output Cout
);
assign Cout = kill & X & Y;
assign S = X ^ Y;
endmodule
| 7.537988 |
module HA (
input X,
input Y,
output S,
output Cout
);
assign Cout = X & Y;
assign S = X ^ Y;
endmodule
| 9.138493 |
module FA_gated (
input X,
input Y,
input Cin,
input kill,
output S,
output Cout
);
assign Cout = kill & ((X & Y) | (X & Cin) | (Y & Cin));
assign S = X ^ Y ^ Cin;
endmodule
| 6.671916 |
module FA (
input X,
input Y,
input Cin,
output S,
output Cout
);
assign Cout = (X & Y) | (X & Cin) | (Y & Cin);
assign S = X ^ Y ^ Cin;
endmodule
| 8.362615 |
module operates than I do.
*/
module DspEmu(
input wire [ 1:0] op, // The DSP opcode
input wire [17:0] a, // INPUT A
input wire [17:0] b, // INPUT B
input wire [47:0] c, // INPUT C
output reg [47:0] p, // OUTPUT
input wire clk
);
always @(posedge cl... | 7.925834 |
module dsp #(
//the delay between a sensor reading and the ADC converter reading
parameter delay = 100,
//period t between each pulse in clock cycles
parameter t = 64,
//log base 2 of t used for counting
parameter t_log2 = 3,
//the signal duration in clock cycles
parameter d = 64,
... | 7.177312 |
module dsp_t1_20x18x64_cfg_ports (
input [19:0] a_i,
input [17:0] b_i,
input [ 5:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
... | 6.797918 |
module dsp_t1_20x18x64_cfg_params (
input [19:0] a_i,
input [17:0] b_i,
input [ 5:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
... | 6.797918 |
module dsp_framer36 #(
parameter BUF_SIZE = 9,
parameter PORT_SEL = 0,
parameter PROT_ENG_FLAGS = 1
) (
input clk,
input reset,
input clear,
input [35:0] data_i,
input src_rdy_i,
output dst_rdy_o,
output [35:0] data_o,
output src_rdy_o,
input dst_rdy_i
);
wire dfifo_in... | 7.693701 |
module dsp_jtag (
input DSP_EMU_A, //emulator signal, it is the signal from DSP to FPGA
input TMS_A, //the signal that controls the TAP controller
input TCK_A, //JTAG clock signal
input TDI_A, //data in
output TDO_A, //data out
//EMULATOR
output EMU_A, //emulator signal from DSP to... | 7.050575 |
module macc_simple (
input wire clk,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk) Z <= Z + (A * B);
endmodule
| 7.627824 |
module macc_simple_clr (
input wire clk,
input wire clr,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk)
if (clr) Z <= (A * B);
else Z <= Z + (A * B);
endmodule
| 7.60981 |
module macc_simple_arst (
input wire clk,
input wire rst,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else Z <= Z + (A * B);
endmodule
| 7.543504 |
module macc_simple_ena (
input wire clk,
input wire ena,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk) if (ena) Z <= Z + (A * B);
endmodule
| 7.279024 |
module macc_simple_arst_clr_ena (
input wire clk,
input wire rst,
input wire clr,
input wire ena,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else if (ena) begin
if ... | 7.543504 |
module macc_simple_preacc (
input wire clk,
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
reg [15:0] acc;
assign Z = acc + (A * B);
always @(posedge clk) acc <= Z;
endmodule
| 6.657201 |
module macc_simple_preacc_clr (
input wire clk,
input wire clr,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
reg [15:0] acc;
assign Z = (clr) ? (A * B) : (acc + (A * B));
always @(posedge clk) acc <= Z;
endmodule
| 6.657201 |
module dsp_mac_top #(
parameter OFFSET = 32'h0, //16'h24d0,
parameter Y1 = 0, //16'h24d0,
parameter Y2 = 0, //16'h0,
parameter Y3 = 0
) //16'h3279)
(
rst,
clk,
clk_en,
dvalid_in,
vdata_in,
dvalid_out,
vdata_out
);
//parameter definition
parameter... | 8.277523 |
module madd_simple_ports (
input wire [ 9:0] A,
input wire [ 8:0] B,
input wire [ 1:0] C,
output reg [18:0] Z
);
// There is no support for autmoatic inference of multiply+add hence the
// DSP cell needs to be instanced manually.
//
// To test the type change the "is_inferred" attribute is ... | 6.692074 |
module madd_simple_params (
input wire [ 9:0] A,
input wire [ 8:0] B,
input wire [ 1:0] C,
output reg [18:0] Z
);
// There is no support for autmoatic inference of multiply+add hence the
// DSP cell needs to be instanced manually.
//
// To test the type change the "is_inferred" attribute is... | 6.692074 |
module DSP_module (
input wire clk,
input wire rst_n,
input wire [7:0] datain,
output wire [7:0] dataout,
// 与RAM交互的线
input readyb0,
input readya1,
output reg [6:0] addrb0,
output reg [6:0] addra1,
output reg finishb0,
output reg finisha1,
output wire wea
);
parameter... | 7.79177 |
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
| 7.552041 |
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
| 7.746267 |
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
| 8.242894 |
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
| 7.590527 |
module mult_8x8_s (
input wire signed [ 7:0] A,
input wire signed [ 7:0] B,
output wire signed [15:0] Z
);
assign Z = A * B;
endmodule
| 8.578529 |
module dsp_mult (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
| 7.696849 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #1 clk <= ~clk;
// Data Clock
reg dclk;
initial dclk <= 1'b0;
always #2 dclk <= ~dclk;
// Input data / reference
reg [19:0] A0;
reg [17:0] B0;
reg [37:0] C0;
always @(negedge dclk) begin
A0 = $random;
B0 = $random;
... | 7.022577 |
module DSP_PREADD
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [26:0] AD,
input ADDSUB,
input [26:0] D_DATA,
input INMODE2,
input [26:0] PREADD_AB
);
// define constants
localparam MODULE_NAME = "DSP_PREADD";
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR... | 7.228939 |
module dsp_reset (
// input wire dsp_clockin, //input from an external clock
input DSP_CLKIN, //input clock from dcm clock2
input LOCKED_IN,
output reg DSP0_RESET,
output reg DSP1_RESET,
output reg xDSP_RESET, //for testing
input DSP_PLL_BYPASS,
output reg dsp_reset_button
);
pa... | 7.46047 |
module effects the IO of the DDC chain.
//By default, this entire module is a simple pass-through.
module dsp_rx_glue
#(
//the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
//frontend bus width
parameter WIDTH = 24
)
(
//control signals
input clock, input reset, input clear, input enable,
... | 7.900239 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module QL_DSP1 (
input wire [19:0] a,
input wire [17:0] b, (* clkbuf_sink *)
input wire clk0, (* clkbuf_sink *)
input wire clk1,
input wire [ 1:0] feedback0,
input wire [ 1:0] feedback1,
input wire load_acc0,
input wire load_acc1,
input wire ... | 7.713218 |
module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b,
in... | 6.964164 |
module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b,
in... | 6.964164 |
module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b,
... | 6.964164 |
module QL_DSP2_MULTADD_REGIN (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
input... | 6.798658 |
module QL_DSP2_MULTADD_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
inpu... | 6.798658 |
module QL_DSP2_MULTADD_REGIN_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
... | 6.798658 |
module QL_DSP2_MULTACC (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire load_acc,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b,
input w... | 6.798658 |
module QL_DSP2_MULTACC_REGIN (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
i... | 6.798658 |
module QL_DSP2_MULTACC_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
... | 6.798658 |
module QL_DSP2_MULTACC_REGIN_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,... | 6.798658 |
module dsp_t1_20x18x64_cfg_ports (
input wire [19:0] a_i,
input wire [17:0] b_i,
input wire [ 5:0] acc_fir_i,
output wire [37:0] z_o,
output wire [17:0] dly_b_o, (* clkbuf_sink *)
input wire clock_i,
input wire reset_i,
input wire [2:0] feedback_i,
input wire ... | 6.797918 |
module QL_DSP3_MULT ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b
);
parameter [92:0] MODE_BITS = 93'b0;
localparam [19:0] COEF... | 7.481567 |
module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b
);
wire [37:0] d... | 7.906614 |
module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b
);
parameter [9... | 7.906614 |
module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire unsigned_a,
input wire unsigned_b
);
parame... | 7.906614 |
module QL_DSP3_MULTADD (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
input wire subtract
);
... | 7.321843 |
module QL_DSP3_MULTADD_REGIN (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
input... | 7.321843 |
module QL_DSP3_MULTADD_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
inpu... | 7.321843 |
module QL_DSP3_MULTADD_REGIN_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire [5:0] acc_fir,
input wire load_acc,
input wire unsigned_a,
... | 7.321843 |
module QL_DSP3_MULTACC (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
input wi... | 7.321843 |
module QL_DSP3_MULTACC_REGIN (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
in... | 7.321843 |
module QL_DSP3_MULTACC_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,
i... | 7.321843 |
module QL_DSP3_MULTACC_REGIN_REGOUT (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z, (* clkbuf_sink *)
input wire clk,
input wire reset,
input wire [2:0] feedback,
input wire load_acc,
input wire unsigned_a,
input wire unsigned_b,... | 7.321843 |
module dsp_t1_20x18x64_cfg_params (
input wire [19:0] a_i,
input wire [17:0] b_i,
input wire [ 5:0] acc_fir_i,
output wire [37:0] z_o,
output wire [17:0] dly_b_o, (* clkbuf_sink *)
input wire clock_i,
input wire reset_i,
input wire [2:0] feedback_i,
input wire ... | 6.797918 |
module simd_mult_inferred (
input wire clk,
input wire [ 7:0] a0,
input wire [ 7:0] b0,
output reg [15:0] z0,
input wire [ 7:0] a1,
input wire [ 7:0] b1,
output reg [15:0] z1
);
always @(posedge clk) z0 <= a0 * b0;
always @(posedge clk) z1 <= a1 * b1;
endmodule
| 6.693085 |
module simd_mult (
input wire clk,
input wire [ 9:0] a0,
input wire [ 8:0] b0,
output reg [18:0] z0,
input wire [ 9:0] a1,
input wire [ 8:0] b1,
output reg [18:0] z1
);
always @(posedge clk) z0 <= a0 * b0;
always @(posedge clk) z1 <= a1 * b1;
endmodule
| 6.705191 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #1 clk <= ~clk;
// Data Clock
reg dclk;
initial dclk <= 1'b0;
always #2 dclk <= ~dclk;
// Input data / reference
reg [ 9:0] A0;
reg [ 9:0] A1;
reg [ 8:0] B0;
reg [ 8:0] B1;
reg [18:0] C0;
reg [18:0] C1;
always @(negedge dc... | 7.022577 |
module dsp_subsystem (
input sample_clock,
input reset,
input [1:0] selector,
input [15:0] input_sample,
output reg [15:0] output_sample
);
wire [15:0] filter_out;
wire [15:0] echo_out;
wire [15:0] output_sample_w;
assign output_sample_w = output_sample;
FIR_filter(
.clk(sample_c... | 6.548835 |
module dsp_system_top;
wire clk;
wire reset;
wire [15:0] io_data_out;
wire io_wr_strb;
wire [15:0] io_data_in;
wire [ 7:0] io_addr_out;
wire io_rd_strb;
wire [15:0] pm_addr;
wire [31:0] pm_data;
wire [15:0] dm0_addr;
wire [15:0] dm0_datai;
wire [15:0] dm0_datao;
... | 7.522348 |
module
`include "../RTL/sram.v" // data sram (15 bit address)
`include "sram_imem.v" // instruction sram (temporary, should be rom eventually)
module DSP_tb();
DSP dsp0( .clk (clk ),
.rst (rst ),
//Data Memory Bank I ... | 6.585576 |
module dsp_template #(
parameter NO_OF_BITS = 16
// parameter [7:0] opmode
) (
input wire clk,
input wire reset,
input wire [NO_OF_BITS-1:0] d_data,
input wire d_valid,
input wire [NO_OF_BITS-1:0] b_data,
input wire b_valid,
input wire [NO_OF_BITS... | 7.682404 |
module effects the IO of the DUC chain.
//By default, this entire module is a simple pass-through.
module dsp_tx_glue
#(
//the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
//frontend bus width
parameter WIDTH = 24
)
(
//control signals
input clock, input reset, input clear, input enable,
... | 7.900239 |
module dsram #(
parameter m = 10,
n = 32
) (
input clk,
w_en,
rst,
//input [m-1:0] addr,
input [n-1:0] addr,
input [n-1:0] din,
output [n-1:0] d_out
);
parameter mem_size = 2 ** m; // 2^m
reg [n-1:0] SRAM[0:mem_size-1]; // [0:((2^m)/2)-1] i_mem and [((2^m)/2): 2^m-1] d_mem
i... | 8.322382 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add26_COUT (
input [25:0] I0,
input [25:0] I1,
output [25:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire i... | 6.585333 |
module Counter26_COUT (
output [25:0] O,
output COUT,
input CLK
);
wire [25:0] inst0_O;
wire inst0_COUT;
wire [25:0] inst1_O;
Add26_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b... | 6.823478 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1... | 6.55013 |
module DssMod (
rst,
clk,
din,
clk_data,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟/DDS驱动时钟，频率：8×31×Rb=49.6 MHz
input din; //原始数据，频率：Rb=200 kbps
output clk_data; //输出的原始数据采样时钟，频率：Rb=200 kbps
output signed [15:0] dout; //载波调制后的扩频信号
//对clk信号8分频，产生PN码时钟信号clk_pn
reg [2:0]... | 8.080603 |
module DsssDemod (
rst,
clk,
din,
locked,
bit_sync,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：49.6MHz
input signed [7:0] din; //DSSS中频输入数据
output locked; //伪码锁定指示信号，高电平锁定
output bit_sync; //位同步信号
output dout; //解调后的数据输出
//实例化NCO核所需的接口信号
wire reset_n, out_valid... | 8.258561 |
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