code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DST (
input pclk,
rstn,
output reg hen,
ven,
hs,
vs
);
reg [11:1] hsg;
reg [10:1] vsg;
always @(posedge pclk, negedge rstn) begin
if (!rstn) begin
hsg <= 'd1039;
vsg <= 'd665;
end else if (!hsg && !vsg) begin
hsg <= 'd1039;
vsg <= 'd665;
end else ... | 7.247531 |
module dst_mux (
clk,
dm_re_EX_DM,
dm_rd_data_EX_DM,
pc_EX_DM,
dst_EX_DM,
rf_w_data_DM_WB,
jmp_imm_EX_DM
);
////////////////////////////////////////////////////////////////////////
// Simple 2:1 mux determining if ALU or DM is source for write to RF //
/////////////////////////////////... | 9.452258 |
module dsu_sram_ctrl(
clk, rst,
rxd, rxd_ready,
sram_ce, sram_we, sram_addr, sram_wdata,
download_enable
);
input clk;
input rst;
// receiver signals
input [7:0] rxd;
input rxd_ready;
// sram interface
output sram_ce;
output sram_we;
output [63:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sra... | 7.464467 |
module dsu_Tx(clk, rst, TxD_start, TxD_data, TxD, TxD_busy);
input clk, rst, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter Baud = 115200;
//parameter Baud = 9600;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmit... | 6.961785 |
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rs... | 7.073433 |
module ds_addr_calc (
lds_base,
in_addr,
out_addr
);
input [15:0] lds_base;
input [31:0] in_addr;
output [31:0] out_addr;
assign out_addr = {16'b0, lds_base} + in_addr;
endmodule
| 7.406525 |
module DT (
input clk,
input reset,
output reg done ,
output reg sti_rd ,
output wire [9:0] sti_addr ,
input [15:0] sti_di,
output reg res_wr ,
output reg res_rd ,
output wire [13:0] res_addr ,
output reg [7:0] res_do,
input [7:0] res_di
);
localparam W = -1... | 6.912486 |
module dtram(
adr,
do,
di,
we,
pwrdown,
clk
);
input [`dt_index:0] adr;
input [`dt_msb:0] di ;
output [`dt_msb:0] do ;
input clk;
input we ;
input pwrdown;
wire we_ ;
wire unknown_adr ;
// synopsys translate_off
// Dtag ram instantiated, maxblocks = 256 in decaf
reg [`dt_msb:0] t_ram [0:`dt_mx... | 6.534993 |
module rrdtag_0_LocalBist (
BIST_ADR,
BIST_WE,
func_do,
BIST_ON,
ERRN_ON,
INVERSE,
NO_COMP,
END_SEQ,
rrdtag_0_ENABLE,
BACKGROUND,
BIST_PATTERN,
we,
rrdtag_0_ERROR
);
input [`dt_msb:0] func_do;
output [`dt_msb:0] BIST_PATTERN;
input [8:0] BIST_ADR;
input BIST_... | 7.158063 |
module rrdtag_1_LocalBist (
BIST_ADR,
BIST_WE,
func_do,
BIST_ON,
ERRN_ON,
INVERSE,
NO_COMP,
END_SEQ,
rrdtag_1_ENABLE,
BACKGROUND,
BIST_PATTERN,
we,
rrdtag_1_ERROR
);
input [`dt_msb:0] func_do;
output [`dt_msb:0] BIST_PATTERN;
input [8:0] BIST_ADR;
input BIST_... | 6.934072 |
module rr512x5_LocalBist (
BIST_ADR,
BIST_WE,
func_doa,
BIST_ON,
ERRN_ON,
INVERSE,
NO_COMP,
END_SEQ,
rr512x5_ENABLE,
BACKGROUND,
BIST_PATTERN,
web,
rr512x5_ERROR
);
input [4:0] func_doa;
output [4:0] BIST_PATTERN;
input [8:0] BIST_ADR;
input BIST_WE, BIST_ON,... | 6.926058 |
module dtcm #(
parameter DW = 32,
parameter AW = 32,
parameter MW = 1024,
parameter RDW = 11
) (
input clk,
input rst_n,
input store_from_lsu,
input load_from_lsu,
input req_from_lsu,
input [AW-1:0] addr_from_lsu,
input [DW-1:0] store_result_fro... | 7.808708 |
module DtcRamMgt (
input reset,
input clk,
input WrConfirm,
input ReadConfirm,
input RamClr,
output reg RamFlag = 1'b0
);
reg ReadConfirm_i = 1'b0;
always @(posedge clk) ReadConfirm_i <= ReadConfirm | RamClr;
parameter WriteWait_st = 6'b00_0001;
parameter Write_st = 6'b00_0010;
para... | 6.905505 |
module of the DDL links
//* Author/Designer : Zhang.Fan (fanzhang.ccnu@gmail.com)
//*
//* Revision history:
//* 18-01-2013 : Initial release
//* 05-03-2013 : Split L0,L1 (posedge) and commands (negedge).
//*******************************************************************************
`timescale 1ns / 1ps
module... | 7.294035 |
module dtc_cmd (
input rdoclk,
//dtc_rx
input dtc_cmd_rnw,
input dtc_cmd_exec, //last 100ns
input dtc_cmd_feenal, //0: fpga, 1:altro
input [19:0] dtc_cmd_data,
input [19:0] dtc_cmd_addr,
output dtc_cmd_ack,
//memory interface
output wire dtc_fpga_cmd_exec,
output wire dtc... | 7.08184 |
module process event data and dcs reply from DTC ports
// Equivalent SRU = SRUV3FM2015070806_PHOS/SRUV3FM2015070901_PHOS
// Fan Zhang. 13 July 2015
module dtc_master_rx(
input dtc_data_p,
input dtc_data_n,
input dtc_return_p,
input dtc_return_n,
output fee_flag,
input ... | 7.753625 |
module sends triggers and commands to DTC ports
// Equivalent SRU = SRUV3FM2015070806_PHOS/SRUV3FM2015070901_PHOS
// Fan Zhang. 13 July 2015
module dtc_master_top(
//dtc phy
output dtc_clk_p,//output
output dtc_clk_n,//output
output dtc_trig_p,//output
output dtc_trig_n,//output
... | 7.613557 |
module does DTC data deserialization and word alignment for EMCal SRU
// Equivalent SRU = SRUV3FM2015070806_PHOS/SRUV3FM2015070901_PHOS
// Fan Zhang. 11 July 2015
`define DLY #1
module dtc_rx_deser(
input bitclk,
input bitclkdiv,
input dtc_data_p,
input dtc_data_n,
input dtc_return_p,
input dtc_return_n,
output [15:0... | 7.145156 |
module dtg (
input clock,
rst,
output reg horiz_sync,
vert_sync,
video_on,
output reg [11:0] pixel_row,
pixel_column
);
// Timing parameters (for 25MHz pixel clock and 640 x 480 display)
parameter
HORIZ_PIXELS = 640, HCNT_MAX = 800,
HSYNC_START = 640+16, HSYNC_END = 640... | 6.84836 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 4/9/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module DTrig (
input clk,
input rst_n,
input [6:0] in1,
input [6:0] in2,
input [6:0] in3,
input [6:0] in4,
input [6:0] in5,
input [6:0] in6,
output reg [6:0] o1,
output reg [6:0] o2,
output reg [6:0] o3,
output reg [6:0]... | 8.088481 |
module Dtrigger (
input clk,
input rst,
input [2:0] iState,
output [2:0] oState
);
reg [2:0] oState;
initial begin
oState = 3'b000;
end
always @(negedge clk or posedge rst) begin
if (rst) begin
oState = 3'b000;
end else begin
oState = iState;
end
end
endmodule
| 9.305364 |
module dtw_core_pe #(
parameter width = 16 // data width
) (
input wire clk,
input wire rst,
input wire running, // PE run enable
input wire [width-1:0] x, // squiggle sample
input wire [width-1:0] y, // reference sample
input wire [width-1:0] N, // north dependancy
inpu... | 7.958005 |
module dtw_core_ref_mem #(
parameter width = 16,
parameter ptrWid = 18,
parameter depth = 2 ** ptrWid,
parameter initalize = 0
) (
input wire clk,
input wire wen,
input wire [ptrWid-1:0] addr,
input wire [ width-1:0] din,
output reg [ width-1:0] dout
);
... | 7.450319 |
module MyDTypeFFV2 (
input clk,
input D,
output reg Q = 0,
output NQ
);
always @(posedge clk) begin
Q <= D;
end
assign NQ = ~Q;
endmodule
| 7.763821 |
module DT (
clk,
reset,
done,
sti_rd,
sti_addr,
sti_di,
res_wr,
res_rd,
res_addr,
res_do,
res_di
);
input clk;
input reset;
output done;
output sti_rd;
output [9:0] sti_addr;
input [15:0] sti_di;
output res_wr;
output res_rd;
output [13:0] res_addr;
output... | 6.735219 |
module control (
clk,
reset,
init_done,
is_object,
rd_res_done,
forward_done,
current_state /*, reg_is_obj*/
);
input clk, reset;
input init_done, is_object, rd_res_done, forward_done;
output current_state;
// output reg_is_obj;
reg [2:0] current_state, next_state;
// reg reg_... | 7.715617 |
module rdSti (
clk,
reset,
control_signal,
global_idx
);
input clk, reset;
input [2:0] control_signal;
output [13:0] global_idx;
reg [13:0] global_idx;
parameter [2:0] STATE_INIT = 3'b0,
STATE_CHECKSTI = 3'b1,
STATE_READRES = 3'b10,
STATE_WRITERES = 3'b11,
STATE_INIT2 = 3'b10... | 6.623962 |
module wrRes (
clk,
reset,
control_signal,
global_idx,
is_object,
rd_idx,
res_di,
res_do,
res_wr,
init_done,
forward_done
);
input clk, reset;
input [2:0] control_signal;
input [13:0] global_idx;
input is_object;
input [1:0] rd_idx;
input [7:0] res_di;
output [... | 6.905515 |
module rdRes (
clk,
reset,
control_signal,
global_idx,
res_rd,
res_addr,
rd_idx,
rd_res_done
);
input clk, reset;
input [13:0] global_idx;
input [2:0] control_signal;
output res_rd;
output [13:0] res_addr;
output [1:0] rd_idx;
output rd_res_done;
wire [13:0] rd_addr_idx... | 6.826732 |
module
module dt_mux
(
input [3:0] i_sel,
output reg [4:0] o_dt
);
always@(*) begin
case(i_sel)
0: o_dt <= 5'd2;
1: o_dt <= 5'd4;
2: o_dt <= 5'd6;
3: o_dt <= 5'd8;
4: o_dt <= 5'd10;
5: o_dt <= 5'd12;
6: o_dt <= 5'... | 7.678222 |
module DT (
clk,
reset,
done,
sti_rd,
sti_addr,
sti_di,
res_wr,
res_rd,
res_addr,
res_do,
res_di
);
input clk;
input reset;
output done;
output sti_rd;
output [9:0] sti_addr;
input [15:0] sti_di;
output res_wr;
output res_rd;
output [13:0] res_addr;
output... | 6.735219 |
module control (
clk,
reset,
current_state,
read_req
);
input clk, reset, read_req;
output [2:0] current_state;
reg [2:0] current_state, next_state;
parameter [2:0] STATE_INIT = 3'b0,
STATE_STIRD1 = 3'b1,
STATE_STIRD2 = 3'b10,
STATE_RESWR1 = 3'b11;
always @(posedge clk or nege... | 7.715617 |
module rdSti (
clk,
reset,
control_signal,
sti_rd,
sti_addr,
global_idx,
read_req
);
input clk, reset;
input [2:0] control_signal;
output sti_rd;
output [9:0] sti_addr;
output [13:0] global_idx;
output read_req;
reg [13:0] global_idx;
// wire [9:0] block_idx;
wire [ 3:0]... | 6.623962 |
module wrRes(clk, reset, control_signal, global_idx, sti_di, res_wr, res_do, res_addr);
input clk, reset;
input [2:0] control_signal;
input [13:0] global_idx;
input [15:0] sti_di;
output res_wr;
output [7:0] res_do;
output [13:0] res_addr;
reg [15:0] top_block, buttom_block;
reg [1:0] top_left, buttom_left;
wire [3... | 6.989272 |
module control (
clk,
reset,
init_done,
is_object,
rd_res_done,
forward_done,
backward_done,
current_state,
done
);
output [3:0] current_state;
input clk, reset, init_done, is_object, rd_res_done, forward_done, backward_done;
output done;
wire N37, N38, N39, N40, n3, n4, n5, ... | 7.715617 |
module top_module (
input clk,
input d,
output q
);
wire a, b;
flip_flop f1 (
clk,
d,
a
);
flip_flop f2 (
~clk,
d,
b
);
multiplexer p (
clk,
a,
b,
q
);
endmodule
| 7.203305 |
module multiplexer (
input op,
input a,
input b,
output out
);
assign out = (op & a) | (~op & b);
endmodule
| 7.049663 |
module flip_flop (
input clk,
input d,
output q
);
always @(posedge clk) q <= d;
endmodule
| 7.373981 |
module dual (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 36bit wide
// 16bit address
input clk;
input [35:0] data;
input [15:0] rdaddress;
input [15:0] wraddress;
input wren;
output [35:0] q;
wire const_zero;
wire [35:0] const_zero_data;
wire [35:0] dont_care_out;
... | 7.339771 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual2 (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 18bit wide
// 16bit address
input clk;
input [17:0] data;
input [15:0] rdaddress;
input [15:0] wraddress;
input wren;
output [17:0] q;
wire const_zero;
wire [17:0] const_zero_data;
wire [17:0] dont_care_out;
... | 7.025837 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual3 (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 8bit wide
// 16bit address
input clk;
input [7:0] data;
input [15:0] rdaddress;
input [15:0] wraddress;
input wren;
output [7:0] q;
wire const_zero;
wire [7:0] const_zero_data;
wire [7:0] dont_care_out;
as... | 7.341584 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module DualBRAM #(
parameter WIDTH = 36,
parameter LOG_DEP = 6
) (
input clock,
input enable,
input wen,
input [LOG_DEP-1:0] waddr,
input [LOG_DEP-1:0] raddr,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout,
output [WIDTH-1:0] wdout
);
localparam DEPTH = 1 << LOG_DEP;
/... | 6.741418 |
module DualBRAM1 #(
parameter WIDTH = 36,
parameter LOG_DEP = 6
) (
input clock,
input enable,
input wen,
input [LOG_DEP-1:0] waddr,
input [LOG_DEP-1:0] raddr,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout,
output reg [WIDTH-1:0] wdout
);
localparam DEPTH = 1 << LOG_DEP;... | 6.693314 |
module top_module (
input clk,
input d,
output q
);
reg pedge, nedge;
assign q = clk ? pedge : nedge;
always @(posedge clk) begin
pedge <= d;
end
always @(negedge clk) begin
nedge <= d;
end
endmodule
| 7.203305 |
module which implements a dual Gray code and and binary counter
// allowing increments or holds
module DualGrayCntr (
CLK,
RST,
INCR,
B_OUT, // Binary code output
G_OUT // Gray code output
);
parame... | 8.216215 |
module testDualGrayCntr ();
parameter dsize = 5;
wire CLK;
wire [dsize -1 : 0] BOUT;
wire [dsize -1 : 0] GOUT;
reg RST;
ClockGen #(20, 10, 10) sysclk (CLK);
initial begin
RST = `BSV_RESET_VALUE;
$display("running test");
$dumpfile("DualGrayCntr.dump");
$... | 7.200193 |
module DualMem (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
wire [7:0] sub_wire0;
wire [7:0] s... | 6.764821 |
module dualport #(
parameter addr_width = 10,
data_width = 12
) //prev_value = 16
(
input wire clock,
input wire [addr_width-1:0] addr_a,
input wire [addr_width-1:0] addr_b,
input wire we_a,
input wire we_b,
input wire [data_width-1:0] in_a,
input wire [data_width-1:0] in_b,
out... | 7.487616 |
module DualPortBRAM #(
parameter DATA = 72,
parameter ADDR = 10
) (
input wire clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:... | 7.950338 |
module dualPortBRamInstantiation (
clka,
clkb,
ena,
enb,
wea,
web,
addressA,
addressB,
dataInA,
dataInB,
dataOutA,
dataOutB
);
//---------------- FUNCTIONS ----------------------------
function integer log2;
input integer value;
begin
value = value - 1... | 7.396398 |
module DualPortedMem (
clk,
rst,
memWriteA,
memWriteB,
addrA,
addrB,
dataInA,
dataInB,
dataOutA,
dataOutB
);
input clk;
input rst;
input memWriteA;
input memWriteB;
input [4:0] addrA;
input [4:0] addrB;
input [31:0] dataInA;
input [31:0] dataInB;
output [31:0] ... | 7.664499 |
module DualPortRam(
CLK, // write clock
WE,
WADDR,
DIN,
RADDR,
DOUT
);
parameter addrWidth = 5; // number of bits in address-bus
parameter dataWidth = 16; /... | 7.477551 |
module dualPortRAMen (
clk,
en,
we,
addra,
addrb,
di,
doa,
dob
);
parameter blockLength = 32;
parameter memDepth = 1024;
parameter addressBitWidth = 10;
parameter file = "meminit.data";
input clk;
input en;
input we;
input [addressBitWidth-1:0] addra;
input [addressBi... | 8.149456 |
module DualPortRamTwoWritePorts (
clka,
clkb,
ena,
enb,
wea,
web,
addra,
addrb,
dia,
dib,
doa,
dob
);
parameter blockLength = 32;
parameter memDepth = 1024;
parameter addressBitWidth = 10;
input clka, clkb, ena, enb, wea, web;
input [5:0] addra, addrb;
inp... | 7.399304 |
module dualPortRAM_tb #(
parameter ADDR_WIDTH = 12,
DATA_WIDTH = 8
) ();
reg clk;
reg we;
reg [ADDR_WIDTH-1:0] read_addr_1;
reg [ADDR_WIDTH-1:0] read_addr_2;
reg [ADDR_WIDTH-1:0] write_addr;
reg [DATA_WIDTH-1:0] write_data;
wire [DATA_WIDTH-1:0] read_data_1;
wire [DATA_WIDTH-1:0] read_data_2;
... | 7.445923 |
module dualportram_8x16_8x16 (
clka,
clkb,
wea,
addra,
addrb,
dia,
dob
);
input clka;
input clkb;
input wea;
input [7:0] addra;
input [7:0] addrb;
input [15:0] dia;
output reg [15:0] dob;
reg [15:0] RAM0[255:0];
always @(posedge clka) begin
if (wea == 1'b1) RAM0[addra[... | 7.345676 |
module DualPort_FF_SyncWr_SyncRd (
// AHB global signals
HCLK,
// Write Port
fifoWrAddr,
fifoWrite,
fifoWrData,
// Read Port
fifoRdAddr,
fifoRdData
)
/* synthesis syn_ramstyle = "registers" */;
//============================================
// Parameter Declarations
//==... | 8.28206 |
module dualport_par #(
parameter WIDTH = 9, // 9 bits of data width
parameter DEPTH = 9
) // 9 bits of address
(
// Port A
input clk_a,
input we_a,
input [DEPTH-1:0] addr_a,
input [WIDTH-1:0] din_a,
// Port B
input clk_b,... | 7.800525 |
module true_dualport_ram #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
) (
input wire clka,
input wire [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input wire [DATALEN-1:0] wdataa,
input wire wea,
input wire ... | 6.945178 |
module true_dualport_ram_clear #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
) (
input wire clka,
input wire [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input wire [DATALEN-1:0] wdataa,
input wire wea,
input wir... | 6.945178 |
module dualport_RAM (
clk,
d_in_1,
d_out_1,
addr_1,
rd_1,
wr_1,
d_in_2,
d_out_2,
addr_2,
rd_2,
wr_2
);
input clk;
input [15:0] d_in_1;
output reg [15:0] d_out_1 = 0;
input [7:0] addr_1; // 8 LSB from address
input rd_1;
input wr_1;
input [15:0] d_in_2;
out... | 6.759499 |
module dualport_ram_async #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 4 //ram depth is equal to 2^ADDR_WIDTH
) (
input wr_clk,
input wr_rst_n,
input wr_en,
input [ADDR_WIDTH-1:0] wr_addr,
input [DATA_WIDTH-1:0] wr_data,
input rd_clk,
input rd_rst_n,
input rd_en,
inp... | 9.687781 |
module DualPort_RAM_SyncWr_SyncRd (
// AHB global signals
HCLK,
// Write Port
fifoWrAddr,
fifoWrite,
fifoWrData,
// Read Port
fifoRdAddr,
fifoRdData
);
//============================================
// Parameter Declarations
//============================================
... | 8.545337 |
module documentation
*/
`define TRUE 1'b1
`define FALSE 1'b0
module dualport_ram_tb;
localparam PERIOD = 10;
localparam HALF_CORE_PERIOD = PERIOD/2;
localparam RESET_CLK_NUM = 10;
localparam PROP_DELAY = 0;
parameter DATA_WIDTH ... | 8.406034 |
module dualport_sram (
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
/*verilator no_inline_module*/
parameter NUM_WMASKS = 2;
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 11;
parameter RAM_DEPTH = 1... | 7.331744 |
module dualpreg1 (
input clk,
input we,
input clr,
input [7:0] OR2,
input [7:0] A_in,
input [7:0] B_in,
input [7:0] ALU_IN,
input [7:0] SP,
input [7:0] mem,
input [2:0] mux_sel,
input [2:0] read_seg,
input [2:0] write_seg,
output reg [7:0] dataout_A,
output reg [7... | 7.15185 |
module dualpreg1tb ;
reg we;
reg clr;
reg clk;
reg [7:0] OR2;
reg [7:0] A_in;
reg [7:0] B_in;
reg [7:0] ALU_IN;
reg [1:0] mux_sel;
reg [2:0] read_seg;
reg [2:0] write_seg;
wire reg [7:0] dataout_A;
wire reg [7:0] dataout_B;
dualpreg1 dual11
(
.we (we),
.clr (clr),
.clk (clk),
.OR2 (... | 7.239254 |
module dualpreg_tm_test (
input clk,
input we,
input clr,
input [7:0] OR2,
input [7:0] A_in,
input [7:0] B_in,
input [7:0] ALU_IN,
input [7:0] SP,
input [7:0] mem,
input [2:0] mux_sel,
input [2:0] read_seg,
input [2:0] write_seg,
output reg [7:0] dataout_A,
output... | 7.912525 |
module dualram (
address_a,
address_b,
byteena_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input rden_a;
input rden_b;
input wren_a;
... | 7.048296 |
module dualram (
address_a,
address_b,
byteena_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input rden_a;
... | 6.888361 |
module dualreset (
input i_reset_1,
i_reset_2,
i_clk,
output o_out
);
reg [2:0] count = 0;
assign o_out = count[0];
assign reset = i_reset_1 & i_reset_2;
always @(posedge i_clk or posedge reset) begin
if (reset) count <= 0;
else count <= count + 1'b1;
end
endmodule
| 7.951619 |
module dualshock_controller #(
parameter FREQ = 27_000_000 // frequency of `clk`
) (
input clk, // Any main clock faster than 1Mhz
input I_RSTn, // MAIN RESET
output O_psCLK, // psCLK CLK OUT
output O_psSEL, // psSEL OUT
output O_psTXD, // psTXD OUT
input I_psRXD, // p... | 7.598881 |
module ps_txd (
input I_CLK,
input I_RSTn,
input I_WT, // pulse to start transmission
input I_EN,
input [7:0] I_TXD_DAT, // byte to transmit, lowest bit first
output reg O_psTXD // output pin
);
reg [7:0] ps; // data buffer
... | 6.677775 |
module dualsyncram #(
parameter DWIDTH = 16,
parameter AWIDTH = 8
) (
input clk,
input [AWIDTH-1:0] a_addr,
input [DWIDTH-1:0] a_wdata,
input a_we,
input [AWIDTH-1:0] b_addr,
input [DWIDTH-1:0] b_wdata,
input b_we,
//input [AWIDTH-1:0] a_raddr,
output reg [DWIDTH-1:0] a_rdata... | 8.269724 |
module dualtoplevel_tb ();
// UART interface
wire rx = 1;
wire tx;
reg clk = 1, reset = 1;
reg tx_req;
wire tx_busy;
reg [7:0] tx_byte;
wire br_1to2;
wire br_2to1;
wire tohost;
toplevel_bruteforcer test1 (
.clk(clk),
.core_clk(clk),
.reset(reset),
.uart_rx(tx),
.u... | 8.157441 |
module dual_act_mon ( /*AUTOARG*/
// Outputs
ack,
// Inputs
req_d0,
req_d1
);
parameter width = 8;
input [width-1:0] req_d0;
input [width-1:0] req_d1;
output ack;
reg ack;
initial ack = 0;
always begin
wait ((req_d0 | req_d1) === {width{1'b1}});
#1;
$display("%m: Recei... | 7.051168 |
module dual_port_ram (
input clk, //clock
input wr_en, //write enable for port 0
input [7:0] data_in, //Input data to port 0.
input [3:0] addr_in_0, //address for port 0
input [3:0] addr_in_1, //address for port 1
input port_en_0, //enable port 0.
... | 8.55547 |
module dual_port_ram_tb;
// Inputs
reg clk;
reg wr_en;
reg [7:0] data_in;
reg [3:0] addr_in_0;
reg [3:0] addr_in_1;
reg port_en_0;
reg port_en_1;
// Outputs
wire [7:0] data_out_0;
wire [7:0] data_out_1;
integer i;
// Instantiate the Unit Under Test (UUT)
dual_port_ram uut (
.clk(cl... | 8.55547 |
module dual_port_rom (
input clk,
input wr_en,
input [3:0] addr_in_0,
input [3:0] addr_in_1,
input port_en_0,
input port_en_1,
output [7:0] data_out_0,
output [7:0] data_out_1
);
reg [4:0] raddr;
reg [7:0] rom[7:0];
always @(posedge clk) begin
if (port_en_0 == 1 && wr_en == 1... | 7.014752 |
module dual_port_rom_tb;
// Inputs
reg clk;
reg wr_en;
reg [3:0] addr_in_0;
reg [3:0] addr_in_1;
reg port_en_0;
reg port_en_1;
// Outputs
wire [7:0] data_out_0;
wire [7:0] data_out_1;
integer i;
// Instantiate the Unit Under Test (UUT)
dual_port_rom uut (
.clk(clk),
.wr_en(wr_e... | 7.014752 |
module dual_async_bidir_buffer_gray_counter #(
parameter COUNTER_WIDTH = 9
) (
output reg [COUNTER_WIDTH-1:0] O, //'Gray' code count output.
input wire EN, //Count enable.
input wire RST, //Count reset.
input wire CLK,
... | 6.727561 |
module dual_async_bidir_buffer_fifo_status_register #(
parameter ADDRESS_WIDTH = 9
) (
input [ADDRESS_WIDTH-1:0] pWr_i,
input [ADDRESS_WIDTH-1:0] pRd_i,
input wr_clk_i,
input rd_clk_i,
output reg full_o,
output reg empty_o,
input rst_i,
output [8:0] pRd_in_Wr_o
);
reg Status = 0;
... | 6.727561 |
module dual_async_distributed_ram #(
parameter RAM_WIDTH = 72, // Bits for each row.
parameter RAM_ADDR_BITS = 8
) // Address of array.
(
input clk,
input wr_ram_enb,
input [RAM_ADDR_BITS-1:0] wr_ram_addr,
input [ RAM_WIDTH-1:0] wr_ram_data,
i... | 9.389726 |
module dual_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [63:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synop... | 6.688233 |
module dual_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [63:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESE... | 6.688233 |
module dual_circular_buffer
#(parameter
DATA_WIDTH = 16,
ADDR_WIDTH = 4,
DIFFERENCE = 3)
(input arst,
input up_clk,
input up_valid,
input [DATA_WIDTH-1:0] up_data,
input ... | 8.137914 |
module dual_clk_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 12
) (
input [(DATA_WIDTH-1):0] data_in,
input [(ADDR_WIDTH-1):0] read_addr,
input [(ADDR_WIDTH-1):0] write_addr,
input we,
input read_clock,
input ... | 8.063226 |
module async_fifo1 #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
input logic winc,
wclk,
wrst_n,
input logic rinc,
rclk,
rrst_n,
input logic [DSIZE-1:0] wdata,
output logic [DSIZE-1:0] rdata,
output logic wfull,
output logic rempty
);
logic [ASIZE-1:0] waddr, raddr;... | 6.899112 |
module fifomem #(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4 // Number of mem address bits
) (
input logic winc,
wfull,
wclk,
input logic [ADDRSIZE-1:0] waddr,
raddr,
input logic [DATASIZE-1:0] wdata,
output logic [DATASIZE-1:0] rdata
);
// RTL Ver... | 7.266945 |
module rptr_empty #(
parameter ADDRSIZE = 4
) (
input logic rinc,
rclk,
rrst_n,
input logic [ADDRSIZE : 0] rq2_wptr,
output logic rempty,
output logic [ADDRSIZE-1:0] raddr,
output logic [ADDRSIZE : 0] rptr
);
logic [ADDRSIZE:0] rbin;
logic [ADDRSIZE:0] rgraynext, rbinnext;
//----... | 7.624786 |
module wptr_full #(
parameter ADDRSIZE = 4
) (
input logic winc,
wclk,
wrst_n,
input logic [ADDRSIZE : 0] wq2_rptr,
output logic wfull,
output logic [ADDRSIZE-1:0] waddr,
output logic [ADDRSIZE : 0] wptr
);
logic [ADDRSIZE:0] wbin;
logic [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYS... | 7.819773 |
module dual_clock_buffer #(
parameter width = 8
) (
input wire reset,
input wire i_clk,
input wire i_valid,
output wire i_ready,
input wire [width-1:0] i_data,
input wire o_clk,
output wire o_valid,
input wire o_ready,
output wire [width-1:0] o_data
);
reg [width-1:0] data;
... | 6.930402 |
module dual_clock_buffer_tb ();
parameter IN_STEP = 200;
parameter OUT_STEP = 50;
initial begin
$dumpfile("dual_clock_buffer_tb.vcd");
$dumpvars;
end
reg o_clk;
initial begin
o_clk = 1'b0;
forever #(OUT_STEP / 2) o_clk = ~o_clk;
end
reg i_clk;
initial begin
i_clk = 1'b0;
fo... | 6.930402 |
module dual_clock_fifo #(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 32 // mudar rd_addr_gray_wr_r
) (
input wire wr_rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_rst_i,
input wire rd_clk_i,
input wire r... | 7.308776 |
module dual_clock_fifo #(
parameter ADDR_WIDTH = 3,
parameter DATA_WIDTH = 32
) (
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_clk_i,
input wire rd_en_i,
output reg [DATA_WIDTH-1:0] rd_data_o,
output reg full_o,
outpu... | 7.308776 |
module dual_clock_fifo_tb #(
parameter data_width = 16,
parameter depth_width = 8
);
localparam DEPTH = 1 << depth_width;
vlog_tb_utils vlog_tb_utils0 ();
vlog_tap_generator #("dual_clock_fifo.tap", 4) vtg ();
reg slow_clk = 1'b1;
reg fast_clk = 1'b1;
reg rst = 1'b1;
reg faster_write_clk ... | 7.308776 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.