code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module NABPDualClockSimpleDualPortRAM
#(
parameter pDataLength = `kFilteredDataLength,
parameter pRAMSize = `kProjectionLineSize,
parameter pAddrLength = `kSLength // log2(pRAMSize)
) (
input wire clk_in,
input wire clk_out,
input wire we,
input wire [pAddrLength-1:0] addr_in,
input wire... | 6.588186 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module dual_config (
input wire [ 2:0] avmm_rcv_address, // avalon.address
input wire avmm_rcv_read, // .read
input wire [31:0] avmm_rcv_writedata, // .writedata
input wire avmm_rcv_write, // .write
output wire [31:0] avmm_rcv_readdata, // .... | 7.095285 |
module dual_config (
avmm_rcv_address,
avmm_rcv_read,
avmm_rcv_writedata,
avmm_rcv_write,
avmm_rcv_readdata,
clk,
nreset
);
input [2:0] avmm_rcv_address;
input avmm_rcv_read;
input [31:0] avmm_rcv_writedata;
input avmm_rcv_write;
output [31:0] avmm_rcv_readdata;
input clk;
inp... | 7.095285 |
module dual_core_w_lock_memory (
input clk,
input rst,
input start,
output wire [1:0] done,
output reg [1:0] lock,
output wire [3:0] S0,
S1,
NS0,
NS1,
output wire [31:0] r10,
r20,
r11,
r21,
output wire [31:0] result0,
result1,
output wire [6:0] opcode0,
... | 7.291774 |
module dual_demux (
Y0,
Y1,
SEL,
EN,
A0,
A1,
B0,
B1
);
input wire Y0, Y1, SEL, EN;
output A0, A1, B0, B1;
assign A0 = EN & ~SEL & Y0;
assign A1 = EN & ~SEL & Y1;
assign B0 = EN & SEL & Y0;
assign B1 = EN & SEL & Y1;
endmodule
| 7.539062 |
module dual_div #(
parameter P_WIDTH = 5,
parameter S_WIDTH = 3
) (
input wire clk, // 时钟输入
input wire rst_n, // 复位信号，低有效
input wire [S_WIDTH-1:0] Si, // S 计数器的最大值
input wire [P_WIDTH-1:0] Pi, // P 计数器的最大值
output wire Fdiv // 分频输出
);
wire f89;
w... | 8.177186 |
module dual_edge_detector_MEALY (
input clk,
rst_n,
input level, //active-high
output reg edg
);
//FSM declarations
localparam zero = 1'b0, one = 1'b1;
reg state_reg, state_nxt;
//FSM register operation
always @(posedge clk, negedge rst_n) begin
if (!rst_n) state_reg <= zero;
else st... | 6.655155 |
module dual_edge_detector_MOORE (
input clk,
rst_n,
input level, //active high
output reg edg
);
//FSM declarations
localparam [1:0] zero = 2'd0, r_edg = 2'd1, one = 2'd2, f_edg = 2'd3;
reg [1:0] state_reg, state_nxt;
//FSM register operation
always @(posedge clk, negedge rst_n) begin
i... | 6.655155 |
module dual_edge_detector_simpler (
input clk,
rst_n,
input level,
output edg
);
reg level_reg = 0;
always @(posedge clk, negedge rst_n)
if (!rst_n) level_reg <= 0;
else level_reg <= level;
assign edg = level ^ level_reg;
endmodule
| 6.655155 |
module debouncing_TEST (
input clk,
rst_n,
input sw, //active low
output [7:0] seg_out,
output [5:0] sel_out
);
reg [3:0] counter_db = 0, counter_sw = 0; //counts from 0-to-9 then wraps up
reg sw_reg = 0, db_reg = 0;
wire [3:0] counter_db_nxt, counter_sw_nxt;
wire tick_db, tick_sw;
wire... | 8.156961 |
module dual_edge_detector_TB;
// Inputs
reg clk;
reg rst_n;
reg level;
// Outputs
wire edg_1, edg_2, edg_3;
// Instantiate the Unit Under Test (UUT)
dual_edge_detector_MOORE uut1 (
.clk (clk),
.rst_n(rst_n),
.level(level),
.edg (edg_1)
);
dual_edge_detector_MEALY uut2 (
... | 6.655155 |
module dual_edge_mealy (
input wire clk,
reset,
input wire level,
output reg tick
);
// symbolic state declaration
localparam zero = 1'b0, one = 1'b1;
// signal declaration
reg state_reg, state_next;
// state register
always @(posedge clk, posedge reset)
if (reset) state_reg <= zer... | 7.971134 |
module dual_edge_moore (
input wire clk,
reset,
input wire level,
output reg tick
);
// symbolic state declaration
localparam [1:0] zero = 2'b00, edg = 2'b01, one = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
// state register
always @(posedge clk, posedge reset) begi... | 8.148406 |
module edge_detect_tb;
// signal declaration
localparam T = 10; //clk period
reg clk, reset;
reg level;
wire tick_mealy;
wire tick_moore;
// instance
dual_edge_moore edg_moore (
.clk (clk),
.reset(reset),
.level(level),
.tick (tick_moore)
);
// mealy edge detector instan... | 7.698943 |
module dual_env;
reg activate_0r;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire activate_0a; // From basicenc of Balsa_basicenc.v
wire [127:0] data__in_0a0d; // From data_drv of dual_psv_drv.v
wire [127:0] data__in_0a1d; // From data_drv of dual_psv_drv.... | 6.548274 |
module dual_gray_counter #(
parameter addr_size = 4
) (
input clk,
output [addr_size:0] gray_count_st, //msb for cycle detction
output [addr_size-1:0] gray_count_nd,
input reset_n,
input en
);
reg [addr_size:0] Q_reg, Q_next;
wire _2nd_msb;
always @(posedge clk, negedge reset_n) begin
... | 7.202583 |
module dual_hbridge #(
parameter current_bits = 4, // bit precision of current
parameter microstep_bits = 8, // bit precision of microsteps
parameter vref_off_brake = 1, // "decay mode"
parameter microstep_count = 256 // quarter-cycle divisions
) (
input clk,
input ... | 8.941102 |
module dual_mode_disp (
input clk,
rst_n,
input rx,
input[3:0] key, //key[0] to move cursor to right,key[1] to move cursor down,key[2] to write @ current cursor,key[3] to change display mode
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vg... | 7.827364 |
module processing_element_tb ();
parameter CLOCK_PERIOD = 100; // 10 MHz clock
parameter NUM_TEST = 10; // Number of tests
reg sys_clk;
wire ready1;
wire ready2;
wire ready;
assign ready = ready1 & ready2;
reg start;
reg [9:0] test_err;
reg [9:0] test_count;
reg [7:0] isu = 0;
wire [7:0] o... | 6.504296 |
module dual_port0 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [6:0] address_a;
input [6:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
//... | 6.510065 |
module dual_port_asyncout_ram #(
parameter D_WIDTH = 11,
parameter A_WIDTH = 2
) (
input clk,
input we,
input [(D_WIDTH-1):0] data,
input [(A_WIDTH-1):0] read_addr,
write_addr,
output [(D_WIDTH-1):0] q
);
reg [D_WIDTH-1:0] ram[2**A_WIDTH-1:0];
always @(posedge clk) begin
if (we... | 8.927961 |
module dual_port_blockram #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 64,
parameter NUM_SET = 64,
parameter SET_PTR_WIDTH_IN_BITS = 6
) (
input clk_in,
input read_en_in,
input [SET_PTR_WIDTH_IN_BITS - 1 : 0] read_set_addr_in,
... | 7.676835 |
module/serial_tx.v"
`include "../../clock_divider_module/clock_divider_pulse.v"
`include "../dual_port_block_ram_module/block_ram.v"
module dual_port_block_ram_test(
output ser_tx,
output led_blue,
output led_green,
output led_red,
output spi_ssn
);
wire led_green_tog;
wire led_red_tog;
... | 7.012184 |
module : dual_port_BRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the ... | 6.868247 |
module : dual_port_BRAM_memory_subsystem
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to... | 6.868247 |
module dual_port_buffer (
input reset,
input write_clk,
input [BUFFER_ADDR_WIDTH-1:0] write_addr,
input [DATA_WIDTH-1:0] write_data,
input write_enable,
input read_clk,
input [BUFFER_ADDR_WIDTH-1:0] read_addr,
output reg [DATA_WIDTH-1:0] read_data
);
parameter DATA_WIDTH = 16;
par... | 8.062416 |
module RisingEdge_DFlipFlop (
D,
D_b,
clk,
Q,
Q_b
);
input D; // Data input
input D_b;
input clk; // clock input
output Q; // output Q
output Q_b;
always @(posedge clk) begin
Q <= D;
Q_b <= D_b;
end
endmodule
| 6.552756 |
module Dual_Port_Mem #(
parameter SIZE = 32,
parameter ADDR_WIDTH = 4
) (
clk,
funct3,
address,
w_data,
MEM_write,
data_out,
q,
addr
);
input clk;
input [2:0] funct3;
input [ADDR_WIDTH+1:0] address;
input [SIZE-1:0] w_data;
input [ADDR_WIDTH-1:0] addr;
input MEM_wri... | 7.570566 |
module dual_port_mem_ww (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 32bit wide
// 13bit address
input clk;
input [31:0] data;
input [12:0] rdaddress;
input [12:0] wraddress;
input wren;
output [31:0] q;
wire const_zero;
wire [31:0] const_zero_data;
wire [31:0] dont... | 8.046258 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual_port_mem_xx (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 32bit wide
// 13bit address
input clk;
input [31:0] data;
input [12:0] rdaddress;
input [12:0] wraddress;
input wren;
output [31:0] q;
wire const_zero;
wire [31:0] const_zero_data;
wire [31:0] dont... | 8.046258 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual_port_mem_yy (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 32bit wide
// 13bit address
input clk;
input [31:0] data;
input [12:0] rdaddress;
input [12:0] wraddress;
input wren;
output [31:0] q;
wire const_zero;
wire [31:0] const_zero_data;
wire [31:0] dont... | 8.046258 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module dual_port_mem_zz (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
// 32bit wide
// 13bit address
input clk;
input [31:0] data;
input [12:0] rdaddress;
input [12:0] wraddress;
input wren;
output [31:0] q;
wire const_zero;
wire [31:0] const_zero_data;
wire [31:0] dont... | 8.046258 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module : dual_port_RAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the S... | 8.739851 |
module dual_port_RAM0 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [6:0] address_a;
input [6:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QI... | 6.886919 |
module dual_port_RAM1 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [6:0] address_a;
input [6:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QI... | 6.886919 |
module dual_port_RAM2 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [6:0] address_a;
input [6:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QI... | 6.886919 |
module dual_port_RAM3 (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [6:0] address_a; //128 location (actually only use 96)
input [6:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [... | 6.886919 |
module dual_port_ram_16k (
input clk,
input wen,
input ren,
input [10:0] waddr,
input [10:0] raddr,
input [7:0] din,
output [7:0] dout
);
dual_port_sram_16kb memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (din),
.rclk (clk),
.r... | 8.55547 |
module dual_port_sram_16kb (
input wclk,
input wen,
input [10:0] waddr,
input [7:0] data_in,
input rclk,
input ren,
input [10:0] raddr,
output [7:0] data_out
);
reg [7:0] ram[2047:0];
reg [7:0] internal;
assign data_out = internal;
always @(posedge wclk) begin
if (wen) beg... | 9.237963 |
module dual_port_ram_1k (
input clk,
input wen,
input ren,
input [6:0] waddr,
input [6:0] raddr,
input [7:0] din,
output [7:0] dout
);
dual_port_sram_1kb memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (din),
.rclk (clk),
.ren ... | 8.55547 |
module dual_port_sram_1kb (
input wclk,
input wen,
input [6:0] waddr,
input [7:0] data_in,
input rclk,
input ren,
input [6:0] raddr,
output [7:0] data_out
);
reg [7:0] ram[127:0];
reg [7:0] internal;
assign data_out = internal;
always @(posedge wclk) begin
if (wen) begin
... | 9.237963 |
module dual_port_ram_asynchronous_behavioral (
input clk_A, // Clock A
input clk_B, // Clock B
// PORT A
input we_A, // Write enable
input [ADDR_WIDTH-1:0] addr_A, // Address
input [DATA_WIDTH-1:0... | 8.55547 |
module dual_port_ram_lattice #(
parameter ADDR_WIDTH = 32,
DATA_WIDTH = 32
) (
input wire [ADDR_WIDTH - 1 : 0] waddr,
input wire [ADDR_WIDTH - 1 : 0] raddr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire write_en,
input wire wclk,
input wir... | 8.55547 |
module xilinx_dual_port_ram_sync #(
parameter ADDR_WIDTH = 6,
DATA_WIDTH = 8
) (
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
addr_b,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a,
dout_b
);
// signal declaration
reg [DATA_WIDTH-1:0... | 8.91283 |
module dual_port_ram_synchronous_behavioral (
input clk, // Clock
// PORT A
input we_A, // Write enable
input [ADDR_WIDTH-1:0] addr_A, // Address
input [DATA_WIDTH-1:0] data_in_A, // Data to write
output reg [DATA_WIDTH-... | 8.55547 |
module DUAL_PORT_RAM_SYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg WE_A, WE_B;
reg [3:0] ADDR_A, ADDR_B;
reg [7:0] DATA_IN_A, DATA_IN_B;
wire [7:0] DATA_OUT_A, DATA_OUT_B;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP_A, DATA_OUTEXP_B;
i... | 7.049627 |
module ram_2 #(
// parameter w=32,
// parameter h=8,
// parameter l=4
// )(
// clk,
// ram_wdat,
// ram_we,
// ram_type,
// ram_addr,
// ram_re,
// data_reg,
// sign
// );
// input wire clk;
// input wire [w-1:0] ram_wdat;
// input wire ra... | 7.10412 |
module dual_port_rom #(
parameter WIDTH = 96,
LENGTH = 1024,
INIT_FILE = ""
) (
clk,
en,
addra,
addrb,
doa,
dob
);
input clk, en;
input [$clog2(LENGTH)-1:0] addra, addrb;
output [WIDTH-1:0] doa, dob;
(* rom_style = "distributed" *) reg [WIDTH-1:0] ram[LENGTH-1:0];
reg [WIDT... | 7.014752 |
module dual_port_sram #(
parameter DATA_WIDTH = 8, // registers are 8 bits in width
parameter ADDR_WIDTH = 5 // 32 registers
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] rr_addr,
input wire [ADDR_WIDTH-1:0] rd_addr,
inout wire [DATA_WIDTH-1:0] rr_data,
inout wire [DATA... | 9.237963 |
module single_port_syn //128k by 3 single port sync ram(uses block ram)
#(
parameter ADDR_WIDTH = 16,
DATA_WIDTH = 3
) (
input clk,
input we,
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_W... | 8.366411 |
module dual_port_syncout_enabled_ram #(
parameter D_WIDTH = 8,
parameter A_WIDTH = 13
) (
input clk,
input rst,
input enableout,
input we,
input [(D_WIDTH-1):0] data,
input [(A_WIDTH-1):0] read_addr,
input [(A_WIDTH-1):0] write_addr,
output reg [(D_WIDTH-1):0] q
);
(*ramstyle ... | 7.218562 |
module dual_prio_test (
input wire clk,
input wire [11:0] sw,
output wire [ 7:0] sseg,
output wire [ 3:0] an
);
// signal declaration
wire [3:0] out_first, out_second;
wire [7:0] led0, led1, led2, led3;
// instance of priority encoder
dual_prio_encoder prio_encoder_unit (
.r(s... | 8.2643 |
module dual_reg_in (
CLK,
IN,
SEL,
WEN_L,
OUTA,
OUTB
);
input CLK;
input [7:0] IN;
input SEL;
input WEN_L;
output [7:0] OUTA;
output [7:0] OUTB;
reg [7:0] OUTA;
reg [7:0] OUTB;
always @(posedge CLK) begin
if (~WEN_L) begin
if (SEL) OUTB = IN;
else OUTA = IN;... | 7.140997 |
module dual_scrolling_display (
input data_clk,
display_clk,
input [9:0] h_pos,
v_pos,
input valid_draw,
input [11:0] sink_data_a,
sink_data_b,
input sink_valid_a,
sink_valid_b,
output reg [7:0] disp_red,
disp_green,
disp_blue
);
//
wire [11:0] buffer_a_data, buffer_... | 8.535381 |
module dual_write_ram (
input wire iClock,
input wire [15:0] iData1,
input wire [15:0] iData2,
input wire [15:0] iWriteAddress1,
input wire [15:0] iWriteAddress2,
input wire [15:0] iReadAddress1,
input wire [15:0] iReadAddress2,
input wire iWE1,
input wire iWE2,
output reg [... | 7.544223 |
module duc (
input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out... | 7.104326 |
module duck_hunt (
clk_100mhz,
rst,
clk_25mhz,
blank,
comp_sync,
hsync,
vsync,
pixel_r,
pixel_g,
pixel_b,
led0,
led1,
trigger_in,
light_in,
data_in,
latch_out,
clk_out,
//clk12mhz, synch, audio_data_out, audio_rst, //audio I/O , tie to pins listed ... | 6.603182 |
module cntr_11_0_6da79292a37693ee (
clk,
ce,
sinit,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input sinit;
output [2 : 0] q;
// synthesis translate_off
wire \blk00000001/sig0000000f ;
wire \blk00000001/sig0000000e ;
wire \blk00000001/sig0000000d ;
wire \b... | 6.50478 |
module cntr_11_0_7a9f00e1c86c8fba (
clk,
ce,
sinit,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input sinit;
output [3 : 0] q;
// synthesis translate_off
wire \blk00000001/sig00000013 ;
wire \blk00000001/sig00000012 ;
wire \blk00000001/sig00000011 ;
wire \b... | 6.613637 |
module dmg_72_1c9994abe91d1da0 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [3 : 0] a;
input [31 : 0] d;
input [3 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(4),
.C_DEFAUL... | 6.713338 |
module dmg_72_903d17a1900ee539 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [3 : 0] a;
input [31 : 0] d;
input [3 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(4),
.C_DEFAUL... | 6.637839 |
module srl17e (
clk,
ce,
d,
q
);
parameter width = 16;
parameter latency = 8;
input clk, ce;
input [width-1:0] d;
output [width-1:0] q;
parameter signed [5:0] a = latency - 2;
wire [width - 1:0] #0.2 d_delayed;
wire [width - 1:0] srl16_out;
genvar i;
assign d_delayed = d;
generate
... | 6.671364 |
module synth_reg (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
parameter complete_num_srl17es = latency / 17;
parameter remaining_latency = latency % 17;
parameter temp_num_srl17es = (latency / 1... | 7.341053 |
module synth_reg_reg (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
wire [width - 1:0] o;
genvar idx;
reg [width - 1:0] reg_bank[latency:0];
integer j;
initial begin
for (j = 0; j < latenc... | 6.614179 |
module synth_reg_w_init (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 'b0000;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
wire [(latency + 1) * width - 1:0] dly_i;
wire #0.2... | 7.190939 |
module single_reg_w_init (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 8'b00000000;
input [width - 1:0] i;
input ce;
input clr;
input clk;
output [width - 1:0] o;
parameter [0:0] init_index_val = (init_index == 1) ? 1'b1... | 8.407813 |
module cast (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 1;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
p... | 6.505444 |
module pad_lsb (
inp,
res
);
parameter signed [31:0] orig_width = 4;
parameter signed [31:0] new_width = 2;
input [orig_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] pad_pos = new_width - orig_width - 1;
wire [new_width-1:0] result;
genvar i;
assign res = result;
... | 6.592947 |
module zero_ext (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] new_width = 2;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
genvar i;
assign res = result;
generate
if (new_width > old_width) begin : u0
assign r... | 6.922503 |
module align_input (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] delta = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] abs_delta = (delta... | 6.860388 |
module round_towards_inf (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [... | 6.669142 |
module round_towards_even (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input ... | 6.669142 |
module trunc (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - ... | 6.502157 |
module wrap_arith (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter sign... | 8.173074 |
module xldelay #(
parameter width = -1,
latency = -1,
reg_retiming = 0,
reset = 0
) (
input [width-1:0] d,
input ce,
clk,
en,
rst,
output [width-1:0] q
);
generate
if ((latency == 0) || ((reg_retiming == 0) && (reset == 0))) begin : srl_delay
synth_reg #(width, latenc... | 7.291426 |
module mux_1f6c522247 (
input [(1 - 1):0] sel,
input [(16 - 1):0] d0,
input [(16 - 1):0] d1,
output [(16 - 1):0] y,
input clk,
input ce,
input clr
);
wire [ (1 - 1):0] sel_1_20;
wire [(16 - 1):0] d0_1_24;
wire [(16 - 1):0] d1_1_27;
localparam [(16 - 1):0] const_value = 16'b0000000000... | 6.937596 |
module reinterpret_81b71e1f8b (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.738645 |
module reinterpret_0e0c011a4e (
input [(18 - 1):0] input_port,
output [(18 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(18 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 7.177582 |
module reinterpret_5668f8e576 (
input [(48 - 1):0] input_port,
output [(48 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(48 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.920317 |
module xldpram_dist_duc_16ch_341 (
dina,
addra,
wea,
ena,
a_ce,
a_clk,
douta,
addrb,
enb,
b_ce,
b_clk,
doutb
);
parameter core_name0 = "";
parameter addr_width = 12;
parameter c_width = 12;
parameter c_address_width = 4;
parameter latency = 1;
input [c_width-1... | 7.00592 |
module reinterpret_2824f666f2 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] input_port_1_40;
wire [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.534911 |
module reinterpret_dee95c6dbb (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(16 - 1):0] input_port_1_40;
wire signed [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.775554 |
module xlslice (
x,
y
);
parameter new_msb = 9;
parameter new_lsb = 1;
parameter x_width = 16;
parameter y_width = 8;
input [x_width-1:0] x;
output [y_width-1:0] y;
assign y = x[new_msb:new_lsb];
endmodule
| 7.92175 |
module addsub_f03aa9b11e (
input [(16 - 1):0] a,
input [(16 - 1):0] b,
output [(17 - 1):0] s,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] a_17_32;
wire signed [(16 - 1):0] b_17_35;
localparam signed [(17 - 1):0] const_value = 17'sb00000000000000000;
reg signed [(17 - 1):0]... | 6.587892 |
module xlcounter_limit_duc_16ch_341 (
ce,
clr,
clk,
op,
up,
en,
rst
);
parameter core_name0 = "";
parameter op_width = 5;
parameter op_arith = `xlSigned;
parameter cnt_63_48 = 0;
parameter cnt_47_32 = 0;
parameter cnt_31_16 = 0;
parameter cnt_15_0 = 0;
parameter count_limited... | 7.348679 |
module counter_5c8ee48e8f (
input [(1 - 1):0] rst,
output [(1 - 1):0] op,
input clk,
input ce,
input clr
);
wire rst_1_40;
reg [(1 - 1):0] count_reg_20_23 = 1'b0;
wire count_reg_20_23_rst;
localparam [(1 - 1):0] const_value = 1'b1;
localparam [(2 - 1):0] const_value_x_000000 = 2'b10;
loc... | 6.580178 |
module reinterpret_f67f49dab9 (
input [(19 - 1):0] input_port,
output [(19 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(19 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.913527 |
module constant_ca7488d888 (
output [(48 - 1):0] op,
input clk,
input ce,
input clr
);
assign op = 48'b000000000000000000000000000000001111111111111111;
endmodule
| 6.97083 |
module mux_f3921567cd (
input [(1 - 1):0] sel,
input [(16 - 1):0] d0,
input [(16 - 1):0] d1,
output [(16 - 1):0] y,
input clk,
input ce,
input clr
);
wire sel_1_20;
wire [(16 - 1):0] d0_1_24;
wire [(16 - 1):0] d1_1_27;
localparam [(16 - 1):0] const_value = 16'b0000000000000000;
reg... | 6.895298 |
module logical_06844c65fb (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(5 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
latency_pipe_5_26[1] = 1'b0;
latency_pipe_... | 7.341654 |
module logical_8641388092 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(1 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
end
wire latency_pipe_5_26_front_din;
wire l... | 7.741808 |
module logical_d5c14b9908 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(5 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
latency_pipe_5_26[1] = 1'b0;
latency_pipe_... | 7.126303 |
module xldpram_duc_16ch_341 (
dina,
addra,
wea,
a_ce,
a_clk,
rsta,
ena,
douta,
dinb,
addrb,
web,
b_ce,
b_clk,
rstb,
enb,
doutb
);
parameter core_name0 = "";
parameter c_width_a = 13;
parameter c_address_width_a = 4;
parameter c_width_b = 13;
para... | 7.043565 |
module reinterpret_84fa2b7df8 (
input [(48 - 1):0] input_port,
output [(48 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(48 - 1):0] input_port_1_40;
wire [(48 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module xlregister (
d,
rst,
en,
ce,
clk,
q
);
parameter d_width = 5;
parameter init_value = 'b0;
input [d_width-1:0] d;
input rst, en, ce, clk;
output [d_width-1:0] q;
wire internal_clr, internal_ce;
assign internal_clr = rst & ce;
assign internal_ce = ce & en;
synth_reg_w_i... | 6.610277 |
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