code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module reinterpret_8eee8341d8 (
input [(7 - 1):0] input_port,
output [(7 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(7 - 1):0] input_port_1_40;
wire signed [(7 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.738645 |
module reinterpret_fd8afbe046 (
input [(10 - 1):0] input_port,
output [(10 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(10 - 1):0] input_port_1_40;
wire signed [(10 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.913527 |
module reinterpret_feb184a5ad (
input [(8 - 1):0] input_port,
output [(8 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(8 - 1):0] input_port_1_40;
wire signed [(8 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.913527 |
module reinterpret_016d92ab20 (
input [(7 - 1):0] input_port,
output [(7 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(7 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 7.177582 |
module reinterpret_6200c8761b (
input [(15 - 1):0] input_port,
output [(15 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(15 - 1):0] input_port_1_40;
wire signed [(15 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.862502 |
module reinterpret_55833616ec (
input [(13 - 1):0] input_port,
output [(13 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(13 - 1):0] input_port_1_40;
wire signed [(13 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.920317 |
module reinterpret_87da68fdf8 (
input [(18 - 1):0] input_port,
output [(18 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(18 - 1):0] input_port_1_40;
wire signed [(18 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module reinterpret_81e883cd82 (
input [(9 - 1):0] input_port,
output [(9 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(9 - 1):0] input_port_1_40;
wire signed [(9 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.738645 |
module reinterpret_79f2a2c095 (
input [(17 - 1):0] input_port,
output [(17 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(17 - 1):0] input_port_1_40;
wire signed [(17 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.758648 |
module reinterpret_7fc77e4dea (
input [(11 - 1):0] input_port,
output [(11 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(11 - 1):0] input_port_1_40;
wire signed [(11 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.758648 |
module reinterpret_888f8372ca (
input [(19 - 1):0] input_port,
output [(19 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(19 - 1):0] input_port_1_40;
wire signed [(19 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module srl17e (
clk,
ce,
d,
q
);
parameter width = 16;
parameter latency = 8;
input clk, ce;
input [width-1:0] d;
output [width-1:0] q;
parameter signed [5:0] a = latency - 2;
wire [width - 1:0] #0.2 d_delayed;
wire [width - 1:0] srl16_out;
genvar i;
assign d_delayed = d;
generate
... | 6.671364 |
module synth_reg (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
parameter complete_num_srl17es = latency / 17;
parameter remaining_latency = latency % 17;
parameter temp_num_srl17es = (latency / 1... | 7.341053 |
module synth_reg_reg (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
wire [width - 1:0] o;
genvar idx;
reg [width - 1:0] reg_bank[latency:0];
integer j;
initial begin
for (j = 0; j < latenc... | 6.614179 |
module synth_reg_w_init (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 'b0000;
parameter latency = 1;
input [width - 1:0] i;
input ce, clr, clk;
output [width - 1:0] o;
wire [(latency + 1) * width - 1:0] dly_i;
wire #0.2... | 7.190939 |
module single_reg_w_init (
i,
ce,
clr,
clk,
o
);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 8'b00000000;
input [width - 1:0] i;
input ce;
input clr;
input clk;
output [width - 1:0] o;
parameter [0:0] init_index_val = (init_index == 1) ? 1'b1... | 8.407813 |
module cast (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 1;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
p... | 6.505444 |
module pad_lsb (
inp,
res
);
parameter signed [31:0] orig_width = 4;
parameter signed [31:0] new_width = 2;
input [orig_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] pad_pos = new_width - orig_width - 1;
wire [new_width-1:0] result;
genvar i;
assign res = result;
... | 6.592947 |
module zero_ext (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] new_width = 2;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
genvar i;
assign res = result;
generate
if (new_width >= old_width) begin : u0
assign ... | 6.922503 |
module align_input (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] delta = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] abs_delta = (delta... | 6.860388 |
module round_towards_inf (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [... | 6.669142 |
module round_towards_even (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input ... | 6.669142 |
module trunc (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - ... | 6.502157 |
module wrap_arith (
inp,
res
);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter sign... | 8.173074 |
module xldelay #(
parameter width = -1,
latency = -1,
reg_retiming = 0
) (
input [width-1:0] d,
input ce,
clk,
en,
output [width-1:0] q
);
generate
if ((latency == 0) || (reg_retiming == 0)) begin : srl_delay
synth_reg #(width, latency) reg1 (
.i (d),
.ce... | 7.291426 |
module mux_1f6c522247 (
input [(1 - 1):0] sel,
input [(16 - 1):0] d0,
input [(16 - 1):0] d1,
output [(16 - 1):0] y,
input clk,
input ce,
input clr
);
wire [ (1 - 1):0] sel_1_20;
wire [(16 - 1):0] d0_1_24;
wire [(16 - 1):0] d1_1_27;
localparam [(16 - 1):0] const_value = 16'b0000000000... | 6.937596 |
module constant_57097453ee (
output [(48 - 1):0] op,
input clk,
input ce,
input clr
);
localparam signed [(48 - 1):0] const_value = 48'sb000000000000000000000000000000000000111111111111;
assign op = 48'b000000000000000000000000000000000000111111111111;
endmodule
| 6.644297 |
module reinterpret_81b71e1f8b (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.738645 |
module reinterpret_0e0c011a4e (
input [(18 - 1):0] input_port,
output [(18 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(18 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 7.177582 |
module reinterpret_5668f8e576 (
input [(48 - 1):0] input_port,
output [(48 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(48 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.920317 |
module xldpram_dist (
dina,
addra,
wea,
ena,
a_ce,
a_clk,
douta,
addrb,
enb,
b_ce,
b_clk,
doutb
);
parameter core_name0 = "";
parameter addr_width = 12;
parameter c_width = 12;
parameter c_address_width = 4;
parameter latency = 1;
input [c_width-1:0] dina;
i... | 6.894075 |
module reinterpret_2824f666f2 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] input_port_1_40;
wire [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.534911 |
module reinterpret_dee95c6dbb (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(16 - 1):0] input_port_1_40;
wire signed [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.775554 |
module xlslice (
x,
y
);
parameter new_msb = 9;
parameter new_lsb = 1;
parameter x_width = 16;
parameter y_width = 8;
input [x_width-1:0] x;
output [y_width-1:0] y;
assign y = x[new_msb:new_lsb];
endmodule
| 7.92175 |
module counter_5c8ee48e8f (
input [(1 - 1):0] rst,
output [(1 - 1):0] op,
input clk,
input ce,
input clr
);
wire rst_1_40;
reg [(1 - 1):0] count_reg_20_23 = 1'b0;
wire count_reg_20_23_rst;
localparam [(1 - 1):0] const_value = 1'b1;
localparam [(2 - 1):0] const_value_x_000000 = 2'b10;
loc... | 6.580178 |
module addsub_f03aa9b11e (
input [(16 - 1):0] a,
input [(16 - 1):0] b,
output [(17 - 1):0] s,
input clk,
input ce,
input clr
);
wire signed [(16 - 1):0] a_17_32;
wire signed [(16 - 1):0] b_17_35;
localparam signed [(17 - 1):0] const_value = 17'sb00000000000000000;
reg signed [(17 - 1):0]... | 6.587892 |
module xlcounter_limit (
ce,
clr,
clk,
op,
up,
en,
rst
);
parameter core_name0 = "";
parameter op_width = 5;
parameter op_arith = `xlSigned;
parameter cnt_63_48 = 0;
parameter cnt_47_32 = 0;
parameter cnt_31_16 = 0;
parameter cnt_15_0 = 0;
parameter count_limited = 0;
inpu... | 7.348679 |
module reinterpret_f67f49dab9 (
input [(19 - 1):0] input_port,
output [(19 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(19 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 6.913527 |
module mux_f3921567cd (
input [(1 - 1):0] sel,
input [(16 - 1):0] d0,
input [(16 - 1):0] d1,
output [(16 - 1):0] y,
input clk,
input ce,
input clr
);
wire sel_1_20;
wire [(16 - 1):0] d0_1_24;
wire [(16 - 1):0] d1_1_27;
localparam [(16 - 1):0] const_value = 16'b0000000000000000;
reg... | 6.895298 |
module logical_06844c65fb (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(5 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
latency_pipe_5_26[1] = 1'b0;
latency_pipe_... | 7.341654 |
module logical_8641388092 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(1 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
end
wire latency_pipe_5_26_front_din;
wire l... | 7.741808 |
module logical_d5c14b9908 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr
);
wire d0_1_24;
wire d1_1_27;
reg latency_pipe_5_26[0:(5 - 1)];
initial begin
latency_pipe_5_26[0] = 1'b0;
latency_pipe_5_26[1] = 1'b0;
latency_pipe_... | 7.126303 |
module xldpram (
dina,
addra,
wea,
a_ce,
a_clk,
rsta,
ena,
douta,
dinb,
addrb,
web,
b_ce,
b_clk,
rstb,
enb,
doutb
);
parameter core_name0 = "";
parameter c_width_a = 13;
parameter c_address_width_a = 4;
parameter c_width_b = 13;
parameter c_addre... | 7.354143 |
module reinterpret_84fa2b7df8 (
input [(48 - 1):0] input_port,
output [(48 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire signed [(48 - 1):0] input_port_1_40;
wire [(48 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module xlregister (
d,
rst,
en,
ce,
clk,
q
);
parameter d_width = 5;
parameter init_value = 'b0;
input [d_width-1:0] d;
input rst, en, ce, clk;
output [d_width-1:0] q;
wire internal_clr, internal_ce;
assign internal_clr = rst & ce;
assign internal_ce = ce & en;
synth_reg_w_i... | 6.610277 |
module reinterpret_8eee8341d8 (
input [(7 - 1):0] input_port,
output [(7 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(7 - 1):0] input_port_1_40;
wire signed [(7 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.738645 |
module reinterpret_fd8afbe046 (
input [(10 - 1):0] input_port,
output [(10 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(10 - 1):0] input_port_1_40;
wire signed [(10 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.913527 |
module reinterpret_feb184a5ad (
input [(8 - 1):0] input_port,
output [(8 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(8 - 1):0] input_port_1_40;
wire signed [(8 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.913527 |
module reinterpret_016d92ab20 (
input [(7 - 1):0] input_port,
output [(7 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(7 - 1):0] input_port_1_40;
assign input_port_1_40 = input_port;
assign output_port = input_port_1_40;
endmodule
| 7.177582 |
module reinterpret_6200c8761b (
input [(15 - 1):0] input_port,
output [(15 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(15 - 1):0] input_port_1_40;
wire signed [(15 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.862502 |
module reinterpret_55833616ec (
input [(13 - 1):0] input_port,
output [(13 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(13 - 1):0] input_port_1_40;
wire signed [(13 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.920317 |
module reinterpret_87da68fdf8 (
input [(18 - 1):0] input_port,
output [(18 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(18 - 1):0] input_port_1_40;
wire signed [(18 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module reinterpret_81e883cd82 (
input [(9 - 1):0] input_port,
output [(9 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(9 - 1):0] input_port_1_40;
wire signed [(9 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40... | 6.738645 |
module reinterpret_79f2a2c095 (
input [(17 - 1):0] input_port,
output [(17 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(17 - 1):0] input_port_1_40;
wire signed [(17 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.758648 |
module reinterpret_7fc77e4dea (
input [(11 - 1):0] input_port,
output [(11 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(11 - 1):0] input_port_1_40;
wire signed [(11 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.758648 |
module reinterpret_888f8372ca (
input [(19 - 1):0] input_port,
output [(19 - 1):0] output_port,
input clk,
input ce,
input clr
);
wire [(19 - 1):0] input_port_1_40;
wire signed [(19 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_... | 6.738645 |
module duc_nco #(
parameter DATA_IN_WIDTH = 16,
parameter DATA_OUT_WIDTH = 16,
parameter FREQ_WIDTH = 32
) (
input clk_in,
input [FREQ_WIDTH-1:0] freq_in,
input freq_in_valid,
input [DATA_IN_WIDTH-1:0] data_in_I,
input [DATA_IN_WIDTH-1:0] data_in_Q,
input data_in_valid,
output [D... | 7.671979 |
module duc_nco_tb;
reg reset_n;
reg clk_in;
reg [31:0] freq_in;
reg freq_in_valid;
reg [15:0] data_in_I;
reg [15:0] data_in_Q;
reg data_in_valid;
wire [15:0] data_out;
wire data_out_valid;
duc_nco #(
.DATA_IN_WIDTH (16),
.DATA_OUT_WIDTH(16),
.FREQ_WIDTH (32)
) duc_nco_inst ... | 6.805317 |
module duc_top (
input clk_200m,
input cfg_rst,
input rx_dds_en,
input [31:0] loop_data,
output [15:0] loopdata_out_i,
output [15:0] loopdata_out_q
);
reg [27:0] dac_data_fcw;
always @(posedge clk_200m or posedge cfg_rst) begin
if (cfg_rst) begin
dac_data_fcw <= 28'd0;
... | 7.12023 |
module apb_dummy_top (
intr,
paddr,
pclk,
penable,
pprot,
prdata,
psel,
pwdata,
pwrite,
presetn
);
input [31:0] paddr;
input pclk;
input penable;
input [2 : 0] pprot;
input psel;
input [31:0] pwdata;
input pwrite;
input presetn;
output [31:0] prdata;
output in... | 7.183666 |
module dummy7;
`define ADDR1 16'h0011
`define ADDR2 16'h0022
`define ADDR81 8'h11
`define ADDR82 8'h22
reg [ 7:0] data1;
reg [ 7:0] data2;
reg [ 7:0] data3;
reg [ 7:0] data4;
reg [ 7:0] addr;
reg [15:0] addr16;
// use mod operator to convert literal to 8 bits - this works in verilogXL
always... | 7.672611 |
module MapController (
input [4:0] map_x,
input [4:0] map_y,
input [2:0] sprite_data_in,
output reg [2:0] sprite_data_out,
input readwrite,
input clock_50
);
wire [8:0] extended_map_x = {3'b000, map_x};
wire [8:0] extended_map_y = {3'b000, map_y};
wire [8:0] client_address;
assign cl... | 7.110401 |
module dummy_cache #(
parameter CORE = 0,
parameter DATA_WIDTH = 32,
parameter ADDRESS_BITS = 12,
parameter PROGRAM = "../software/applications/binaries/<your_program>",
parameter MISS_THRESHOLD = 3,
parameter HIT_THRESHOLD = 3
) (
input clock,
input reset,
input read,
input wr... | 7.106833 |
module NOR (
input A,
B,
output Z
);
endmodule
| 7.366253 |
module dummy_dev (
// Inputs
input clk_i
, input rst_i
, input [31:0] cfg_addr_i
, input [31:0] cfg_data_wr_i
, input cfg_stb_i
, input cfg_we_i
, input m2p_valid_i
, input [31:0] m2p_data_i
, input p2m_accept_i
// Outputs
, ou... | 6.637363 |
module filter #(
parameter order = 4
) (
input wire [23:0] i_sample,
input wire [(16*order-1):0] i_coefficients_flat,
input wire i_start,
input wire i_rst_n,
input wire i_clk,
output reg [41:0] o_result, // width = i_sample + i_coefficients + log2(order) [rounded upwards]
output reg o_r... | 7.200473 |
module dummy_fsl_client (
// Outputs
fsl_m_control,
fsl_m_data,
fsl_m_write,
fsl_s_read,
data_out,
// Inputs
gclk,
reset_l,
fsl_m_full,
fsl_s_exists,
fsl_s_control,
fsl_s_data,
//Dummy input
fsl_s_clk,
fsl_m_clk
);
//=============================... | 7.59831 |
module is a dummy master device used for testing the
// bus. This module is implemented by a request queue.
//DATE: 2020-10-16
//AUTHOR: Thimble Liu
module dummy_master(
clk, request, ready, grant, address, data, r_w
);
input clk, ready, grant;
output request, r_w;
output [... | 6.996298 |
module dummy_master_1 (
//This module is identical to dummy_master, but with different operations.
clk,
request,
ready,
grant,
address,
data,
r_w,
ready_inner
);
input clk, ready, grant;
output request, r_w, ready_inner;
output [31:0] address;
inout [31:0] data;
//dummy re... | 6.986608 |
module dummy_mc #(
parameter MC_RTNCTL_WIDTH = 32,
parameter RAM_DEPTH = 64
) (
input clk,
input mc_rq_vld,
input [ 2:0] mc_rq_cmd,
input [ 3:0] mc_rq_scmd,
input [ 47:0] mc_rq_va... | 8.720195 |
module d_mem (
input wire reset,
input wire oe,
input wire we,
input wire [15:0] addr,
inout wire [15:0] data_io
);
reg [15:0] data_out;
reg [15:0] mem[0:65535];
reg [15:0] i;
initial begin
data_out <= 16'b0;
for (i = 0; i < 2000; i = i + 1) begin
mem[i] <= 8'b0;
e... | 7.209086 |
module dummy_ntsc_capture (
input clk, // the main system clock
input clock_27mhz,
input reset, // reset line
output tv_in_reset_b, // these are all labkit wires
output tv_in_i2c_clock, // |
inout tv_in_i2c_data, // |
input tv_in_line_clock1, // |
input [19:0] tv_in_ycrcb, //... | 6.962796 |
module dummy_rom_fx55 (
input wire [11:0] read_address,
output reg [ 7:0] rom_out
);
always @* begin
case (read_address)
12'h200: rom_out <= 8'h60;
12'h201: rom_out <= 8'hEA;
12'h202: rom_out <= 8'h61;
12'h203: rom_out <= 8'hAC;
12'h204: rom_out <= 8'h62;
12'h205: ro... | 7.33184 |
module dummy_rx (
input clk,
input rst,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [13:0] adc_a,
input adc_ovf_a,
input [13:0] adc_b,
input adc_ovf_b,
output [31:0] sample,
input run,
output strobe
);
wire [15:0] scale_i, scale_q;
wire [31:0]... | 6.540035 |
module for dummy slave devices.
module dummy_slave_fast(
clk,address, data, request, ready_out, r_w,clr
);
input clk, r_w, request;
input [31:0] address;
inout [31:0] data;
output ready_out;
input clr;
//-------------------------- Module implementation -------------------------
//dummy... | 6.71688 |
module for dummy slave devices.
module dummy_slave_mid(
clk,address, data, request, ready_out, r_w
);
input clk, r_w, request;
input [31:0] address;
inout [31:0] data;
output ready_out;
//-------------------------- Module implementation -------------------------
//dummy memory
(* ram_i... | 6.71688 |
module Super_Mealy_FIR
#(
parameter nTap = 9,
parameter super_ratio = 4 //,
) (
input clock,
input reset,
input [(32*super_ratio) - 1: 0] din,
output [(32*super_ratio) - 1: 0] dout //,
);
reg [(32*super_ratio) -1: 0] drin;
reg [(32*(nTap-1) ) -1: 0] dst;
wire [(32*(nTap-1) ) -1: 0] stin [super_ratio:0];
... | 6.682692 |
module dummy_zbt_tb;
reg clock;
reg reset;
reg wr;
reg [`LOG_ADDR-1:0] addr;
reg [`LOG_MEM-1:0] write;
wire [`LOG_MEM-1:0] data;
dummy_zbt mem (
.clock(clock),
.reset(reset),
.wr(wr),
.addr(addr),
.write(write),
.data(data)
);
always #5 clock = !clock;
integ... | 6.615124 |
module dump ( /*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOINOUT*/
/*AUTOWIRE*/
/*AUTOREG*/
initial begin
`ifdef DUMP_FILE
$fsdbDumpfile(`DUMP_FILE);
`else
$fsdbDumpfile("./dump/dump.fsdb");
`endif
$fsdbDumpvars(0, TEST_TOP);
$fsdbDumpvars(0, TEST_TOP.xCMBUS);
$fsdbDumpvars(0, ... | 6.569403 |
module dump;
initial begin
$timeformat(-9, 2, "ns", 10); // -9 =ns 2=digits after .
end // initial begin
initial begin
$dumpfile("testdump.vcd");
$dumpvars(0, testbench);
$dumpon;
// // Use with signalscan (optional)
// //$recordvars("depth =3",netfpga_top);
//
e... | 6.671858 |
module dumpoff (
reset,
clk,
dumpoff
);
input clk;
input reset;
output dumpoff;
reg dumpoff;
reg [4:0] count;
always @(posedge clk) begin
if (!reset) begin
count <= 0;
dumpoff <= 0;
end else begin
if (count <= 21) begin
if (count == 1) begin
dumpo... | 7.313924 |
module dumpon (
reset,
clk,
dumpon
);
input clk;
input reset;
output dumpon;
reg dumpon;
reg [4:0] count;
always @(posedge clk) begin
if (!reset) begin
count <= 0;
dumpon <= 0;
end else begin
if (count <= 21) begin
if (count == 1) begin
dumpon <= 1... | 7.460493 |
module dumpvcd ();
// ======================================
// Dump Waves to VCD File
// ======================================
`ifdef AMBER_DUMP_VCD
initial begin
$display("VCD Dump enabled from %d to %d", (`AMBER_DUMP_START),
(`AMBER_DUMP_START + `AMBER_DUMP_LENGTH));
$dumpfile(`AMBER... | 6.961344 |
module DUMP_OFF (
rst_n,
state_start,
clk_sys,
dump_off
);
input rst_n;
input state_start;
input clk_sys;
output dump_off;
wire \off_on_coder_0_i_[1] , \off_on_coder_0_i_[0] ,
off_on_state_0_state_over, \off_on_timer_0_count_[4] ,
\off_on_timer_0_count_[3] , \off_on_timer_0_... | 7.716941 |
module DUMP_ON (
dump_on,
state_start,
rst_n,
clk_sys
);
output dump_on;
input state_start;
input rst_n;
input clk_sys;
wire \off_on_coder_0_i_[1] , \off_on_coder_0_i_[0] ,
off_on_state_0_state_over, \off_on_timer_0_count_[4] ,
\off_on_timer_0_count_[3] , \off_on_timer_0_cou... | 7.609114 |
module dump_sustain_timer (
clk_sys,
rst_n,
state_start,
start,
dump_sustain_data,
load,
clk_10k
);
input clk_sys;
input rst_n;
input state_start;
input [3:0] dump_sustain_data;
input load;
input clk_10k;
output start;
reg start;
reg [3:0] count;
reg [3:0] data;
wir... | 7.117797 |
module dump_sustain_timer_tb;
reg rst_n;
reg state_start;
reg clk_5k;
wire start;
initial begin
rst_n = 1'b0;
state_start = 1'b0;
clk_5k = 1'b0;
end
initial begin
#3 rst_n = 1'b1;
state_start = 1'b1;
end
always #1 clk_5k <= !clk_5k;
dump_sustain_timer dump_sustain_timer_0 ... | 7.117797 |
module dump_timer (
clk_sys,
rst_n,
state_start,
timer_start,
count
);
input clk_sys;
input rst_n;
input state_start;
input timer_start;
output [11:0] count;
reg [11:0] count;
wire en;
assign en = state_start & timer_start;
always @(posedge clk_sys) begin
if (rst_n == 1'b... | 6.508487 |
module DuneDataCompressibGp #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [11 : 0] din0,
input [11... | 7.441757 |
module DuneDataCompressibHp #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 7.441757 |
module DuneDataCompressibIp #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 7.441757 |
module DuneDataCompressibJp #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 7.441757 |
module DuneDataCompressibKp_DSP48_0 (
input [13 - 1:0] in0,
input [10 - 1:0] in1,
input [22 - 1:0] in2,
output [24 - 1:0] dout
);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in0);
... | 7.441757 |
module DuneDataCompressibKp (
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1... | 7.441757 |
module DuneDataCompressibLp_DSP48_1 (
input [13 - 1:0] in0,
input [10 - 1:0] in1,
input [21 - 1:0] in2,
output [24 - 1:0] dout
);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in0);
... | 7.441757 |
module DuneDataCompressibLp (
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1... | 7.441757 |
module DuneDataCompressibPq #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [63 : 0] din0,
input [63... | 7.441757 |
module DuneDataCompressionCore_BUS_A_s_axi_ram #(
parameter BYTES = 4,
DEPTH = 256,
AWIDTH = log2(DEPTH)
) (
input wire clk0,
input wire [ AWIDTH-1:0] address0,
input wire ce0,
input wire we0,
input wire [ BYTES-1:0] be0,
input wire [B... | 7.441757 |
module duration_counter (
input wire clk,
input wire reset,
input wire enable,
input wire [31:0] din,
output reg power_select
);
reg [31:0] counter;
// state machine
parameter [2:0] STATE_IDLE = 2'd0;
parameter [2:0] STATE_RUNNING = 2'd1;
parameter [2:0] STATE_DONE = 2'd2;
reg [2:0] s... | 7.423602 |
module music (
input sysclk, // tested with 25MHz
input [3:0] drum,
output reg [3:0] led,
output reg speaker, // connect to a speaker
output reg gain,
output reg shutdown
);
reg clk;
parameter [3:0] N = 4'd4;
reg drum1_ack = 1'd0;
reg drum2_ack = 1'd0;
reg drum3_ack = 1'd0;
reg d... | 7.115746 |
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