code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module music_ROM (
input clk,
input [7:0] address,
input [3:0] drum,
output reg [7:0] note
);
reg [ 3:0] drum_ack = 4'd0;
reg [ 3:0] drum1_count;
reg [15:0] delay = 16'd0;
reg [15:0] correction_count3 = 16'd0;
reg [15:0] correction_count4 = 16'd0;
//reg [2:0]count_drum1 = 3'd0;
always ... | 6.94161 |
module dut (
wb_master_if mast_if,
wb_slave_if slave_if
);
assign slave_if.CYC_I = mast_if.CYC_O;
assign slave_if.DAT_I = mast_if.DAT_O;
assign mast_if.DAT_I = slave_if.DAT_O;
assign mast_if.DAT_I = slave_if.DAT_O;
assign slave_if.TGD_I = mast_if.TGD_O;
assign mast_if.TGD_I = slave_if.T... | 7.230721 |
module dutmem0 (
clk,
rstn,
ce,
we,
addr,
din,
dout
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter DEPTH = (1 << AWIDTH);
input clk, rstn;
input ce, we;
input [AWIDTH-1:0] addr;
input [DWIDTH-1:0] din;
output [DWIDTH-1:0] dout;
reg [DWIDTH-1:0] do_r;
reg [... | 6.87361 |
module dutmem1 (
clk,
rstn,
ce,
we,
addr,
din,
dout
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter DEPTH = (1 << AWIDTH);
input clk, rstn;
input ce, we;
input [AWIDTH-1:0] addr;
input [DWIDTH-1:0] din;
output [DWIDTH-1:0] dout;
reg [DWIDTH-1:0] do_r;
reg [... | 6.756538 |
module dutmem2 (
clk,
rstn,
ce,
we,
addr,
din,
dout
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter DEPTH = (1 << AWIDTH);
input clk, rstn;
input ce, we;
input [AWIDTH-1:0] addr;
input [DWIDTH-1:0] din;
output [DWIDTH-1:0] dout;
reg [DWIDTH-1:0] do_r;
reg [... | 6.75241 |
module determines the duty cycle of the input
* signal and compares it against the desired duty cycle.
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
module duty_cycle_check (
/* duty cycle multiplied by 1000 (500 for 50 % in high) */
inpu... | 6.986217 |
module duty_cycle_check_tb ();
reg rst;
reg clk;
reg LOCKED;
wire fail;
reg [31:0] duty_cycle_1000;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 4;
duty_cycle_check dut (
.desired_duty_cycle_1000(`DESIRED_DUTY_CYCLE * 1000),... | 6.696864 |
module dut_Add_10Ux8U_10U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.561392 |
module dut_Add_10Ux8U_10U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.561392 |
module dut_Add_10Ux8U_11U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2;
input [7:0] in1;
output [10:0] out1;
wire [10:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.561392 |
module dut_Add_10Ux8U_11U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2;
input [7:0] in1;
output [10:0] out1;
wire [10:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.561392 |
module dut_Add_16Ux16U_17U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.048674 |
module dut_Add_16Ux16U_17U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.048674 |
module dut_Add_2U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.088478 |
module dut_Add_2U_2_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2, in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.372762 |
module dut_Add_32Ux16U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux16U_33U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux16U_33U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux17U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [16:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux17U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [16:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux17U_33U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [16:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux17U_33U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [16:0] in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.001621 |
module dut_Add_32Ux32U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.1678 |
module dut_Add_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.1678 |
module dut_Add_32Ux32U_33U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.1678 |
module dut_Add_32Ux32U_33U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [32:0] out1;
wire [32:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.1678 |
module dut_Add_3Sx2S_3S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + ({in1[1], in1});
assign out1 = asc001;
endmodule
| 6.78659 |
module dut_Add_3Sx2S_3S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + ({in1[1], in1});
assign out1 = asc001;
endmodule
| 6.78659 |
module dut_Add_3U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.398861 |
module dut_Add_3U_23_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.165957 |
module dut_Add_3U_8_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.177157 |
module dut_Add_4Sx2S_4S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = +(in2) + ({{2{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.993377 |
module dut_Add_4Sx2S_4S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = +(in2) + ({{2{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.993377 |
module dut_Add_4Sx2S_5S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [4:0] out1;
wire [4:0] asc001;
assign asc001 = +({in2[3], in2}) + ({{3{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.993377 |
module dut_Add_4Sx2S_5S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [4:0] out1;
wire [4:0] asc001;
assign asc001 = +({in2[3], in2}) + ({{3{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 6.993377 |
module dut_Add_4Ux2S_4S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = +(in2) + ({{2{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 7.031582 |
module dut_Add_4Ux2S_4S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = +(in2) + ({{2{in1[1]}}, in1});
assign out1 = asc001;
endmodule
| 7.031582 |
module dut_Add_4U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [3:0] in2, in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.172643 |
module dut_Add_5U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [4:0] in2, in1;
output [4:0] out1;
wire [4:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.160605 |
module dut_Add_6Ux1U_6U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input in1;
output [5:0] out1;
wire [5:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.899357 |
module dut_Add_6Ux1U_6U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input in1;
output [5:0] out1;
wire [5:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.899357 |
module dut_Add_6U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2, in1;
output [5:0] out1;
wire [5:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.09136 |
module dut_Add_7U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [6:0] in2, in1;
output [6:0] out1;
wire [6:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.09434 |
module dut_Add_8Ux8U_9U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2, in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.709135 |
module dut_Add_8Ux8U_9U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2, in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.709135 |
module dut_Add_9Ux8U_10U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [8:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.889107 |
module dut_Add_9Ux8U_10U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [8:0] in2;
input [7:0] in1;
output [9:0] out1;
wire [9:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.889107 |
module dut_And_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.348487 |
module dut_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.348487 |
module dut_And_1U_3_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.511486 |
module dut_And_1U_3_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.511486 |
module dut_DECODE_16U_3_4 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = 16'B0000000000000001 << in1;
assign out1 = asc001;
endmodule
| 6.702724 |
module dut_DECODE_16U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = 16'B0000000000000001 << in1;
assign out1 = asc001;
endmodule
| 6.702724 |
module dut_DECODE_32U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [4:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = 32'B00000000000000000000000000000001 << in1;
assign out1 = asc001;
endmodule
| 6.841833 |
module dut_DECODE_4U_25_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = 4'B0001 << in1;
assign out1 = asc001;
endmodule
| 7.386196 |
module dut_DECODE_4U_3_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = 4'B0001 << in1;
assign out1 = asc001;
endmodule
| 7.386196 |
module dut_DECODE_4U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;
assign asc001 = 4'B0001 << in1;
assign out1 = asc001;
endmodule
| 7.386196 |
module dut_Equal_1U_1_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.944842 |
module dut_Equal_1U_1_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.944842 |
module dut_Equal_1U_2_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.944842 |
module dut_Equal_1U_2_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.944842 |
module dut_Equal_6Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux4U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux4U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux5U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [4:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux5U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2;
input [4:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut_Equal_6Ux6U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [5:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.997801 |
module dut (
input a_signed,
b_signed,
input [17:0] a,
b,
output [35:0] z
);
MULT18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
.SIGNEDA(a_signed),
.SIGNEDB(b_signed),
.Z(... | 7.120761 |
module dut (
input a_signed,
b_signed,
input [17:0] a,
input [35:0] b,
output [53:0] z
);
MULT18X36 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
.SIGNEDA(a_signed),
.SIGNEDB(b_signe... | 7.120761 |
module dut (
input a_signed,
b_signed,
input [34:0] a,
input [29:0] b,
output [64:0] z
);
assign z = a * b;
endmodule
| 7.120761 |
module dut (
input a_signed,
b_signed,
input [35:0] a,
input [35:0] b,
output [71:0] z
);
MULT36X36 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
.SIGNEDA(a_signed),
.SIGNEDB(b_signe... | 7.120761 |
module dut (
input clk,
strobe,
input a_signed,
b_signed,
// using a vector here and reduce-and/oring reduces the probability of being reset/disabled
input [2:0] cea,
ceb,
rsta,
rstb,
input [2:0] ceout,
rstout,
input [35:0] a,
input [35:0] b,
output [71:0] z
);... | 7.120761 |
module dut (
input a_signed,
b_signed,
input [8:0] a,
b,
output [17:0] z
);
MULT9X9 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
.SIGNEDA(a_signed),
.SIGNEDB(b_signed),
.Z(z)
... | 7.120761 |
module dut (
input clk,
strobe,
input cea,
ceb,
rsta,
rstb,
input a_signed,
b_signed,
input [8:0] a,
b,
output [17:0] z
);
MULT9X9 #(
.REGINPUTA("REGISTER"),
.REGINPUTB("REGISTER"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.CLK(clk)... | 7.120761 |
module dut (
input clk,
strobe,
input ceout,
rstout,
input a_signed,
b_signed,
input [8:0] a,
b,
output [17:0] z
);
MULT9X9 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("REGISTER"),
.GSR("DISABLED")
) mult_i (
.CLK(clk),
.A(a),
... | 7.120761 |
module dut (
input is_signed,
addsub,
cin,
input [17:0] a,
b,
input [53:0] c,
output [53:0] z
);
MULTADDSUB18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGADDSUB("BYPASS"),
.REGLOADC("BYPASS"),
.REGLOADC2("BYPASS"),
... | 7.120761 |
module dut (
input clk,
strobe,
input [2:0] cepipe,
rstpipe,
cectrl,
rstctrl,
cec,
rstc,
cecin,
rstcin,
input is_signed,
addsub,
cin,
input [17:0] a,
b,
input [53:0] c,
output [53:0] z
);
MULTADDSUB18X18 #(
.REGINPUTA("BYPASS"),
.REGINPU... | 7.120761 |
module dut (
input clk,
strobe,
input ceout,
rstout,
input is_signed,
addsub,
cin,
input loadc,
input [17:0] a,
b,
input [53:0] c,
output [53:0] z
);
MULTADDSUB18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGADDSUB... | 7.120761 |
module dut (
input clk,
strobe,
input [2:0] cepipe,
rstpipe,
cectrl,
rstctrl,
cec,
rstc,
cecin,
rstcin,
input is_signed,
addsub,
cin,
input [17:0] a,
b,
input [53:0] c,
output [53:0] z
);
MULTADDSUB18X18 #(
.REGINPUTA("BYPASS"),
.REGINPU... | 7.120761 |
module dut (
input is_signed,
addsub,
cin,
input [35:0] a,
b,
input [107:0] c,
output [107:0] z
);
MULTADDSUB36X36 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGADDSUB("BYPASS"),
.REGLOADC("BYPASS"),
.REGLOADC2("BYPASS"),
... | 7.120761 |
module dut (
input clk,
strobe,
input [2:0] cepipe,
rstpipe,
cectrl,
rstctrl,
cec,
rstc,
cecin,
rstcin,
input is_signed,
addsub,
cin,
input [35:0] a,
b,
input [107:0] c,
output [107:0] z
);
MULTADDSUB36X36 #(
.REGINPUTA("BYPASS"),
.REGIN... | 7.120761 |
module dut (
input clk,
strobe,
input [2:0] cepipe,
rstpipe,
cectrl,
rstctrl,
cec,
rstc,
cecin,
rstcin,
input is_signed,
addsub,
cin,
input [35:0] a,
b,
input [107:0] c,
output [107:0] z
);
MULTADDSUB36X36 #(
.REGINPUTA("BYPASS"),
.REGIN... | 7.120761 |
module dut (
input [8:0] a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3,
input [3:0] addsub,
input is_signed,
input [53:0] c,
output [53:0] z
);
MULTADDSUB9X9WIDE #(
.REGINPUTAB0("BYPASS"),
.REGINPUTAB1("BYPASS"),
.REGINPUTAB2("BYPASS"),
.REGINPUTAB3("BYPASS"),
... | 7.120761 |
module dut (
input a_signed,
b_signed,
c_signed,
input [17:0] a,
b,
c,
output [35:0] z
);
MULTPREADD18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
... | 7.120761 |
module dut (
input clk,
strobe,
input a_signed,
b_signed,
c_signed,
input [17:0] a,
b,
c,
input rstc,
cec,
output [35:0] z
);
MULTPREADD18X18 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("REGISTER"),
.REGOUTPUT("BYPASS"),
.GSR("DI... | 7.120761 |
module dut (
input a_signed,
b_signed,
c_signed,
input [8:0] a,
b,
c,
output [17:0] z
);
MULTPREADD9X9 #(
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS"),
.GSR("DISABLED")
) mult_i (
.A(a),
.B(b),
.C(... | 7.120761 |
module dut_Mul_10Ux10U_20U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2, in1;
output [19:0] out1;
wire [19:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.737935 |
module dut_Mul_10Ux10U_20U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [9:0] in2, in1;
output [19:0] out1;
wire [19:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.737935 |
module dut_Mul_32Ux32U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.627662 |
module dut_Mul_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.627662 |
module dut_Mul_8Ux8U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.52871 |
module dut_Mul_8Ux8U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.52871 |
module dut_NotBit_1U_2_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.509906 |
module dut_NotBit_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.509906 |
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