code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dut_NotBit_1U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.509906 |
module dut_NotBit_1U_5_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.509906 |
module dut_Not_1U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.751715 |
module dut_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.751715 |
module dut_OrReduction_1U_3_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_OrReduction_1U_6_1 (
in1,
out1
); /* architecture "behavioural" */
input [5:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_OrReduction_1U_6_4 (
in1,
out1
); /* architecture "behavioural" */
input [5:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_OrReduction_2S_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_OrReduction_2S_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_OrReduction_6U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [5:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.73306 |
module dut_Or_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.528063 |
module dut_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.528063 |
module dut_Or_1U_0_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.248168 |
module dut_Or_1U_0_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.543789 |
module dut (
input [17:0] a,
output [17:0] z
);
assign z = a;
endmodule
| 7.120761 |
module dut_RAM_8X8_1 (
DIN,
CE,
RW,
in1,
out1,
clk
);
input [7:0] DIN;
input CE;
input RW;
input [2:0] in1;
input clk;
output [7:0] out1;
reg [7:0] out1;
reg [7:0] mem [7:0];
always @(posedge clk) begin : dut_RAM_8X8_1_thread_1
if (CE) begin
if (RW) begin
m... | 6.71248 |
module master (
input clk,
reset,
input [31:0] trans_data,
input ready,
output reg valid,
output reg [31:0] data,
output valid_var
);
reg state_m, nxt_state_m;
parameter idle_m = 0, valid_m = 1;
assign valid_var = !(trans_data == 32'b0);
always @(*) begin
case (state_m)
... | 7.034859 |
module slave (
input clk,
reset,
input valid,
input reg [31:0] data,
input valid_var,
input [31:0] s_data_fill,
output reg ready
);
wire ready_var, datapath_open;
reg [31:0] s_data;
reg state_s, nxt_state_s;
parameter busy_s = 0, ready_s = 1;
reg ready_var1;
reg valid_delay;
... | 7.264319 |
module master (
input clk,
reset,
input [31:0] trans_data,
input ready,
output reg valid,
output [31:0] data,
output valid_var
);
reg state_m, nxt_state_m;
parameter idle_m = 0, valid_m = 1;
assign data = trans_data;
assign valid_var = !(trans_data == 32'b0);
always @(*) begin
... | 7.034859 |
module slave (
input clk,
reset,
input valid,
input [31:0] data,
input valid_var,
output reg ready
);
wire ready_var, datapath_open;
reg [31:0] s_data;
reg state_s, nxt_state_s;
parameter busy_s = 0, ready_s = 1;
assign ready_var = (s_data == 0);
assign datapath_open = ready_var &&... | 7.264319 |
module cnt60 (
o_cnt60,
clk,
rst_n
);
output [5:0] o_cnt60;
input clk;
input rst_n;
reg [5:0] o_cnt60;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
o_cnt60 <= 6'd0;
end else begin
if (o_cnt60 >= 6'd59) begin
o_cnt60 <= 6'd0;
end else beg... | 7.719197 |
module nco (
o_gen_clk,
i_nco_num,
clk,
rst_n
);
output o_gen_clk; // 1Hz CLK
input [31:0] i_nco_num;
input clk; // 50Mhz CLK
input rst_n;
reg [31:0] cnt ;
reg o_gen_clk ;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= 32'd0;
o_gen_c... | 7.065527 |
module nco_cnt (
o_nco_cnt,
i_nco_num,
clk,
rst_n
);
output [5:0] o_nco_cnt;
input [31:0] i_nco_num;
input clk;
input rst_n;
wire gen_clk;
nco u_nco (
.o_gen_clk(gen_clk),
.i_nco_num(i_nco_num),
.clk(clk),
.rst_n(rst_n)
);
cnt60 u_cnt60 (
.o_cnt60(o_nco_... | 7.235482 |
module double_fig_sep (
o_left,
o_right,
i_double_fig
);
output [3:0] o_left;
output [3:0] o_right;
input [5:0] i_double_fig;
assign o_left = i_double_fig / 10;
assign o_right = i_double_fig % 10;
endmodule
| 6.726406 |
module top_nco_cnt_disp (
o_seg_enb,
o_seg_dp,
o_seg,
clk,
rst_n
);
output [5:0] o_seg_enb;
output o_seg_dp;
output [6:0] o_seg;
input clk;
input rst_n;
wire [ 5:0] o_nco_cnt_w;
wire [ 3:0] o_left_w;
wire [ 3:0] o_right_w;
wire [41:0] six_digit_seg;
wire [ 6:0] seg_left;
... | 6.689429 |
module dut_top (
clk,
nrst,
enable,
fifo_full,
fifo_wr_en,
dut_dout
);
parameter data_width = 16;
//parameter rom_depth_bits = 9;
parameter rom_depth_bits = 12;
localparam rom_depth = 2 ^ rom_depth_bits; //4096 words
parameter data_width_out = 40;
input clk, nrst;
input enable, ... | 6.995473 |
module dut_umi_fifo #(
parameter TARGET = "DEFAULT", // synthesis target
parameter MONITOR = 1, // turn on umi monitor
parameter NUMI = 1, // number of umi interfaces
parameter NCLK = 1, // number of clk pins
parameter NCTRL = 1, // number of ctrl pins
... | 7.117581 |
module dut_umi_fifo_flex #(
parameter TARGET = "DEFAULT", // synthesis target
parameter BYPASS = 0,
parameter MONITOR = 1, // turn on umi monitor
parameter NUMI = 1, // number of umi interfaces
parameter NCLK = 1, // number of clk pins
parameter NCTRL = 1, ... | 7.159695 |
module master (
input clk,
reset,
input [31:0] trans_data,
input ready,
output reg valid,
output [31:0] data,
output valid_var
);
reg state_m, nxt_state_m;
parameter idle_m = 0, valid_m = 1;
reg valid_var1;
reg [31:0] trans_data_var, trans_data_sync;
assign data = trans_data_sync... | 7.034859 |
module slave (
input clk,
reset,
input valid,
input reg [31:0] data,
input valid_var,
input [31:0] s_data_fill,
output reg ready
);
wire ready_var, datapath_open;
reg [31:0] s_data;
reg state_s, nxt_state_s;
parameter busy_s = 0, ready_s = 1;
reg ready_var1;
assign ready_var =... | 7.264319 |
module master (
input clk,
reset,
input [31:0] trans_data,
input ready,
output reg valid,
output [31:0] data,
output valid_var
);
reg state_m, nxt_state_m;
parameter idle_m = 0, valid_m = 1;
reg valid_var1;
reg [31:0] trans_data_var, trans_data_sync;
assign data = trans_data_sync... | 7.034859 |
module slave (
input clk,
reset,
input valid,
input [31:0] data,
input valid_var,
output reg ready
);
wire ready_var, datapath_open;
reg [31:0] s_data;
reg state_s, nxt_state_s;
parameter busy_s = 0, ready_s = 1;
assign ready_var = (s_data == 0);
assign datapath_open = ready_var &&... | 7.264319 |
module for the dut module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
*********************... | 6.534428 |
module dut_Xor_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) ^ (in1);
assign out1 = asc001;
endmodule
| 6.77286 |
module dut_Xor_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) ^ (in1);
assign out1 = asc001;
endmodule
| 6.77286 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f32m_sub (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_sub
s1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
s2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.641308 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module duv (
clk
, nreset
, sel
, in0
, in1
, out
);
input clk;
input nreset;
input sel;
input in0;
input in1;
output out;
reg q0;
reg mux_out;
wire out;
//wire mux_out;
wire d0;
//assign mux_out = sel ? in1 : in0;
always @(*) begin
case (sel)
0: mux_ou... | 6.577522 |
module DU_CU (
i_clk,
start,
data_input,
EQ,
LT,
GT,
out_A,
out_B,
p_STATE,
done,
Sub_out
);
input [`DATA_WID1-1:0] data_input;
input i_clk;
input start;
output done;
output [`DATA_WID1-1:0] out_A, out_B, Sub_out;
output EQ, LT, GT;
output [`WIDTH_STATE-1 : 0] p... | 7.193601 |
module dValidTag (
a,
d,
clk,
we,
spo
);
input [6 : 0] a;
input [0 : 0] d;
input clk;
input we;
output [0 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(7),
.C_DEFAULT_DATA("0"),
.C_DEPTH(128),
.C_FAMILY("virtex5"),
.C_HAS_CLK(... | 6.624595 |
module ldpc_muxreg #(
parameter LLRWIDTH = 4,
parameter NUMINPS = 4,
parameter MUXSIZE = 4,
parameter SELBITS = 2
) (
input clk,
input rst,
input [ SELBITS-1:0] sel,
input [NUMINPS*LLRWIDTH-1:0] din,
output [ LLRWIDTH-1:0] dout
);
// convert to 2-d array
wir... | 8.218031 |
module ldpc_ram_behav #(
parameter WIDTH = 4,
parameter LOG2DEPTH = 4
) (
input clk,
input we,
input [ WIDTH-1:0] din,
input [LOG2DEPTH-1:0] wraddr,
input [LOG2DEPTH-1:0] rdaddr,
output [ WIDTH-1:0] dout
);
reg [ WIDTH-1:0] storage [0... | 7.42255 |
module tmr0 (
input clk,
input clr,
input [31:0] din,
input ld,
input tmr_en,
output tmr_req,
output [31:0] cntr_o
);
reg [31:0] s_cntr;
reg [31:0] cntr;
assign cntr_o = cntr;
always @(posedge clk) if (ld) s_cntr <= din;
always @(posedge clk)
if (ld) cntr <= din;
else if (c... | 7.304298 |
module tmr_d (
input clr,
input clk,
input d,
output reg q
);
always @(posedge clk)
if (clr) q <= 0;
else q <= d | q;
endmodule
| 7.098953 |
module dvga_fifo64x32 (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full,
prog_empty,
prog_full
); // synthesis black_box
input clk;
input [31 : 0] din;
input rd_en;
input rst;
input wr_en;
output [31 : 0] dout;
output empty;
output full;
output prog_empty;
ou... | 6.671039 |
module dvga_sprite_post (
clk,
rst,
r_i,
g_i,
b_i,
hsync_i,
vsync_i,
blank_i,
r_o,
g_o,
b_o,
hsync_o,
vsync_o,
blank_o
);
input clk;
input rst;
input [7:0] r_i;
input [7:0] g_i;
input [7:0] b_i;
input hsync_i;
input vsync_i;
input blank_i;
out... | 7.410072 |
module dvga_sprite_pre (
clk,
rst,
xpos_i,
ypos_i,
xpos_o,
ypos_o,
r_i,
g_i,
b_i,
hsync_i,
vsync_i,
blank_i,
r_o,
g_o,
b_o,
hsync_o,
vsync_o,
blank_o
);
input clk;
input rst;
input [`XCNTW-1:0] xpos_i;
input [`YCNTW-1:0] ypos_i;
output... | 7.410072 |
module dvga_tb_wbs_master (
clk,
reset,
wb_adr_o,
wb_dat_o,
wb_dat_i,
wb_sel_o,
wb_we_o,
wb_stb_o,
wb_cyc_o,
wb_ack_i,
wb_err_i,
wb_cti_o,
wb_bte_o,
start
);
parameter baseaddr = 32'h0000_0000;
parameter outdelay = 10;
input clk;
input reset;
output [3... | 7.909668 |
module originally
// written by Sameer Puri. It is a verilog version
// with all HDMI logic removed, hard coded to
// 3 data channels and uses no vendor IP blocks. It
// also uses a 10x pixel to drive serialization rather
// than a 5x clock. It is expected the tmds and
// tmds_clock outputs will be passed to a differe... | 7.474321 |
module DVICoder (
input [7:0] blue,
input [7:0] green,
input [7:0] red,
input hsync,
input vsync,
input visible,
input pxclk,
input rst,
output [9:0] data0,
output [9:0] data1,
output [9:0] data2
);
TMDS_8b10b_enc channel0 (
.rst(rst),
.d (blue),
.c ({v... | 6.65141 |
module a_1DA_VINCI_TB;
// output list
wire [`ADDRESS_INDEX_LIMIT:0] ADDR;
wire READ, WRITE, CLK;
// inout list
wire [`DATA_INDEX_LIMIT:0] DATA_IN, DATA_OUT;
// reset
reg RST;
// Clock generator instance
CLK_GENERATOR clk_gen_inst (CLK);
// DA_VINCI v1.0 instance
defparam da_vinci_inst.mem_init_... | 6.760009 |
module dviTransmitter #(
parameter H_ACTIVE = 24,
parameter H_FRONT_PORCH = 2,
parameter H_SYNC = 8,
parameter H_BACK_PORCH = 4,
parameter H_TOTAL = H_ACTIVE + H_FRONT_PORCH + H_SYNC + H_BACK_PORCH,
parameter V_ACTIVE = 16,
parameter V_FRONT_PORCH = 2,
parameter V_SYNC = 4,
parameter... | 7.807026 |
module takes a half-rate bit clock (5x pixel clock) and drives a
// pseudodifferential pixel clock using DDR outputs.
module dvi_clock_driver (
input wire clk_x5,
input wire rst_n_x5,
output wire qp,
output wire qn
);
reg [9:0] ring_ctr;
always @ (posedge clk_x5 or negedge rst_n_x5) be... | 6.797335 |
module dvi_controller (
output [3:0] tmds,
output [3:0] tmdsb,
input [7:0] switches,
input clk_100mhz,
input reset
);
wire h_sync, v_sync, dataenable;
wire [9:0] r_enc;
wire [9:0] g_enc;
wire [9:0] b_enc;
wire pixel_clk1x, pixel_clk2x, pixel_clk10x;
wire serdesstrobe;
... | 7.327937 |
module for the DVI component
*
* Updated: 2012/02/12
*******************************************************************************/
`include "dvi_defines.v"
module dvi_controller_top(
input clk,
input enable,
input reset,
input [`COLOR_WIDTH-1:0] r,
input [`COLOR_WIDTH-1:0] g,
input [`COLOR... | 6.841726 |
module DVI_ENC (
input CK
, input XAR
, input CKE_i
, input [ 7 : 0] DAT_R_i
, input [ 7 : 0] DAT_G_i
, input [ 7 : 0] DAT_B_i
, input DE_i
, input HD_i
, input VD_i
, output [29 : 0] TMDS_o
);
wire [9 : 0] QQA_R... | 6.531074 |
module dvi_encoder (
input wire clkin, // pixel clock
input wire clkx2in, // pixel clock x2
input wire rstin, // reset
input wire [7:0] blue_din, // Blue data in
input wire [7:0] green_din, // Green data in
input wire [7:0] red_din, // Red data in... | 7.152342 |
module dvi_encoder_top (
input wire pclk, // pixel clock
input wire pclkx2, // pixel clock x2
input wire pclkx10, // pixel clock x2
input wire serdesstrobe, // OSERDES2 serdesstrobe
input wire rstin, // reset
input wire [7:0] blu... | 6.502728 |
module dvi_framebuffer_dp_ram (
// Inputs
input clk0_i
, input rst0_i
, input [ 8:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 8:0] addr1_i
, input [31:0] data1_i
, input wr1_i
// Outp... | 7.441372 |
module dvi_fb_psf_sys_timing (
// Inputs
input clk_i
, input rst_i
, input enable_i
// Mode
, input [9:0] display_res_x_i
, input [8:0] display_res_y_i
, input display_interlaced_i
, input display_pal_i
// 640x480 video timing
, input h_sync_i
, inp... | 6.977028 |
module dvi_framebuffer_fifo (
// Inputs
input clk_i
, input rst_i
, input [31:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [31:0] data_out_o
, output accept_o
, output valid_o
);
//----------------------------------... | 7.441372 |
module dvi_framebuffer_dp_ram (
// Inputs
input clk0_i
, input rst0_i
, input [ 9:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 9:0] addr1_i
, input [31:0] data1_i
, input wr1_i
// Outp... | 7.441372 |
module dvi (
// Inputs
input wire rst_i
, input wire clk_i
, input wire clk_x5_i
, input wire [7:0] vga_red_i
, input wire [7:0] vga_green_i
, input wire [7:0] vga_blue_i
, input wire vga_blank_i
, input wire vga_hsync_i
, input wire vga_vsyn... | 6.649615 |
module dvi_interface (
input gpu_clk0, // Pixel Clock
input dvi_clk0, // TFT Clock
input dvi_clk180, // TFT Clock 180 Phase
input dvi_clk315, // TFT Clock 315 Phase
input Rst, // TFT Reset
input hsync_in, // Hsync input
input... | 7.158648 |
module vga_logger #(
parameter C_COMPONENT_DEPTH = 8,
parameter C_FILE_NAME = "vga.txt"
) (
input wire pixel_clk,
input wire output_enable,
input wire [C_COMPONENT_DEPTH-1:0] red,
input wire [C_COMPONENT_DEPTH-1:0] green,
input wire [C_COMPONENT_DEPTH-1:0] blue,
input wire hsync,
inp... | 6.742606 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dvi_module(//Outputs
dvi_vs, dvi_hs, d... | 7.088073 |
module dvi_palette_mem #(
parameter W_ADDR = 8,
parameter W_DATA = 24
) (
input wire wclk,
input wire wen,
input wire [W_ADDR-1:0] waddr,
input wire [W_DATA-1:0] wdata,
input wire rclk,
input wire ren,
input wire [W_ADDR-1:0] ra... | 7.068678 |
module dvi_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------... | 6.783508 |
module dvi_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------... | 6.783508 |
module dvi_serialiser (
input clk_i
, input rst_i
, input strobe_i
, input [9:0] data_i
, output serial_p_o
, output serial_n_o
);
reg [1:0] data_p, data_n;
always @(posedge clk_i) data_p[0] <= data_i[0];
always @(posedge clk_i) data_n[0] <= ~data_i[0]... | 7.672078 |
module dvi_serialiser (
input wire clk_i
, input wire rst_i
, input wire strobe_i
, input wire [9:0] data_i
, output wire serial_o
);
`ifndef verilator
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE")
, .INIT(1'b0)
, .SRTYPE("ASYNC")
) u_ddr_r (
.C (clk... | 7.672078 |
module test;
reg tb_clk;
reg tb_button;
wire tb_spd;
wire tb_spc;
wire [11:0] tb_d;
wire tb_xclk_p;
wire tb_xclk_n;
wire tb_hsync;
wire tb_vsync;
wire tb_de;
wire tb_reset_n;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
dvi_top DUT (
.SYSCLK(tb_clk),
... | 6.990557 |
module dvi_timing (
input clk,
input rst,
output reg hs,
output reg vs,
output [10:0] x,
output [10:0] y,
output enable,
output [19:0] address
);
//ˮƽ
parameter H_FRONT = 40; //ǰ
parameter H_SYNC = 128; //ͬ
parameter H_BACK = 88; //
parameter H_ACT = 800; //Ч
parameter H... | 8.267565 |
module dvi_timing_controller (
output pixel_x,
output pixel_y,
output h_blank,
output v_blank,
output h_sync,
output v_sync,
output dataenable,
input pixel_clk,
input reset
);
reg [10:0] h_count;
reg [10:0] v_count;
assign h_blank = h_count > 800;
assign v_blank = v_count... | 6.52275 |
module dvi_tmds_encoder (
input clk
, input reset
, input [7:0] data
, input [1:0] c
, input blank
, output [9:0] encoded
);
/* verilator lint_off WIDTH */
/* verilator lint_off UNOPTFLAT */
reg [9:0] encoded_q;
wire [8:0] xored;
wire [8:0] xnored;
wire [3:... | 7.321811 |
module dvi_tmds_encoder (
input wire clk
, input wire reset
, input wire [7:0] data
, input wire [1:0] c
, input wire blank
, output wire [9:0] encoded
);
/* verilator lint_off WIDTH */
/* verilator lint_off UNOPTFLAT */
reg [9:0] encoded_q;
wire [8:0] xored;
... | 7.321811 |
module dvi_tx_clk_drv (
input pixel_clock,
output [1 : 0] tmds_clk
);
wire tmds_clk_pre;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_inst (
.Q (tmds_clk_pre),
.C (pixel_clock),
.CE(1),
.D1(1),
.D2(0),
.R (0),
... | 6.848181 |
module DVI_TX_Top (
I_rst_n,
I_serial_clk,
I_rgb_clk,
I_rgb_vs,
I_rgb_hs,
I_rgb_de,
I_rgb_r,
I_rgb_g,
I_rgb_b,
O_tmds_clk_p,
O_tmds_clk_n,
O_tmds_data_p,
O_tmds_data_n
);
input I_rst_n;
input I_serial_clk;
input I_rgb_clk;
input I_rgb_vs;
input I_rgb_hs;
i... | 6.653875 |
module dvi_tx_fixed_res (
// Clocks
p_clk_x1,
p_clk_x2,
p_clk_x10,
serdesstrobe,
// Reset
reset,
// Pixel coordinates
HPos,
VPos,
// Video data
red_data,
green_data,
blue_data,
//
active,
preload_vid_line,
h_sync,
// HDMI physical interface
... | 9.093389 |
module dvi_tx_parallel #(
// Defaults are for 640x480p 60 Hz (from CEA 861D).
// All horizontal timings are in pixels.
// All vertical timings are in scanlines.
parameter H_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter H_FRONT_PORCH = 16,
parameter H_SYNC_WIDTH = 96,
parame... | 9.214007 |
module dvi_tx_top (
input pixel_clock,
input ddr_bit_clock,
input reset,
input den,
input hsync,
input vsync,
input [23 : 0] pixel_data,
output [1 : 0] tmds_clk,
output [1 : 0] tmds_d0,
output [1 : 0] tmds_d1,
output [1 : 0] tmds_d2
);
wire [ 5 : 0] ctrl;
wir... | 6.921846 |
module dvp_controller #(
parameter DW = 16
) (
input wire pclk,
input wire aresetn,
input wire frame_en,
input wire [DW-1:0] data_pixel,
input wire [31:0] h_pad_left,
input wire [31:0] h_pad_right,
input wire [31:0] v_pad_up,
input wire [31:0] v_pad_down,
input wire [31:0] sync_w... | 8.123455 |
module dvp_rx_top (
input wire clk,
reset,
//CAM
input wire dvp_pclk,
dvp_href,
dvp_vsync,
dvp_orientation, //external pclk with freq constraint
input wire [11:0] dvp_din,
//VGA
input wire [11:0] sw,
input wire sw_test_mode,
output wire h... | 6.559958 |
module dvp_tb ();
reg pclk, aresetn, frame_en;
reg [15:0] data_pixel;
reg [31:0] frame_hfp, frame_hbp, frame_vfp, frame_vbp, video_h, video_v;
wire vsync, hsync, pixel_clk;
wire [15:0] data_bus;
initial begin
pclk = 0;
aresetn = 0;
frame_en = 0;
#200 aresetn = 1;
#2000 frame_en = 1;
e... | 6.501578 |
module dvp_to_ft #(
parameter IM_X = 1280,
parameter IM_Y = 720,
parameter COLOR_MODE = 2, // 1 - Grayscale, 2 - RGB565
parameter FPGA_PROCESSING = 2, // 1 - Convert RGB565 -> 8-bit Grayscale, 2 - No processing
parameter CAMERA_ADDR = 8'h78, // 8'h60 - OV2640, 8'h42 - OV7670, 8'h78 - OV5642
p... | 6.833833 |
module dvsdclaa_1v8 (
S,
Cout,
A,
B,
Cin
);
input wire [3:0] A, B;
input wire Cin;
wire [3:0] P, G, Car;
output [3:0] S;
output Cout;
assign P = A ^ B;
assign G = A & B;
assign Car[0] = G[0] || (P[0] & Cin);
assign Car[1] = G[1] || (P[1] & G[0]) || (P[1] & P[0] & Cin);
assign Ca... | 6.60465 |
module dvsd_pe (
en,
in,
eno,
gs,
out
);
input en; //Enable Input
input [7:0] in; //8 Input line
output eno, gs; //Enable outputs
output reg [2:0] out; //3 Output lines
wire _a_;
// Compiling enable outputs
assign _a_ = ~∈
assign eno = ~(_a_ & en);
assign gs = ~eno &... | 8.073091 |
module dv_ctrl_local ( /*AUTOARG*/
// Outputs
nreset,
clk1,
clk2,
start,
// Inputs
dut_active,
stim_done,
test_done
);
parameter CFG_CLK1_PERIOD = 10;
parameter CFG_CLK1_PHASE = CFG_CLK1_PERIOD / 2;
parameter CFG_CLK2_PERIOD = 100;
parameter CFG_CLK2_PHASE = CFG_CLK2_PERIOD... | 7.117701 |
module dv_driver #(
parameter N = 1, // "N" packets wide
parameter AW = 32, // address width
parameter PW = 104, // packet width (derived)
parameter IDW = 12, // id width
parameter NAME = "none", // north, south etc
parameter STIMS = 1, // number of stimul... | 6.70835 |
module dv_top ();
parameter DW = 64; // Memory width
parameter MAW = 15; // Memory address width
//regs/wires
reg [1023:0] filename;
wire [DW-1:0] ext_packet;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire nreset; // From dv_ctrl of dv_ctrl.v
wire s... | 6.676339 |
module dv_top ();
//static variables
parameter N = 1;
parameter IDW = 12;
parameter AW = 32;
parameter PW = 2 * AW + 40;
//local variables
integer r;
wire [ IDW-1:0] dv_coreid;
wire [ N*N-1:0] vdd;
wire vss;
wire clkout;
wire dut_acti... | 7.077271 |
module dv_top ();
//static variables
parameter TIMEOUT = 100;
parameter N = 1;
parameter IDW = 12;
parameter AW = 32;
parameter PW = 2 * AW + 40;
//local variables
integer r;
wire [ IDW-1:0] dv_coreid;
wire [ N*N-1:0] vdd;
wire vss;
wire clkout;
w... | 7.077271 |
module DW01_binenc(A, ADDR)/* synthesis syn_builtin_du = "weak" */;
parameter A_width = 32;
parameter ADDR_width = 6;
output [ADDR_width-1:0]ADDR;
input [A_width-1:0]A;
reg [ADDR_width-1:0]ADDR;
always @(A)
begin : local
integer i;
/* returns the value of the highest bit numb... | 6.66945 |
module DW01_bsh (
A,
SH,
B
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 8; //parameter for specifying the input A width
parameter SH_width = 3; //parameter for specifying the input SH width
input [A_width-1:0] A;
input [SH_width-1:0] SH;
output [A_width-1:0] B;
//internal... | 6.976498 |
module DW01_cmp6 (
A,
B,
TC,
LT,
GT,
EQ,
LE,
GE,
NE
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 16;
input [width - 1 : 0] A;
input [width - 1 : 0] B;
input TC;
output LT;
output GT;
output EQ;
output LE;
output GE;
output NE;
//Internal data... | 6.699863 |
module DW01_csa (
a,
b,
c,
ci,
carry,
sum,
co
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 14; //parameter specifying number of bits
//Input/output declaration
input [width - 1 : 0] a; //input line 1
input [width - 1 : 0] b; //input line 2
input [width - 1 : 0]... | 7.061906 |
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