code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DW01_inc (
A,
SUM
);
parameter width = 4;
// port list declaration in order
input [width-1 : 0] A;
output [width-1 : 0] SUM;
// synopsys translate_off
//-------------------------------------------------------------------------
// Parameter legality check
//---------------------------... | 6.679497 |
module DW01_inc (
A,
SUM
);
parameter width = 4;
// port list declaration in order
input [width-1 : 0] A;
output [width-1 : 0] SUM;
assign SUM = ((^(A ^ A) !== 1'b0)) ? {width{1'bx}} : A - {width{1'b1}};
endmodule
| 6.679497 |
module DW01_mux_any #(
parameter A_width = 512,
SEL_width = 8,
MUX_width = 2
) (
input [ A_width-1:0] A,
input [SEL_width-1:0] SEL,
output reg [MUX_width-1:0] MUX
) /* synthesis syn_builtin_du = "weak" */;
localparam MAX_inputs = (2 ** SEL_width);
integer i;
//wire [(MAX_inp... | 8.144669 |
module DW02_divide (
A,
B,
TC,
QUOTIENT,
DIVIDE_BY_0
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 14;
parameter B_width = 9;
parameter TC_mode = 1;
input [A_width - 1 : 0] A;
input TC;
input [B_width - 1:0] B;
output [A_width - 1 : 0] QUOTIENT;
output DIVIDE_BY_0... | 6.585571 |
module DW02_mac_async#(parameter A_width = 16,parameter B_width = 16)(
02 input clk, // 时钟
03 input rst_n, // 复位
04 input TC, // unsigned (TC = 0) or signed (TC = 1)
05 input [A_width - 1 : 0] A, // 乘法输入项A
06 input [B_width - 1 : 0] B, // 乘法输入项B
07 input [A_width + B_width - 1 : 0] C, // 累加项C
08 outpu... | 7.573569 |
module DW02_mac_top (
clk,
rstn,
in1,
in2,
out
);
input clk;
input rstn;
input [15:0] in1;
input [15:0] in2;
output [35:0] out;
wire [35:0] out_mac;
DW02_mac #(16, 16) U1 (
.A (in1),
.B (in2),
.C (out[31:0]),
.TC (1'b1),
.MAC(out_mac[31:0])
);
re... | 7.467288 |
module DW02_mult (
A,
B,
TC,
PRODUCT
);
parameter A_width = 8;
parameter B_width = 16;
/********* Internal parameter *************/
parameter width = A_width + B_width;
/*****************************************/
input [A_width - 1 : 0] A;
input [B_width - 1 : 0] B;
input TC;
output... | 6.692305 |
module DW02_multp (
a,
b,
tc,
out0,
out1
);
// parameters
parameter a_width = 8;
parameter b_width = 8;
parameter out_width = 18;
parameter verif_en = 1; // verif_en ignored by synthesis
localparam upperhalf = out_width / 2;
localparam lowerhalf = out_width - (out_width / 2);
/... | 6.623389 |
module DW02_sin (
A, //Angle in Binary
SIN //Sine value of A
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 16;
parameter sin_width = 32;
//Input/output declaration
input [A_width - 1 : 0] A;
output [sin_width - 1 : 0] SIN;
//Internal signal declaration
wire [sin_width - 1:0... | 6.852967 |
module DW02_sincos (
A, //Angle in Binary
SIN_COS, //Sine (SIN_COS=0) or cosine(SIN_COS=1)
WAVE //Sine or Cosine value of A
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 16;
parameter wave_width = 32;
//Input/output declaration
input [A_width - 1 : 0] A;
input SIN_COS;
o... | 6.867202 |
module DW03_BICTR_DCNTO (
clk,
rst,
load,
cen,
up_dn,
data,
count_to,
count,
tercnt
);
parameter width = 4;
input clk;
input rst;
input load;
input cen;
input up_dn;
input [width-1:0] data;
input [width-1:0] count_to;
output [width-1:0] count;
output tercnt;
... | 6.880183 |
module DW03_BICTR_DCNTO_TB ();
parameter width = 4;
reg clk;
reg rst;
reg load;
reg cen;
reg up_dn;
reg [width-1:0] count_to;
reg [width-1:0] data;
wire tercnt;
wire [width-1:0] count;
always #5 clk <= ~clk;
init... | 6.880183 |
module DW03_bictr_decode #(
parameter WIDTH = 'd8 // numar de biti ai numaratorului
) (
input clk, // semnal de ceas
input rst_n, // semnal de reset asincron, activ low
input count_up_dwn,
input cen,
input ... | 8.400786 |
module DW03_bictr_decode_tb #(
parameter WIDTH = 'd8 // numar de biti ai numaratorului
) (
input clk, // semnal de ceas
input rst_n,
output reg cen, // semnal de reset asincron, activ low
output reg count_up_dwn, ... | 8.400786 |
module DW03_bictr_decode_test;
localparam WIDTH = 'd8; // numar de biti ai numaratorului
wire clk; // semnal de ceas
wire rst_n; // semnal de reset asincron, activ low
wire count_up_dwn; // comanda de numarare, activa high
wire load;
wire ... | 8.400786 |
module DW03_bictr_scnto (
data, //Counter load input
up_dn, //High for count up and low for count down
load, //Enable data load to counter, active low
cen, //Count enable, active high
clk, //Clock
reset, //Counter reset, active low
count, //Output count bus
tercnt //Terminal coun... | 6.667168 |
module DW03_pipe_reg (
A,
clk,
B
) /* synthesis syn_builtin_du = "weak" */;
parameter depth = 8;
parameter width = 8;
input [width - 1 : 0] A;
input clk;
output [width - 1 : 0] B;
//reg [width - 1 : 0] B;
reg [width - 1 : 0] temp[depth - 1 : 0];
integer i;
/*
always @(posedge clk)
beg... | 7.452097 |
module DW03_reg_s_pl (
d,
clk,
reset_N,
enable,
q
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
parameter reset_value = 0;
parameter set_value = (width >= 32) ? 0 : reset_value;
//Input/output declaration
input clk;
input [width - 1 : 0] d;
input enable;
input r... | 6.596238 |
module DW03_shftreg (
clk,
s_in,
p_in,
shift_n,
load_n,
p_out
) /* synthesis syn_builtin_du = "weak" */;
parameter length = 6;
//Input/output declaration
input clk;
input s_in;
input [length - 1 : 0] p_in;
input shift_n;
input load_n;
output [length - 1 : 0] p_out;
//Signal ... | 7.093376 |
module DW03_UPDN_CTR (
data,
up_dn,
load,
cen,
clk,
rst,
count,
tercnt
);
parameter width = 4;
input [width-1:0] data;
input up_dn;
input load;
input cen;
input clk;
input rst;
output [width-1:0] count;
output tercnt;
reg [width-1:0] count_intern;
always @(posed... | 7.477631 |
module DW03_UPDN_CTR_TB ();
parameter width = 4;
reg clk;
reg rst;
reg load;
reg cen;
reg up_dn;
reg [width-1:0] data;
wire tercnt;
wire [width-1:0] count;
always #5 clk = ~clk;
initial begin
clk = 0;
rst ... | 7.477631 |
module DW04_par_gen (
datain,
parity
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 16;
parameter par_type = 0;
//Input/output declaration
input [width -1 : 0] datain;
output parity;
wire temp = ^(datain);
wire parity = par_type ? temp : ~temp;
endmodule
| 7.018653 |
module DW04_shad_reg (
datain,
sys_clk,
shad_clk,
reset,
SI,
SE,
sys_out,
shad_out,
SO
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
parameter bld_shad_reg = 1;
//Input/output declaration
input [width - 1 : 0] datain;
input SI;
input SE;
input sys_c... | 6.504141 |
module dw2pw_reorder_addr_gen (
input clk_calc,
input dw_stride,
input [25:0] base_addr,
// input [10:0] channel ,
input [ 6:0] co_div16,
input [14:0] co_div16_pic,
// input [18:0] channel_pic ,
input [ 2:0] cnt_1,
input [ 6:0] col_c... | 6.558941 |
module
// (up with async reset, count_enable, load and
// terminal count outputs) (Verilog version)
//
// MODIFICATION HISTORY:
// L.Rieder 05.06.96 Verilog version with fixed width
// of 8 created
// Bala Needamangalam May 20,1998 Changed the structural GTECH based
// des... | 7.423624 |
module DW8051_updn_ctr (
data,
up_dn,
load,
cen,
clk,
reset,
count,
tercnt
);
parameter width = 16;
input [(width-1):0] data;
input up_dn;
input load;
input cen;
input clk;
input reset;
output [(width-1):0] count;
output tercnt;
//-----------------------------------... | 7.091926 |
module (up with sync.clear)
//
// MODIFICATION HISTORY:
// L.Rieder 29.05.96 Verilog version for fixed width of 2
// created
//
// Gina Ngo 11.20.96 Fixed star 38722: added header
// Bala Needamangalam
// May 20 98 Converted GTECH instantiatio... | 7.272591 |
module DWC_DownConv_Hold_Reg_Rd (
// Inputs
ACLK,
sysReset,
DWC_DownConv_hold_data_in,
DWC_DownConv_hold_fifo_empty,
DWC_DownConv_hold_get_next_data,
// Outputs
DWC_DownConv_hold_fifo_rd_en,
DWC_DownConv_hold_data_out,
DWC_DownConv_hold_reg_empty,
// Decoded outputs
m... | 7.593337 |
module DWC_DownConv_Hold_Reg_Wr (
// Inputs
ACLK,
sysReset,
DWC_DownConv_hold_data_in,
DWC_DownConv_hold_fifo_empty,
DWC_DownConv_hold_get_next_data,
// Outputs
DWC_DownConv_hold_fifo_rd_en,
DWC_DownConv_hold_data_out,
DWC_DownConv_hold_reg_empty,
// Decoded outputs
s... | 7.593337 |
module for DWC_gmac
//
// DesignWare IP ID: ac263890
//
////////////////////////////////////////////////////////////////////////////////
module DWC_gmac_bcm22 (
clk_s,
rst_s_n,
init_s_n,
event_s,
clk_d,
rst_d_n,
init_d_n,
event_d,
test
)... | 8.127587 |
module DWC_gmac_bus_synczr (
clk_s,
rst_s_n,
init_s_n,
data_s,
ack_s,
clk_d,
rst_d_n,
init_d_n,
data_d,
ack_d,
test
);
parameter WIDTH = 2;
parameter F_SYNC_TYPE = 2; // RANGE 0 to 3
parameter TST_MODE = 0; // RANGE 0 to 2
parameter VERIF_EN = 1; // RANGE 0 to 2... | 8.083642 |
module looks
// for any change in the card_detect signals and filters any
// card insertion/removal de-bounces associated with it and
// generate one interrupt to the host.
// The host should keep a copy of previous card_detect status and
// on rec... | 7.986364 |
module DWC_mobile_storage_clkmux_interleave (
//Outputs
cdata_out_int,
//Input
toggle,
cdata_out_1,
ddr
);
//ouput
output [`NUM_CARD_BUS*8-1:0] cdata_out_int;
//Input
input [`NUM_CARD_BUS-1:0] toggle;
input [`NUM_CARD_BUS*8-1:0] cdata_out_1;
input ddr;
//Wire
reg [ `NUM_CARD... | 7.841514 |
module DWC_mobile_storage_clk_and (
/*AUTOARG*/
// Outputs
Y,
// Inputs
A,
B
);
// --------------------------------------
// Input and Output Port Declaration
// --------------------------------------
// Clocks
input A; // Clock0 input
input B; // Clock1 input
output Y; // cl... | 7.841514 |
module DWC_mobile_storage_clk_mux_2x1 (
/*AUTOARG*/
// Outputs
out_clk,
// Inputs
in0_clk,
in1_clk,
clk_sel
);
// --------------------------------------
// Input and Output Port Declaration
// --------------------------------------
// Clocks
input in0_clk; // Clock0 input
inpu... | 7.841514 |
module DWC_mobile_storage_clk_mux_4x1 (
/*AUTOARG*/
// Outputs
out_clk,
// Inputs
in0_clk,
in1_clk,
in2_clk,
in3_clk,
clk_sel
);
// --------------------------------------
// Input and Output Port Declaration
// --------------------------------------
// Clocks
input in0_cl... | 7.841514 |
module DWC_mobile_storage_clk_or (
/*AUTOARG*/
// Outputs
Y,
// Inputs
A,
B
);
// --------------------------------------
// Input and Output Port Declaration
// --------------------------------------
// Clocks
input A; // Clock0 input
input B; // Clock1 input
output Y; // clo... | 7.841514 |
module DWC_mobile_storage_crc7 (
/*AUTOARG*/
// Outputs
serial_crc,
// Inputs
cclk_in,
cclk_in_en,
creset_n,
start_crc,
send_serial_crc,
din
);
// --------------------------------------
// Input and Output Port Declaration
// --------------------------------------
input ... | 7.841514 |
module DWC_mobile_storage_dmac_if (
// Outputs
prdata_muxed_o,
push1_o,
pop1_o,
fifo_din1_o,
// Inputs
use_internal_dmac_i,
biu_fifo_pop_i,
biu_fifo_push_i,
biu_fifo_wdata_i,
prdata_i,
dmac_csr_sel_i,
dmac_csr_rdata_i,
dmac_fifo_pop_i,
dmac_fifo_push_i,
d... | 7.841514 |
module handles the B channel signals within the up converter.
// It instantiates two modules:
// - FIFO storing the useful information of the address phase (i.e. whether
// the current transaction is split into multiple ones or not)
// - B response control assigns the master B response chann... | 7.873189 |
module DWC_UpConv_WChan_Hold_Reg #(
parameter DATA_WIDTH_IN = 32,
parameter USER_WIDTH = 32,
parameter DATA_WIDTH_OUT = 32
) (
input wire clk,
input wire rst,
input wire DWC_UpConv_hold_fifo_empty,
input wire DWC_UpConv_hold_get_next_data,
output wire DWC_UpConv_hold_fifo_rd_en, // ... | 8.279041 |
module DWF_absval #(
parameter N = 8
) (
input [N-1:0] opa,
output [N-1:0] opb
);
function [N-1:0] cal;
input [N-1:0] A;
begin
cal = (^(A ^ A) !== 1'b0) ? ({N{1'bx}}) : ((A[N-1] == 1'b1) ? (~A + 1'b1) : A);
end
endfunction
assign opb = cal(opa);
endmodule
| 7.721188 |
module dwt4db (
input clk,
rst,
input signed [15:0] x,
output clk2,
output signed [15:0] a,
d
);
// Declaracao de fios auxiliares
wire signed [15:0] x0, x1;
// Declaracao dos registros z^(-1) expandidos
reg signed [23:0] z01, z02, z03, z04, z11, z12, z13, z14, z15, z16;
// componen... | 8.103282 |
module for DWbb
//
// DesignWare IP ID: 84d7966e
//
////////////////////////////////////////////////////////////////////////////////
`include "DW_amba_constants.v"
`include "DW_ahb_cc_constants.v"
`include "DW_ahb_constants.v"
module DW_ahb_bcm01 (
// Inputs
a,
tc,
min_max,
// Outputs
value,
index
)... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: 6909e2df
//
////////////////////////////////////////////////////////////////////////////////
`include "DW_amba_constants.v"
`include "DW_ahb_cc_constants.v"
`include "DW_ahb_constants.v"
module DW_ahb_bcm02(
a,
sel,
mux
);
parameter A_WIDTH = 8; // width of input... | 6.850609 |
module DW_ahb_dfltslv (
hclk,
hresetn,
hready,
htrans,
hsel_none,
hready_resp_none,
hresp_none,
hrdata_none
);
// physical parameters
parameter ahb_data_width = `AHB_DATA_WIDTH; // 32, 64, 128, 256
input hclk;
input hresetn;
input hready;
input [`HTRANS_WIDTH-1:0] htrans;
... | 10.417875 |
module controls which source wins.
-- =====================================================================
*/
`include "DW_amba_constants.v"
`include "DW_ahb_cc_constants.v"
`include "DW_ahb_constants.v"
module DW_ahb_gating (
wten,
grant,
grant_3t,
parked,
parked_3t,
grant_2t,
parked_2t
);
input ... | 8.016281 |
module
//
//
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
module i_uart_DW_apb_async_rst_gen
(
// Inputs
clk,
async_rst1,
async_rst2,
scan_mode,
// Outputs
new_async_rst_n
)... | 9.610936 |
module for DWbb
//
// DesignWare IP ID: 3f96e4ae
//
////////////////////////////////////////////////////////////////////////////////
module i_uart_DW_apb_uart_bcm41 (
clk_d,
rst_d_n,
init_d_n,
data_s,
test,
data_d
);
parameter WIDTH = 1; // RANGE 1 to 1024
parameter RST_VAL =... | 6.850609 |
module for the DW_apb_uart
// macro-cell.
//
//
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
module i_uart_DW_apb_uart_rst
(
// Inputs
presetn,
scan_mode,
// Outputs
new_pr... | 9.491665 |
module for DWbb
//
// DesignWare IP ID: 84d7966e
//
////////////////////////////////////////////////////////////////////////////////
module DW_axi_bcm01 (
// Inputs
a,
tc,
min_max,
// Outputs
value,
index
);
parameter WIDTH = 4; // element WIDTH
parameter NUM_INPUTS = 8; // number of elements i... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: e2f0bec1
//
////////////////////////////////////////////////////////////////////////////////
module DW_axi_bcm57 (
clk,
rst_n,
init_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
);
parameter DATA_WIDTH = 4; // RANGE 1 to 256
parameter DEPTH = 8; // RA... | 6.850609 |
module DW_axi_busdemux (
sel,
din,
dout
);
parameter BUS_COUNT = 2; // Number of input buses.
parameter MUX_WIDTH = 3; // Bit width of data buses.
parameter SEL_WIDTH = 1; // Width of select line.
input [SEL_WIDTH-1:0] sel; // Select signal.
input [MUX_WIDTH-1:0] din; // Input bus.
wire ... | 8.10348 |
module would be able to mux three 12-bit buses, or
** seven 5-bit buses, or any other combination,
** depending on the parameter values used when the
** module is instantiated.
**
** ---------------------------------------------------------------------
*/
module DW_axi_busmux ( sel, d... | 8.634706 |
module would be able to mux three 12-bit buses, or
-- seven 5-bit buses, or any other combination,
-- depending on the parameter values used when the
-- module is instantiated.
--
-- Modification History:
-- Date By Version Change Description
-... | 8.634706 |
module for DW_axi
//
// DesignWare IP ID: 5bf0f11f
//
////////////////////////////////////////////////////////////////////////////////
//VCS coverage exclude_file
module DW_axi_fifo_s1_sf
(clk, rst_n, init_n, push_req_n, pop_req_n, diag_n, data_in, empty,
nxt_empty, almost_empty, half_full, almost_full, f... | 7.674989 |
module for DWbb
//
// DesignWare IP ID: e2f0bec1
//
////////////////////////////////////////////////////////////////////////////////
module DW_axi_gm_bcm57 (
clk,
rst_n,
init_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
);
parameter DATA_WIDTH = 4; // RANGE 1 to 256
parameter DEPTH = 8; //... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: 15e30698
//
////////////////////////////////////////////////////////////////////////////////
module DW_axi_gm_bcm65
(clk, rst_n, init_n, push_req_n, pop_req_n, diag_n, data_in, empty,
almost_empty, half_full, almost_full, full, error, data_out
);
parameter WIDTH ... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: e2f0bec1
//
////////////////////////////////////////////////////////////////////////////////
module g512_DW_axi_gs_bcm57 (
clk,
rst_n,
init_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
);
parameter DATA_WIDTH = 4; // RANGE 1 to 256
parameter DEPTH = 8... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: 15e30698
//
////////////////////////////////////////////////////////////////////////////////
module g512_DW_axi_gs_bcm65
(clk, rst_n, init_n, push_req_n, pop_req_n, diag_n, data_in, empty,
almost_empty, half_full, almost_full, full, error, data_out
);
parameter WI... | 6.850609 |
module g512_DW_axi_gs_fifo (
// Global
clk, // Clock, positive edge
clk_en, // Clock enable for quasi-synchronous clocking mode
rst_n, // Reset, active low
// Source Interface
src_data, // Input data
src_vld, // Source indicates valid input data is available
src_rdy, // FIFO indi... | 6.607351 |
module g512_DW_axi_gs_tl (
// Outputs
active_trans,
// Inputs
aclk,
aresetn,
gclken,
awvalid,
awready,
bvalid,
bready,
arvalid,
arready,
rvalid,
rlast,
rready
);
output active_trans;
// AXI INTERFACE
// Global
input aclk;
input aresetn;
input gcl... | 6.607351 |
module DW_axi_lockdec (
// Inputs.
bus_awpayload_i,
bus_arpayload_i,
// Outputs.
bus_awlocktx_o,
bus_arlocktx_o
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
//----------------------------------------------------------------------
parameter NUM_VIS... | 6.887544 |
module DW_axi_lp (
aclk_i,
aresetn_i,
awpendtrans_i,
arpendtrans_i,
awvalid_m_i,
arvalid_m_i,
csysreq_i,
csysack_o,
cactive_o,
ready_en_o
);
input aclk_i; // AXI system clock
input aresetn_i; // AXI system reset
input [`AXI_NUM_MASTERS-1:0] awpendtrans_i; // Num... | 8.528083 |
module DW_axi_lpfsm (
// Outputs
cactive,
csysack,
ready,
// Inputs
aclk,
aresetn,
active_trans,
csysreq
);
// -------------------------------------------------------------------
// Parameters
// -------------------------------------------------------------------
parameter ... | 7.129775 |
module DW_axi_mca_reqhold (
// Inputs - System.
aclk_i,
aresetn_i,
// Inputs - Payload source.
bus_req_i,
bus_prior_i,
// Inputs - Multi cycle arbitration control.
new_req_i,
// Outputs - Channel arbiter.
bus_req_o,
bus_prior_o
);
//-------------------------------------... | 6.598666 |
module DW_axi_mp_tzone (
// Inputs.
slvnum_i,
prot_i,
bus_secure_i,
// Outputs.
slvnum_o
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
//----------------------------------------------------------------------
parameter NUM_VIS_SP = 16;... | 8.7146 |
module
** which can implement a parameterisable number of
** busmuxes.
**
** ---------------------------------------------------------------------
*/
module DW_axi_multibusmux ( sel, din, dout );
parameter BUS_COUNT = 2; // Number of input buses.
parameter MUX_WIDTH = 3; // Bit widt... | 7.890496 |
module to count outstanding transactions.
module DW_axi_sp_addrch_tx_cnt (
clk_i,
resetn_i,
tx_acc_i,
tx_cpl_i,
cnt_max_o,
cnt_nz_o
);
parameter CNT_W = 1; // Count width.
parameter CNT_MAX = 1; // Count max.
parameter REG_OUTPUT = 1; // Registered or combinatorial output.
input clk_i;
input res... | 7.424899 |
module for DWbb
//
// DesignWare IP ID: e2f0bec1
//
////////////////////////////////////////////////////////////////////////////////
module x32_DW_axi_x2p_bcm57 (
clk,
rst_n,
init_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
);
parameter DATA_WIDTH = 4; // RANGE 1 to 256
parameter DEPTH = 8... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: e2f0bec1
//
////////////////////////////////////////////////////////////////////////////////
module x128_DW_axi_x2x_bcm57 (
clk,
rst_n,
init_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
);
parameter DATA_WIDTH = 4; // RANGE 1 to 256
parameter DEPTH = ... | 6.850609 |
module for DWbb
//
// DesignWare IP ID: 15e30698
//
////////////////////////////////////////////////////////////////////////////////
module x128_DW_axi_x2x_bcm65
(clk, rst_n, init_n, push_req_n, pop_req_n, diag_n, data_in, empty,
almost_empty, half_full, almost_full, full, error, data_out
);
parameter W... | 6.850609 |
module x512_DW_axi_x2x_busdemux (
sel,
din,
dout
);
parameter BUS_COUNT = 2; // Number of input buses.
parameter MUX_WIDTH = 3; // Bit width of data buses.
parameter SEL_WIDTH = 1; // Width of select line.
input [SEL_WIDTH-1:0] sel; // Select signal.
input [MUX_WIDTH-1:0] din; // Input bus... | 7.870553 |
module would be able to mux three 12-bit buses, or
** seven 5-bit buses, or any other combination,
** depending on the parameter values used when the
** module is instantiated.
**
** ---------------------------------------------------------------------
*/
module DW_axi_x2x_busmux ( se... | 8.634706 |
module would be able to mux three 12-bit buses, or
-- seven 5-bit buses, or any other combination,
-- depending on the parameter values used when the
-- module is instantiated.
--
-- Modification History:
-- Date By Version Change Description
-... | 8.634706 |
module for DW_axi_x2x
//
// DesignWare IP ID: 5bf0f11f
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Edited version of BCM module for DW_axi_x2x project.
//
// - Addition of the nxt_empty output. Pre registered version of empty
// signal
//
///////////////////////////... | 6.964016 |
module DW_bc_1 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.157954 |
module DW_bc_10 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary s... | 6.951484 |
module DW_bc_2 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.869814 |
module DW_bc_3 (
capture_clk, //Clocks data into the capture stage
capture_en, //Enable for data clocked into the capture stage, active low
shift_dr, //Enables the boundary scan chain to shift data one stage
//toward its serial output (tdo)
mode, //Determines whether data_out is contr... | 7.758565 |
module DW_bc_4 (
capture_clk, //Clocks data into the capture stage
capture_en, //Enable for data clocked into the capture stage, active low
shift_dr, //Enables the boundary scan chain to shift data one stage
//toward its serial output (tdo)
si, //Serial path from the previous boundary... | 7.47776 |
module DW_bc_5 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.155949 |
module DW_bc_7 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.766308 |
module DW_bc_8 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.812951 |
module DW_bc_9 (
capture_clk, //Clocks data into the capture stage
update_clk, //Clocks data into the update stage
capture_en, //Enable for data clocked into the capture stage, active low
update_en, //Enable for data clocked into the update stage, active high
shift_dr, //Enables the boundary sc... | 7.902531 |
module DW_bin2gray (
b,
g
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
input [width - 1:0] b;
output [width - 1:0] g;
wire [width - 1:0] g = (width == 1) ? b : bin2gray(b);
// Function to convert binary to gray code
function [width-1:0] bin2gray;
input [width-1:0] bin;
... | 6.725423 |
module DW_cntr_gray (
clk,
rst_n,
init_n,
load_n,
data,
cen,
count
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8; //parameter for specifying the register width
//Input/output declaration
input clk; //clock input
input rst_n; //Reset, async. active low
input in... | 6.939573 |
module DW_data_sync_na (
clk_s,
rst_s_n,
init_s_n,
send_s,
data_s,
clk_d,
rst_d_n,
init_d_n,
test,
data_avail_d,
data_d
// Embedded dc_shell script
// _model_constraint_1
);
parameter width = 8; // RANGE 1 to 1024
parameter f_sync_type = 2; // RANGE 0 to 4
pa... | 7.69143 |
module DW_decode_en (
en,
a,
b
);
parameter width = 3;
// declaration of inputs and outputs
input en;
input [width-1:0] a;
output [(1 << width)-1:0] b;
// synopsys translate_off
//-------------------------------------------------------------------------
// Parameter legality check
//----... | 6.575987 |
module DW_div_rem (
a,
b,
tc,
quotient,
divide_by_0,
remainder
) /* synthesis syn_builtin_du = "weak" */;
parameter a_width = 14;
parameter b_width = 9;
parameter tc_mode = 1;
input [a_width - 1 : 0] a;
input tc;
input [b_width - 1:0] b;
output [a_width - 1 : 0] quotient;
outp... | 7.435214 |
module DW_fifo_s1_df (
clk,
rst_n,
push_req_n,
pop_req_n,
diag_n,
ae_level,
af_thresh,
data_in,
empty,
almost_empty,
half_full,
almost_full,
full,
error,
data_out
);
//Parameter declaration
parameter width = 8;
parameter depth = 4;
parameter err_mode ... | 6.622761 |
module DW_fifo_s1_sf (
clk,
rst_n,
push_req_n,
pop_req_n,
diag_n,
data_in,
empty,
almost_empty,
half_full,
almost_full,
full,
error,
data_out
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
parameter depth = 4;
parameter ae_level = 1;
paramet... | 6.568707 |
module DW_fp_add_DG (
a,
b,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23;
parameter exp_width = 8;
parameter ieee_compliance = 0;
// declaration of inputs and outputs
input [sig_width + exp_width:0] a, b;
input [3:0] rnd;
input DG_ctrl;
output [sig_width + exp_width:0] z;... | 6.735324 |
module DW_FP_ALIGN (
// ports
a,
sh,
b,
stk
// Embedded dc_shell script
// _model_constraint_1
// set_attribute current_design "enable_dp_opt" "TRUE" -type "boolean" -quiet
);
//----------------------------------------------------------------------------
// main module parameters
... | 7.782535 |
module DW_fp_div_DG (
a,
b,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23; // range 2 to 253
parameter exp_width = 8; // range 3 to 31
parameter ieee_compliance = 0; // range 0 to 1
parameter faithful_round = 0; // range 0 to 1
input [sig_width + exp_width:0] a;
input [sig... | 7.336344 |
module DW_fp_ifp_conv (
a,
z
// Embedded dc_shell script
// _model_constraint_1
// set_attribute current_design "enable_dp_opt" "TRUE" -type "boolean" -quiet
);
parameter sig_widthi = 23; // RANGE 2 to 253 bits
parameter exp_widthi = 8; // RANGE 3 to 31 bits
parameter sig_widtho = 25; //... | 6.956171 |
module DW_fp_recip_DG (
a,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23; // range 2 to 253
parameter exp_width = 8; // range 3 to 31
parameter ieee_compliance = 0; // range 0 to 1
parameter faithful_round = 0; // range 0 to 1
input [sig_width + exp_width:0] a;
input [2:0] rnd... | 7.40677 |
module DW_fp_sub_DG (
a,
b,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23;
parameter exp_width = 8;
parameter ieee_compliance = 0;
// declaration of inputs and outputs
input [sig_width + exp_width:0] a, b;
input [3:0] rnd;
input DG_ctrl;
output [sig_width + exp_width:0] z;... | 6.985328 |
module DW_fp_sum3_DG (
a,
b,
c,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23; // RANGE 2 to 253 bits
parameter exp_width = 8; // RANGE 3 to 31 bits
parameter ieee_compliance = 0; // RANGE 0 or 1
parameter arch_type = 0; // RANGE 0 or 1
// declarati... | 7.25176 |
module DW_gray2bin (
g,
b
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
input [width-1:0] g;
output [width-1:0] b;
wire [width - 1:0] b = (width == 1) ? g : gray2bin(g);
// Function to convert gray code to binary
function [width - 1:0] gray2bin;
input [width - 1:0] gray;
... | 6.629593 |
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