code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DW_lbsh (
A, //Input data
SH, //Shift control
SH_TC, //Shift two's complement control, 0 - unsigned, 1 - signed
B //Shifted data out
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 49; //Word length of A and B
parameter SH_width = 6; //Word length SH
/******** Inter... | 6.778699 |
module DW_lod (
a,
dec,
enc
);
parameter a_width = 8;
localparam addr_width = ((a_width>65536)?((a_width>16777216)?((a_width>268435456)?((a_width>536870912)?30:29):((a_width>67108864)?((a_width>134217728)?28:27):((a_width>33554432)?26:25))):((a_width>1048576)?((a_width>4194304)?((a_width>8388608)?24:2... | 6.527034 |
module DW_lp_cntr_updn_df (
clk,
rst_n,
enable,
up_dn,
ld_n,
ld_count,
term_val,
count,
term_count_n
);
parameter width = 8;
parameter rst_mode = 0;
parameter reg_trmcnt = 0;
input clk;
input rst_n;
input enable;
input up_dn;
input ld_n;
input [width-1 : 0] ld_co... | 7.077775 |
module DW_lp_cntr_up_df (
clk,
rst_n,
enable,
ld_n,
ld_count,
term_val,
count,
term_count_n
);
parameter width = 8;
parameter rst_mode = 0;
parameter reg_trmcnt = 0;
input clk;
input rst_n;
input enable;
input ld_n;
input [width-1 : 0] ld_count;
input [width-1 : 0] t... | 7.077775 |
module DW_lp_fp_multifunc_DG (
a,
func,
rnd,
DG_ctrl,
z,
status
);
parameter sig_width = 23; // RANGE 2 to 23
parameter exp_width = 8; // RANGE 3 to 8
parameter ieee_compliance = 0; // RANGE 0 to 1
parameter func_select = 127; // RANGE 1 to 127
parameter faithful_round = 1; // RA... | 7.39475 |
module DW_lp_multifunc_DG (
a,
func,
DG_ctrl,
z,
status
);
parameter op_width = 24;
parameter func_select = 127;
input [op_width : 0] a;
input [15 : 0] func;
input DG_ctrl;
output [op_width+1 : 0] z;
output status;
// synopsys translate_off
wire [op_width+1 : 0] z_temp;
wire... | 7.490689 |
module DW_lsd (
a,
dec,
enc
);
parameter a_width = 8;
localparam addr_width = ((a_width>65536)?((a_width>16777216)?((a_width>268435456)?((a_width>536870912)?30:29):((a_width>67108864)?((a_width>134217728)?28:27):((a_width>33554432)?26:25))):((a_width>1048576)?((a_width>4194304)?((a_width>8388608)?24:2... | 7.668349 |
module works under
// some basic conditions:
// 1. B is subtracted from A, and the result is expected to have 2
// or more zeros. The case when only 1 zero happens, will require
// normalization.
// 2. The output is maximum when the vector should have all its bit... | 7.583099 |
module DW_lzd (
a,
dec,
enc
) /* synthesis syn_builtin_du = "weak" */;
parameter a_width = 32;
parameter size = (clogb2((a_width - 1) / 2)) + 2;
//Input/output declaration
input [a_width-1:0] a;
output [a_width-1:0] dec;
output [size-1:0] enc;
//Internal signal declaration
reg [a_widt... | 7.596877 |
module min_unsigned (
a,
value,
index
);
parameter width = 8;
parameter num_inputs = 2;
input [num_inputs*width-1 : 0] a;
output [width-1 : 0] value;
output index;
wire [width-1 : 0] a_high;
assign a_high = a >> width;
assign value = a_high < a[width-1 : 0] ? a_high : a[width-1 : 0];
... | 7.610739 |
module min_signed (
a,
value,
index
);
parameter width = 8;
parameter num_inputs = 2;
input [num_inputs*width-1 : 0] a;
output [width-1 : 0] value;
output index;
wire [width-1 : 0] a_high;
wire [width-1 : 0] a_signH;
wire [width-1 : 0] a_signL;
wire [width-1 : 0] value_tmp;
assign ... | 8.049551 |
module max_unsigned (
a,
value,
index
);
parameter width = 8;
parameter num_inputs = 2;
input [num_inputs*width-1 : 0] a;
output [width-1 : 0] value;
output index;
wire [width-1 : 0] a_high;
assign a_high = a >> width;
assign value = ((a_high > a[width-1 : 0])|| (a_high == a[width-1 : 0])... | 6.851933 |
module max_signed (
a,
value,
index
);
parameter width = 3;
parameter num_inputs = 4;
input [num_inputs*width-1 : 0] a;
output [width-1 : 0] value;
output index;
wire [width-1 : 0] a_high;
wire [width-1 : 0] a_signH;
wire [width-1 : 0] a_signL;
wire [width-1 : 0] value_tmp;
assign a... | 7.597457 |
module DW_mult_tc (
a,
b,
product
);
// parameters
parameter a_width = 8;
parameter b_width = 8;
//-----------------------------------------------------------------------------
// ports
input [a_width-1 : 0] a;
input [b_width-1 : 0] b;
output [a_width+b_width-1:0] product;
wire signed... | 7.150833 |
module DW_mult_uns (
a,
b,
product
);
// parameters
parameter a_width = 8;
parameter b_width = 8;
//-----------------------------------------------------------------------------
// ports
input [a_width-1 : 0] a;
input [b_width-1 : 0] b;
output [a_width+b_width-1:0] product;
assign pro... | 8.149006 |
module for positive fractional input.
// The fixed-point input format is a = (a0.a1 a2 a3 a4... a(a_width-1), where ai represents a bit.
// Input a has 1 integer bit and a_width-1 fractional bits. The normalization process consists in
// shifting the input vector a to the left until the output bit-vector has a 1 in th... | 6.560268 |
module DW_observ_dgen (
OBIN,
CLK,
TDGO
);
input OBIN;
input CLK;
output TDGO;
reg TDGO;
always @(posedge CLK) begin
TDGO <= OBIN;
end
endmodule
| 8.180886 |
module DW_pl_reg (
clk,
rst_n,
enable,
data_in,
data_out
// set_ungroup current_design
// if ( find("cell", "data_pipe*") ) {
// set_transform_for_retiming find( "cell", "data_pipe*" ) multiclass
// }
// if ( find("cell", "in_reg*") ) {
// set_dont_retime find("cell", "in... | 7.038079 |
module DW_pricod (
a,
cod,
zero
);
parameter a_width = 8;
input [a_width-1:0] a;
output [a_width-1:0] cod;
output zero;
// include modeling functions
`include "DW_pricod_function.inc"
// synopsys translate_off
//-------------------------------------------------------------------------
... | 6.746178 |
module DW_pulse_sync (
clk_s,
rst_s_n,
init_s_n,
event_s,
clk_d,
rst_d_n,
init_d_n,
event_d,
test
// Embedded dc_shell script
// _model_constraint_1
);
parameter reg_event = 1; // RANGE 0 to 1
parameter f_sync_type = 2; // RANGE 0 to 4
parameter tst_mode = 0; // R... | 7.503837 |
module DW_ram_2r_w_a_dff (
rst_n,
cs_n,
wr_n,
test_mode,
test_clk,
rd1_addr,
rd2_addr,
wr_addr,
data_in,
data_rd1_out,
data_rd2_out
);
parameter data_width = 4; // RANGE 1 to 256
parameter depth = 8; // RANGE 2 to 256
parameter rst_mode = 0; // RANGE 0 to 1
local... | 8.271641 |
module DW_ram_2r_w_s_dff (
clk,
rst_n,
cs_n,
wr_n,
rd1_addr,
rd2_addr,
wr_addr,
data_in,
data_rd1_out,
data_rd2_out
// synopsys dc_tcl_script_begin
// set ::suppress_errors [concat $::suppress_errors {EQN-10}]
// set save_suppress_dwbb_ram_2r_w_s_dff [lminus $::suppr... | 7.347142 |
module DW_ram_fifo (
clk,
rst_n,
push_req_n,
pop_req_n,
diag_n,
data_in,
empty,
almost_empty,
half_full,
almost_full,
full,
error,
data_out
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
parameter depth = 4;
parameter ae_level = 1;
parameter... | 6.747848 |
module DW_ram_rw_a_dff (
rst_n,
cs_n,
wr_n,
test_mode,
test_clk,
rw_addr,
data_in,
data_out
);
parameter data_width = 4; // RANGE 1 to 256
parameter depth = 8; // RANGE 2 to 256
parameter rst_mode = 0; // RANGE 0 to 1
localparam DW_addr_width = ((depth>256)?((depth>4096)?((d... | 9.187394 |
module DW_ram_rw_s_dff (
clk,
rst_n,
cs_n,
wr_n,
data_in,
rw_addr,
data_out
// synopsys dc_tcl_script_begin
// set ::suppress_errors [concat $::suppress_errors {EQN-10}]
// set save_suppress_dwbb_ram_rw_s_dff [lminus $::suppress_errors {EQN-10}]
// set ::suppress_errors {VHD... | 7.682522 |
module DW_ram_rw_s_lat (
clk,
cs_n,
wr_n,
rw_addr,
data_in,
data_out
) /* synthesis syn_builtin_du = "weak" */;
parameter data_width = 8;
parameter depth = 16;
`define _synp_dep depth
// +* `include "inc_file.inc"
//$Header: ///map510rc/designware/inc_file.inc#1 $
//--------------... | 7.357382 |
module DW_ram_r_w_a_dff (
rst_n,
wr_n,
cs_n,
test_mode,
test_clk,
rd_addr,
wr_addr,
data_in,
data_out
);
parameter data_width = 4; // RANGE 1 to 256
parameter depth = 8; // RANGE 2 to 256
parameter rst_mode = 1; // RANGE 0 to 1
localparam DW_addr_width = ((depth>256)?((d... | 9.112937 |
module DW_ram_r_w_s (
clk,
rst_n,
cs_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
// synopsys dc_tcl_script_begin
// set ::suppress_errors [concat $::suppress_errors {EQN-10}]
// set save_suppress_dwbb_ram_r_w_s_dff [lminus $::suppress_errors {EQN-10}]
// set ::suppress_... | 7.580587 |
module DW_ram_r_w_s_dff (
clk,
rst_n,
cs_n,
wr_n,
data_in,
wr_addr,
rd_addr,
data_out
// synopsys dc_tcl_script_begin
// set ::suppress_errors [concat $::suppress_errors {EQN-10}]
// set save_suppress_dwbb_ram_r_w_s_dff [lminus $::suppress_errors {EQN-10}]
// set ::suppr... | 7.160511 |
module DW_ram_r_w_s_lat (
clk, //Clock
cs_n, //Chip select, active low
wr_n, //Write enable, active low
rd_addr, //Read address bus
wr_addr, //Write address bus
data_in, //Input data bus
data_out //Output data bus
) /* synthesis syn_buil... | 7.160511 |
module DW_rash (
A, //Input data
DATA_TC, //Data two's complement control 0 - unsigned, 1 - signed
SH, //Shift control
SH_TC, //Shift two's complement control 0 - unsigned, 1 - signed
B //Output data
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 256; //Word length of A and... | 7.14114 |
module DW_square (
a,
tc,
square
) /* synthesis syn_builtin_du = "weak" */;
parameter width = 8;
//Input/output declaration
input [width - 1 : 0] a;
input tc;
output [(2 * width) - 1 : 0] square;
//Signal declaration
reg [width - 1 : 0] temp_a;
//Generate square value
assign square = t... | 6.578821 |
module DW_squarep (
a,
tc,
out0,
out1
);
// parameters
parameter width = 8;
parameter verif_en = 1; // verif_en ignored by synthesis
//-----------------------------------------------------------------------------
// ports
input [width-1 : 0] a;
input tc;
output [2*width-1:0] out0, o... | 7.140701 |
module DW_stack (
clk, //Input clock
rst_n, //Reset input, active LOW
push_req_n, //Stack push request, active LOW
pop_req_n, //Stack pop request, active LOW
data_in, //Stack push data
empty, //Stack empty flag, active HIGH
full, //Stack full flag, active HIGH
error, //Stack erro... | 6.97233 |
module DW_tap (
tck,
trst_n,
tms,
tdi,
so,
bypass_sel,
sentinel_val,
clock_dr,
shift_dr,
update_dr,
tdo,
tdo_en,
tap_state,
extest,
samp_load,
instructions,
sync_capture_en,
sync_update_dr,
test
);
parameter width = 2;
parameter id = 0;
... | 7.927804 |
module DW_thermdec (
en,
a,
b
);
parameter width = 3;
// declaration of inputs and outputs
input en;
input [width-1:0] a;
output [(1 << width)-1:0] b;
// synopsys translate_off
//-------------------------------------------------------------------------
// Parameter legality check
//-----... | 6.719995 |
module DW_ver_mod (
A,
B,
TC,
MODULUS
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 14;
parameter B_width = 9;
parameter TC_mode = 1;
input [A_width - 1 : 0] A; //Dividend
input TC; //Two's Complement Control
input [B_width - 1:0] B; //Divisor ... | 6.638399 |
module DW_wc_d1_s (
shift_clk,
rst_n,
set_n,
shift_en,
capture_en,
safe_control,
safe_value,
cti,
cfi,
cfo,
cto,
toggle_state
);
parameter rst_mode = 0;
input shift_clk;
input rst_n;
input set_n;
input shift_en;
input capture_en;
input safe_control;
inp... | 6.904049 |
module DW_wc_s1_s (
shift_clk,
rst_n,
set_n,
shift_en,
capture_en,
safe_control,
safe_value,
cti,
cfi,
cfo,
cfo_n,
cto,
toggle_state
);
parameter rst_mode = 0;
input shift_clk;
input rst_n;
input set_n;
input shift_en;
input capture_en;
input safe_co... | 6.836319 |
module DX (
instrIn,
PCin,
rsIn,
rtIn,
rtrdIn,
rsOut,
rtOut,
rtrdOut,
instrOut,
PCout,
clock,
enable,
clear
);
input clock, enable, clear;
input [4:0] rtrdIn;
input [31:0] PCin;
input [31:0] instrIn, rsIn, rtIn;
output [4:0] rtrdOut;
output [31:0] PCout;
... | 7.412713 |
module dxm_ff (
clk,
rst_n,
d,
q
);
`include "cc_params.inc"
`ifdef DX_INTERNAL_ENV
`define SIM_CDC
`define DXM_DFF_HOLD 0.5
`define DXM_DFF_SETUP 1
`endif
input clk, rst_n;
input d;
output q;
reg q;
always @(posedge clk or negedge rst_n)
if (~rst_n) q <= 1'b0;
else q <= #1 d;... | 6.61014 |
module dxm_interrupt_low (
rst_n,
clk,
r_din,
clr_status_1p,
events_1p,
mask,
status,
int_req
);
parameter VEC_W = 8;
parameter DO_PRINT = 1;
`include "cc_params.inc"
input rst_n;
input clk;
input [VEC_W-1:0] r_din;
input clr_status_1p;
input [VEC_W-1:0] events_1p;
inpu... | 7.262785 |
module dxm_mux (
in_low,
in_high,
control,
out
);
parameter mux_width = 1;
`include "cc_params.inc"
input control;
input [mux_width-1:0] in_low;
input [mux_width-1:0] in_high;
output [mux_width-1:0] out;
assign out = control ? in_high : in_low;
endmodule
| 8.101775 |
module dxm_mux_clk (
in_low,
in_high,
control,
out
);
parameter mux_width = 1;
`include "cc_params.inc"
input control;
input [mux_width-1:0] in_low;
input [mux_width-1:0] in_high;
output [mux_width-1:0] out;
assign out = control ? in_high : in_low;
endmodule
| 7.339575 |
module dxm_sync (
clk,
rst_n,
in,
out
);
parameter width = 1;
parameter show_warn = 1;
`include "cc_params.inc"
input clk, rst_n;
input [width-1:0] in;
output [width-1:0] out;
wire [width-1:0] out;
wire [width-1:0] internal;
// synopsys translate_off
initial
if ((width != 1) && (... | 7.383446 |
module dx_latch (
a,
b,
pc_out,
ir_out,
data_readRegA,
data_readRegB,
pc_in,
ir_in,
clock,
clear
);
input clock, clear;
input [31:0] pc_in, ir_in, data_readRegA, data_readRegB;
output [31:0] pc_out, ir_out, a, b;
// module register(out, in, clk, input_1'b1able, clr);
... | 6.705557 |
module dynamicFF (
d,
phi,
q
);
input d, phi;
output q;
wire d1, phibar;
trireg #(2, 2, 70) x;
trireg #(2, 2, 70) x1;
not (phibar, phi);
cmos #(10: 12: 14, 8: 10: 12) c1 (x, d, phi, phibar);
cmos #(10: 12: 14, 8: 10: 12) c2 (x1, d1, phibar, phi);
not #(10: 12: 14) (d1, x);
not #(10: 12: ... | 6.554175 |
module DynamicLighting (
dynamicClock,
left,
middle,
right,
digit,
dynamicDigit
);
input dynamicClock; // _Ci~bN_p̃NbN(Hz)
// ̃W[炤
input [2:0] left, middle, right; // 3邤ōA^AEƊU
output [3:0] digit;
output [2:0] dynamicDigit; // EA^AÊǂ_悤ɂ邩
... | 7.050688 |
module dynamicNumber (
input wire dyn_clk, // Dynamic clock.
input wire reset, // Back to zero.
input wire inc, // Increment number.
input wire dec, // Decrement number.
output wire [3:0] number, // Output number.
output wire carry // Zero af... | 7.322964 |
module DynamicRam (
input clk,
ce5,
ce2Hd2,
ce2Hd3,
input [14:0] DRBA,
input DRAMn,
BRWn,
BITMDn,
PIXA,
input [7:0] BD,
output [7:0] dram_to_cpu,
input [7:0] hs,
input [7:0] vs,
output reg [3:0] BIT
);
wire [7:0] bmw_to_dram = PIXA ? {BD[7:4], cpu_read[3:0]}... | 7.432999 |
module dynamic_combine (
input wire sys_clk,
input wire sys_rst_n,
input wire sign,
input wire seg_en,
input wire [19:0] data,
input wire [5:0] point,
output wire shcp,
output wire stcp,
output wire oe,
output wire ds
);
wire [5:0] sel;
wire [7:0] seg;
seg_dynamic seg_dy... | 7.886459 |
module
// Please use original "dynamic_delay.sv" where it is posibble
module dynamic_delay #( parameter
LENGTH = 63, // maximum delay chain length
WIDTH = 4, // data width
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
... | 7.432728 |
module dynamic_display (
// input
CLK,
RSTN,
RSW,
SEG_A_0,
SEG_B_0,
SEG_C_0,
SEG_D_0,
// output
SEG_A,
//11.11.29del
//SEG_B,
//SEG_C,
//SEG_D
SEG_SEL
);
// ------ input --------------------------------------------
input CLK; // System Clock
input RST... | 7.302349 |
module dynamic_disp_instance1_tb;
reg clk;
reg [3:0] ina, inb, inc;
wire [5:0] seg_sel;
wire [7:0] seg_led;
TOP #(
.DIVCLK_CNTMAX(1)
) UUT (
.clk_50M(clk),
.ina(ina),
.inb(inb),
.inc(inc),
.seg_sel(seg_sel),
.seg_led(seg_led)
);
initial begin
clk = 1'b0;
... | 7.190554 |
module dynamic_disp_instance3_tb;
reg clk;
reg [3:0] units,tens;
reg rst,preset;
wire [5:0] seg_sel;
wire [7:0] seg_led;
TOP #(
.DIVCLK_CNTMAX_1ms(1),
.DIVCLK_CNTMAX_1s(2)
)
UUT(
.clk_50M(clk),
.units(units),
.tens(tens),
.rst(rst),
... | 7.190554 |
module dynamic_input_route_request_calc (
route_req_n,
route_req_e,
route_req_s,
route_req_w,
route_req_p,
default_ready_n,
default_ready_e,
default_ready_s,
default_ready_w,
default_ready_p,
my_loc_x_in,
my_loc_y_in,
my_chip_id_in,
abs_x,
abs_y,
abs_chip_... | 6.879804 |
module dynamic_input_route_request_calc (
route_req_n,
route_req_e,
route_req_s,
route_req_w,
route_req_p,
default_ready_n,
default_ready_e,
default_ready_s,
default_ready_w,
default_ready_p,
my_loc_x_in,
my_loc_y_in,
my_chip_id_in,
abs_x,
abs_y,
abs_chip_... | 6.879804 |
module dynamic_input_route_request_calc_para(<%= route_reqs%>
<%= default_readys%>
my_loc_x_in, my_loc_y_in, my_chip_id_in, abs_x, abs_y, abs_chip_id, final_bits, length, header_in);
// begin port declarations
<%
dynamic_node_para_define.p... | 6.879804 |
module dynamic_input_top_16 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_input_top_16 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_input_top_16_para (
route_req_0_out,
route_req_1_out,
route_req_2_out,
default_ready_0_out,
default_ready_1_out,
default_ready_2_out,
tail_out,
yummy_out,
data_out,
valid_out,
clk,
reset,
my_loc_x_in,
my_loc_y_in,
my_chip_id_in,
valid_in,
... | 6.879804 |
module dynamic_input_top_16_para(<%= route_req_outs%><%= default_readys%>tail_out, yummy_out, data_out, valid_out, clk, reset, my_loc_x_in, my_loc_y_in, my_chip_id_in, valid_in, data_in,<%= thanks[:-2]%>);
// begin port declarations
<%
for a in range (DYNAMIC_NODE_PORT):
s = "output route_req_%d_out;" % a
print(s... | 6.879804 |
module dynamic_input_top_4 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_input_top_4 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_input_top_4_para (
route_req_0_out,
route_req_1_out,
route_req_2_out,
default_ready_0_out,
default_ready_1_out,
default_ready_2_out,
tail_out,
yummy_out,
data_out,
valid_out,
clk,
reset,
my_loc_x_in,
my_loc_y_in,
my_chip_id_in,
valid_in,
... | 6.879804 |
module dynamic_input_top_4_para(<%= route_req_outs%>
<%= default_readys%>
tail_out, yummy_out, data_out, valid_out, clk, reset,
my_loc_x_in, my_loc_y_in, my_chip_id_in, valid_in, data_in,
<%= thanks[:-2]%>);
//... | 6.879804 |
module network_input_blk_multi_out #(
parameter LOG2_NUMBER_FIFO_ELEMENTS = 2
) (
input wire clk,
input wire reset,
input wire [64-1:0] data_in,
input wire valid_in,
input wire thanks_in,
output wire yummy_out,
// data_val and data_val1 are the same, this is just done for buffering to
... | 6.896572 |
module bus_compare_equal (
a,
b,
bus_equal
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a == b) ? 1'b1 : 1'b0;
endmodule
| 7.34093 |
module flip_bus (
in,
out
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] in;
output wire [WIDTH-1:0] out;
assign out = ~in;
endmodule
| 7.814939 |
module one_of_eight (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
parameter WIDTH = 8;
parameter BHC = 10;
input [2:0] sel;
input [WIDTH-1:0] in0, in1, in2, in3, in4, in5, in6, in7;
output reg [WIDTH-1:0] out;
always @(*) begin
out = {WIDTH{1'b0}};
cas... | 6.683524 |
module one_of_five (
in0,
in1,
in2,
in3,
in4,
sel,
out
);
parameter WIDTH = 8;
parameter BHC = 10;
input [2:0] sel;
input [WIDTH-1:0] in0, in1, in2, in3, in4;
output reg [WIDTH-1:0] out;
always @(*) begin
out = {WIDTH{1'b0}};
case (sel)
3'd0: out = in0;
3'd1: ... | 6.561086 |
module net_dff #(
parameter WIDTH = 8,
parameter BHC = 10
) (
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q,
input wire clk
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 6.926378 |
module dynamic_input_route_request_calc (
route_req_n,
route_req_e,
route_req_s,
route_req_w,
route_req_p,
default_ready_n,
default_ready_e,
default_ready_s,
default_ready_w,
default_ready_p,
my_loc_x_in,
my_loc_y_in,
my_chip_id_in,
abs_x,
abs_y,
abs_chip_... | 6.879804 |
module dynamic_input_top_16 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_input_top_4 (
route_req_n_out,
route_req_e_out,
route_req_s_out,
route_req_w_out,
route_req_p_out,
default_ready_n_out,
default_ready_e_out,
default_ready_s_out,
default_ready_w_out,
default_ready_p_out,
tail_out,
yummy_out,
data_out,
valid_out,
... | 6.879804 |
module dynamic_node_top_wrap (
input clk,
input reset_in,
input [64-1:0] dataIn_N, // data inputs from neighboring tiles
input [64-1:0] dataIn_E,
input [64-1:0] dataIn_S,
input [64-1:0] dataIn_W,
input [64-1:0] dataIn_P, // data input from processor
input validIn_N, // valid signals... | 7.284099 |
module dynamic_node_top_wrap_para (
input clk,
input reset_in,
input [64-1:0] dataIn_0,
input [64-1:0] dataIn_1,
input validIn_0,
input validIn_1,
input yummyIn_0,
input yummyIn_1,
/*
//original
input [`DATA_WIDTH-1:0] dataIn_N, // data inputs from neighboring tiles
... | 7.284099 |
module dynamic_node_top_wrap (
input clk,
input reset_in,
input [`DATA_WIDTH-1:0] dataIn_N, // data inputs from neighboring tiles
input [`DATA_WIDTH-1:0] dataIn_E,
input [`DATA_WIDTH-1:0] dataIn_S,
input [`DATA_WIDTH-1:0] dataIn_W,
input [`DATA_WIDTH-1:0] dataIn_P, // data input from proc... | 7.284099 |
module dynamic_node_top_wrap_para (
input clk,
input reset_in,
input [`DATA_WIDTH-1:0] dataIn_0,
input [`DATA_WIDTH-1:0] dataIn_1,
input [`DATA_WIDTH-1:0] dataIn_2,
input validIn_0,
input validIn_1,
input validIn_2,
input yummyIn_0,
input yummyIn_1,
input yummyIn_2,
/... | 7.284099 |
module dynamic_node_top_wrap_para
(
input clk,
input reset_in,
<%
print("")
dynamic_node_para_define.print_ports_nl (" input [`DATA_WIDTH-1:0] dataIn_%d,")
dynamic_node_para_define.print_ports_nl (" input validIn_%d,")
dynamic_node_para_define.print_ports (" input yummyIn_%d,")
... | 7.284099 |
module dypat (
clk,
rst,
in,
out
); //without valid signal
input clk, rst, in;
output reg out;
parameter size = 5;
reg [size-1:0] pat, cur_pat;
//ov variation
initial begin
/*$value$plusargs("size=%d",size);
#3;
$value$plusargs("pat=%b",pat);*/
pat = 5'b11011;
out = 0;
end
... | 7.596375 |
module dyn_pattern_exp (
clk,
rst,
valid,
in,
out
);
parameter S0 = 4'b0000, // Reset state
S1 = 4'b0001, // 1st bit detected
S2 = 4'b0010, // 2nd bit detected
S3 = 4'b0011; // 3rd bit detected
input clk, rst, valid, in;
output reg out;
// Pattern stores the 3 bit pattern to det... | 7.136525 |
module dyn_pattern_imp (
clk,
rst,
valid,
in,
out,
pattern
);
// N bit pattern detector
parameter BITS = 5;
input clk, rst, valid, in;
input [BITS-1 : 0] pattern;
output reg out;
reg [BITS-1 : 0] buffer;
integer count;
always @(posedge clk) begin
if (rst == 1) begin
... | 6.74151 |
module dynamic_seg_display_5 (
clk,
scan,
minute,
second,
m_second,
a,
b,
c,
d,
e,
f,
g,
dp,
position
);
input clk, scan;
input [3:0] m_second;
input [7:0] minute, second;
output a, b, c, d, e, f, g, dp;
output [4:0] position;
wire [2:0] counter_data;... | 7.087168 |
module dynamic_shift_register_1 (
CLK,
CE,
SEL,
SI,
DO
);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2 ** SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK) begin
if (CE == 1'b1) data <= ... | 8.394772 |
module dynaQ_demon_toplevel_tb #(
parameter LOCATION_LENGTH = 5,
parameter STEP_LENGTH = 5,
parameter EPSILON_LENGTH = 7,
parameter DATA_LENGTH = 16,
parameter REWARD_LENGTH = 2,
parameter MAP_SIZE = 25,
parameter STATE_LENGTH = 5
) ();
// ------------------------- Glo... | 7.35379 |
module DynCharacter #(
parameter color_fg = 3'b110, // Foreground font color.
parameter color_bg = 3'b001, // Background font color.
parameter gsize = 16, // Glyph size.
parameter alpha = 1 // Transparent font.
) (
input wire px_clk, // Pixel clock.
input wire [2... | 8.359204 |
module DynCharacterS01 #(
parameter color_fg = 3'b110, // Foreground font color.
parameter color_bg = 3'b001, // Background font color.
parameter gsize = 16, // Glyph size.
parameter alpha = 1 // Transparent font.
) (
// RGB stream input.
input wire px_clk, // Pixel ... | 7.116256 |
module DynCharacterS03 #(
parameter color_fg = 3'b110, // Foreground font color.
parameter color_bg = 3'b001, // Background font color.
parameter gsize = 16, // Glyph size.
parameter alpha = 1 // Transparent font.
) (
// RGB stream input.
input wire px_clk, // Pixel ... | 7.116256 |
module DynConsole #(
parameter size = 16 // Glyhp size (must be a power of 2).
) (
// Data interface.
input wire rcv, // Data received.
input wire [7:0] data_i, // Data input.
// Position cursor.
output reg [6:0] cursor_x, // X video map cursor position.
output reg [6:0] cursor_y... | 9.197784 |
module dyndivider (
input clk100MHz,
input [31:0] hz,
output reg clkOut
);
reg [31:0] count = 0;
initial begin
clkOut = 0;
end
always @(posedge clk100MHz) begin
if (count < 50000000 / hz) count <= count + 1;
else begin
count <= 0;
clkOut <= ~clkOut;
end
end
endmodule
| 6.615139 |
module test_here (
input clk,
in,
output [2:0] out
);
always @(posedge clk) begin
out <= in % 2;
end
endmodule
| 6.627466 |
module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter l... | 8.296277 |
module rom_dual_port
(
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter latency = 1;
parameter init_file = "UNUSED";
input clk;
inp... | 7.576841 |
module DynNumber (
input wire clk, // Dynamic clock.
input wire reset, // Back to zero.
input wire inc, // Increment number.
input wire dec, // Decrement number.
output wire [3:0] number, // Output number.
output wire carry_out // Zero ... | 7.163117 |
module MCU_trigger_tx (
input wire clk,
input wire clk_4x,
input wire serdesstrobe,
input wire rst,
input wire [7:0] mcu_trigger_data,
output wire [1:0] trigger_serial
);
MCU_tx tx0 (
.clk(clk),
.clk_4x(clk_4x),
.serdesstrobe(serdesstrobe),
... | 7.45589 |
module DynPong (
input wire dyn_clk, // Dynamic clock.
input wire reset, // Reset the game.
input wire play, // Play-Pause the game.
input wire [9:0] pos_ply1, // Actual player 1 position.
input wire [9:0] pos_ply2, // Actua... | 7.678228 |
module dynpreaddmultadd # (parameter SIZEIN = 16)
module dynpreaddmultadd # (parameter SIZEIN = 8)
(
input clk, ce, rst, subadd,
input signed [SIZEIN-1:0] a, b, c, d,
output signed [2*SIZEIN:0] dynpreaddmultadd_out
);
// Declare registers for intermediate values
reg sig... | 7.970323 |
module dyn_pll_ctrl #(
parameter SPEED_MHZ = 25,
parameter SPEED_LIMIT = 100,
parameter SPEED_MIN = 25,
parameter OSC_MHZ = 100
) (
clk,
clk_valid,
speed_in,
start,
progclk,
progdata,
progen,
reset,
locked,
status
);
input clk; // NB Assumed to be 12.5MHz uart... | 8.51 |
module dypat (
clk,
rst,
in,
out
); //without valid signal
input clk, rst, in;
output reg out;
parameter size = 5;
reg [size-1:0] pat, cur_pat;
integer num_bit;
//non-ov variation
initial begin
/*$value$plusargs("size=%d",size);
#3;
$value$plusargs("pat=%b",pat);*/
pat = 5'b1101... | 7.596375 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.