code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dzcpu_ucode_cblut (
input wire [7:0] iMop,
output reg [8:0] oUopFlowIdx
);
always @(iMop) begin
case (iMop)
8'h7C: oUopFlowIdx = 9'd16; //BIT7
8'h11: oUopFlowIdx = 9'd69; //RLr_b
8'h38: oUopFlowIdx = 9'd505; //SRL_b
`RRr_a, `RRr_b, `RRr_c, `RRr_d, `RRr_e, `RRr_h, `RRr_... | 6.945022 |
module divider_array (
input [63:0] x,
input [63:0] y,
output [63:0] r,
output q
);
wire [64:0] r_temp;
wire q_temp;
assign r_temp = x - y;
assign q_temp = ~r_temp[64];
assign r = q_temp ? r_temp[63:0] : x;
assign q = q_temp;
endmodule
| 7.45817 |
module divider_block_64 (
input X,
input [63:0] Y,
input [63:0] Rin,
output [63:0] Rout,
output Q
);
divider_array row_0 (
{Rin[62:0], X},
Y,
Rout,
Q
);
endmodule
| 7.943326 |
module div_control (
input start,
input clk,
input reset,
input [6:0] div_count,
output reg [4:0] mux_A_sel,
output reg mux_Rin_sel,
output reg mux_smaller_X,
output reg reg_Rin_en,
output reg reg_Q_en,
output reg rdy
);
parameter R1 = 1'b0, Rounds = 1'b1;
reg state_reg, st... | 7.499706 |
module CLA15 ( /* IN */
A,
B,
Cin,
/* OUT */ SUM
);
input [15:1] A, B;
input Cin;
output [15:1] SUM;
wire [15:1] P, G, PS;
wire GS;
assign P[15:1] = A[15:1] | B[15:1];
assign G[15:1] = A[15:1] & B[15:1];
assign PS[15:1] = A[15:1] ^ B[15:1];
assign GS = Cin ? (G[1] | P[1]) : G[1];... | 6.536953 |
module d_align (
in_high,
in_low,
offset,
out
);
input [63:0] in_high;
input [63:0] in_low;
input [2:0] offset;
output [63:0] out;
// FIXME this is a lot of gates
// could use tristates instead
mux #(
.WIDTH (64),
.INPUTS(8)
) mux1 (
{
{in_high[55:0], in_low[... | 7.001175 |
module D_block (
clk,
reset,
D,
Q_ff
);
input clk, reset, D;
parameter en = 1;
output Q_ff;
reg Q_ff;
initial Q_ff = 0;
always @(posedge clk) begin
if (!reset) begin
if (en) Q_ff <= D;
else Q_ff <= 0;
end
end
endmodule
| 7.235234 |
module d_bounce_edge (
sig,
btn,
clk
);
input btn, clk;
output reg sig;
reg [22:0] holdin = 23'h5FFF0F;
reg [1:0] q;
reg out;
always @(posedge clk) begin
if (btn == 1'd1 && holdin != 23'd0) begin
holdin <= holdin - 1'b1;
out <= 1'b0;
end else if (btn == 1'd1 && holdin == 23... | 6.911381 |
module dff (
q,
d,
clk
);
input d, clk;
output reg q;
always @(posedge clk) begin
q <= d;
end
endmodule
| 8.035763 |
module RegEnable (
input clock,
input reset,
input [7:0] io_in,
input io_en,
output [7:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[RegEnable.scala 11:22]
assign io_out = reg_; // @[RegEnable.scala 15:12]
... | 6.779288 |
module RegEnable_2 (
input clock,
input reset,
input io_in,
input io_en,
output io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[RegEnable.scala 11:22]
assign io_out = reg_; // @[RegEnable.scala 15:12]
always @(posedge clock) begin
... | 6.543778 |
module d_cache_simple #(
parameter A_WIDTH = 32,
parameter C_INDEX = 6
) (
//CPU
input wire clk,
clrn,
input wire [A_WIDTH-1:0] p_a,
input wire [31:0] p_dout,
input wire p_strobe, //en
input wire p_rw, //0 read 1 write
input wire [3:0] p_wen,
p_ren,
input flush_except, ... | 8.075263 |
module name : BUX2
// description : Buffer
//****************************************************************************
module BUX2 (A, Q);
input A;
output Q;
// Function Q = A
wire Q;
assign Q = A;
endmodule
| 7.638967 |
module name : BUX4
// description : Buffer
//****************************************************************************
module BUX4 (A, Q);
input A;
output Q;
// Function Q = A
wire Q;
assign Q = A;
endmodule
| 7.418983 |
module name : BUX12
// description : Buffer
//****************************************************************************
module BUX12 (A, Q);
input A;
output Q;
// Function Q = A
wire Q;
assign Q = A;
endmodule
| 7.034943 |
module name : DFRX2
// description : D-flipflop
//****************************************************************************
module DFRX2 (D, C, QN, Q);
input D;
input C;
output QN;
output Q;
reg Q;
wire QN;
assign QN = ~Q;
// Function Q <= D
always @(posedge C) begi... | 6.937435 |
module name : INX2
// description : Inverter
//****************************************************************************
module INX2 (A, Q);
input A;
output Q;
// Function Q = !A
wire Q;
assign Q = !A;
endmodule
| 7.064358 |
module name : LOGIC0
// description : Constant logic 0
//****************************************************************************
module LOGIC0 (Q);
output Q;
// Function Q = 0
wire Q;
assign Q = 1'b0;
endmodule
| 7.240311 |
module name : LOGIC1
// description : Constant logic 1
//****************************************************************************
module LOGIC1 (Q);
output Q;
// Function Q = 1
wire Q;
assign Q = 1'b1;
endmodule
| 7.859624 |
module name : BU_3VX2
// description : Buffer
//****************************************************************************
module BU_3VX2 (A, Q);
input A;
output Q;
// Function Q = A
wire Q;
assign Q = A;
endmodule
| 7.470764 |
module name : IN_3VX2
// description : Inverter
//****************************************************************************
module IN_3VX2 (A, Q);
input A;
output Q;
// Function Q = !A
wire Q;
assign Q = !A;
endmodule
| 7.216771 |
module name : LOGIC0_3V
// description : Constant logic 0
//****************************************************************************
module LOGIC0_3V (Q);
output Q;
// Function Q = 0
wire Q;
assign Q = 1'b0;
endmodule
| 7.240311 |
module name : LOGIC1_3V
// description : Constant logic 1
//****************************************************************************
module LOGIC1_3V (Q);
output Q;
// Function Q = 1
wire Q;
assign Q = 1'b1;
endmodule
| 7.859624 |
module d_cla4 (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g;
assign p[0] = (a[0] ^ b[0]), p[1] = (a[1] ^ b[1]), p[2] = (a[2] ^ b[2]), p[3] = (a[3] ^ b[3]);
assign g[0] = (a[0] & b[0]), g[1] = (a[1] & b[1]), g[2] = (a[2] & b[2]),... | 6.817329 |
module D_CMP (
input [31:0] rs_data,
input [31:0] rt_data,
input [3:0] CMPop,
output reg need_b
);
always @(*) begin
case (CMPop)
0: begin
need_b = (rs_data == rt_data);
end
1: begin
need_b = (rs_data != rt_data);
end
default: begin
need_b = 0;... | 6.649035 |
module d_confreg_port (
input clk,
input rst,
input memwriteM,
input wire [ 3:0] sel,
input wire [ 1:0] data_sram_size,
input wire [31:0] aluoutM,
input wire [31:0] writedata2M,
input wire memenM,
output wire [31:0] readdataM,
output data_r... | 7.12819 |
module CSA15 ( /* IN */
INa,
INb,
INc,
/* OUT */ SOUT,
COUT
);
input [15:1] INa, INb, INc;
output [15:1] SOUT;
output [16:2] COUT;
CSA_d b1 (
INa[1],
INb[1],
INc[1],
SOUT[1],
COUT[2]
);
CSA_d b2 (
INa[2],
INb[2],
INc[2],
SOUT[2],
... | 6.532016 |
module CSA_d ( /* IN */
INa,
INb,
INc,
/* OUT */ SUM,
COUT
);
input INa, INb, INc;
output SUM, COUT;
wire TMP;
assign TMP = INa ^ INb;
assign SUM = TMP ^ INc;
assign COUT = (INa & INb) | (INb & INc) | (INc & INa);
endmodule
| 7.625029 |
module CSA_d ( /* IN */
INa,
INb,
INc,
SUM,
COUT
);
input INa, INb, INc;
output SUM, COUT;
wire TMP;
assign TMP = INa ^ INb;
assign SUM = TMP ^ INc;
assign COUT = (INa & INb) | (INb & INc) | (INc & INa);
endmodule
| 7.625029 |
module D_decoder (
I,
state,
status,
cw_IW,
K
);
input [31:0] I;
input [1:0] state;
input [4:0] status;
wire [10:0] op;
wire [ 8:0] zf_address;
wire [ 1:0] op2;
wire [ 4:0] Rn;
wire [ 4:0] Rt;
assign {op, zf_address, op2, Rn, Rt} = I;
wire store_load = op[1]; // when op[1]=0,... | 6.753492 |
module d_Divider (
d_w,
d_possible,
e,
L
);
parameter size = 4;
output reg [((size*2)-1):0] d_w;
input [((2*size)-1):0] d_possible;
input [((size*2)-1):0] L;
input [(size-1):0] e;
parameter k = 4; //Can assign k as any integer so long as its smaller than L
always @(*) begin
if ((d_... | 6.657782 |
module RegEnable (
input clock,
input reset,
input [7:0] io_in,
input io_en,
output [7:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[RegEnable.scala 11:22]
assign io_out = reg_; // @[RegEnable.scala 15:12]
... | 6.779288 |
module RegEnable_2 (
input clock,
input reset,
input io_in,
input io_en,
output io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[RegEnable.scala 11:22]
assign io_out = reg_; // @[RegEnable.scala 15:12]
always @(posedge clock) begin
... | 6.543778 |
module D_EXT (
input [15:0] imm16,
input EXTop,
output [31:0] EXTout
);
assign EXTout = EXTop ? {{16{imm16[15]}}, imm16} : {{16{1'b0}}, imm16};
endmodule
| 7.899259 |
module d_factor_unit (
input clock,
input reset,
input [31:0] data_in,
input dv_in,
output [31:0] data_out,
output dv_out
);
// counter_1 signals
wire [ 9:0] cnt1;
wire tc_cnt1;
// counter_2 signals
wire [ 9:0] cnt2;
wire ce_cnt2;
w... | 6.522069 |
module D_ff (
Q,
QN,
D,
EN,
RST,
CLK
); //锁存器
output reg Q, QN; // 状态信号Q，～Q
input D; // 激励信号
input EN, RST, CLK; //使能信号EN， 复位信号RST， 时钟信号CLK
// 边沿敏感
always @(posedge CLK) begin // 同步复位
//always @ (posedge CLK, posedge RST) begin // 复位与CLK无关，异步复位
if (RST) begin
Q <= ... | 6.823703 |
module D_ff_AR (
Q,
Qb,
D,
Clk,
reset
);
output Q, Qb;
input D, Clk, reset;
reg Q;
assign Qb = ~Q;
always @(posedge Clk, negedge reset)
if (!reset) Q <= 1'b0;
else Q <= D;
endmodule
| 7.350349 |
module d_ff_async (
q,
d,
clk,
reset
);
input d, clk, reset;
output q;
reg q;
always @(posedge clk or negedge reset) begin
if (!reset) q <= 1'b0;
else q <= d;
end
endmodule
| 6.974274 |
module D_ff_asynCLR (
CLK,
CLR,
D,
Q
);
input CLK, CLR, D;
output reg Q;
always @(posedge CLK or posedge CLR)
if (CLR) Q <= 0;
else Q <= D;
endmodule
| 6.973191 |
module D_FF_async_rst #(
parameter mem_width = 8
) (
input clk,
input reset,
input [mem_width-1 : 0] Rin,
input we,
output reg [mem_width-1 : 0] Rout = {mem_width - 1{1'b0}}
);
always @(posedge clk) begin
if (!reset) begin
Rout <= 0;
end else if (we) begin
Rout <= Rin;
... | 7.680781 |
module D_FF_block #(
parameter mem_width = 16,
parameter mem_depth = 16
) (
input clk,
input reset,
input [mem_width-1 : 0] Rin,
input we,
input [mem_depth-1:0] S,
output [mem_width*mem_depth-1:0] Rout
);
genvar i;
generate
for (i = 0; i < mem_depth; i = i + 1) begin
defpa... | 9.164304 |
module d_ff_data (
d,
q,
qb,
clk
);
input d, clk;
output q, qb;
assign q = ~((~(d & clk)) & qb);
assign qb = ~((~((~d) & clk)) & q);
endmodule
| 7.400981 |
module D_FF_DOWN (
D,
Clk,
Q,
Qn
);
input D, Clk;
output Q, Qn;
wire Clkn, Q0, Qn0;
not i0 (Clkn, Clk);
D_Latch d0 (
D,
Clk,
Q0,
Qn0
);
D_Latch d1 (
Q0,
Clkn,
Q,
Qn
);
endmodule
| 6.960956 |
module d_ff_en #(
parameter W = 32
) (
input wire clk, //system clock
input wire rst, //system reset
input wire enable, //load signal
input wire [W-1:0] D, //input signal
output reg [W-1:0] Q //output signal
);
always @(posedge clk, posedge rst) begin
if (rst) Q <= 0;
else if (ena... | 7.751021 |
module D_FF_Enable_Async (
clk,
resetn,
enable,
d,
q
);
input clk;
input resetn;
input enable;
input d;
output reg q;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
q <= 1'b0;
end else begin
if (enable) begin
q <= d;
end
end
end... | 6.508274 |
module d_ff_reset_en (
input wire clk,
input wire reset,
input wire en,
input wire d,
output reg q
);
reg r_next, r_reg;
//memory/register/d_ff
always @(posedge clk, posedge reset) begin
if (reset) r_reg <= 1'b0;
else r_reg <= r_next;
end
//next state logic
always @(*) be... | 6.62678 |
module d_ff_gates (
d,
clk,
q,
q_bar
);
input d, clk;
output q, q_bar;
wire n1, n2, n3, q_bar_n;
wire cn, dn, n4, n5, n6;
// First Latch
not (n1, d);
nand (n2, d, clk);
nand (n3, n1, clk);
nand (dn, q_bar_n, n2);
nand (q_bar_n, dn, n3);
// Second Latch
not (cn, clk);
not ... | 7.466829 |
module D_FF_neg (
input D,
input clk,
output reg Q
);
always @(negedge clk) begin
Q <= D;
end
endmodule
| 6.877336 |
module D_FF_pos (
input D,
input clk,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 6.832859 |
module d_ff_reset (
input wire clk,
input wire reset,
input wire d,
output reg q
);
always @(posedge clk, posedge reset) begin
if (reset) q <= 1'b0;
else q <= d;
end
endmodule
| 6.930152 |
module d_ff_reset_en (
input wire clk,
input wire reset,
input wire en,
input wire d,
output reg q
);
always @(posedge clk, posedge reset) begin
if (reset) q <= 1'b0;
else if (en) q <= d;
else q <= q;
end
endmodule
| 6.62678 |
module d_ff_reset_en_tb ();
reg clk;
reg reset;
reg en;
reg d;
wire q;
d_ff_reset_en circuit1 (
.clk(clk),
.reset(reset),
.en(en),
.d(d),
.q(q)
);
always begin
clk = ~clk;
#10;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0, d_ff_reset_en_tb... | 6.62678 |
module D_FF_set_reset (
input clk,
input D,
input reset_n,
input set_n,
output Q
);
reg Q_reg, Q_next;
// Asynchronous reset
always @(negedge clk, negedge reset_n) begin
if (!reset_n) Q_reg <= 1'b0;
else Q_reg <= Q_next;
end
// Synchronous set
// Next state logic
al... | 8.26792 |
module D_FF_set_reset_tb ();
reg clk, D, reset_n, set_n;
wire Q;
// Instantiate unit under test
D_FF_set_reset FF0 (
.clk(clk),
.D(D),
.reset_n(reset_n),
.set_n(set_n),
.Q(Q)
);
// Generating a clk signal
// Clock period is T nano seconds
localparam T = 20; //local para... | 8.26792 |
module d_reg_sync #(
parameter WIDTH = 8
) (
input clk,
reset,
en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk)
if (reset) begin
q <= 0;
end else begin
if (en) begin
q <= d;
end
end
endmodule
| 7.340359 |
module: D_FF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module D_FF_TestBench;
// Inputs
reg d;
reg clk;
reg reset;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT... | 7.281187 |
module D_FF_with_Enable (
clk,
resetn,
enable,
d,
q
);
input clk;
input resetn;
input enable;
input d;
output reg q;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
q <= 1'b0;
end else begin
if (enable) begin
q <= d;
end
end
end
... | 7.015492 |
module D_FIFO (
input clock,
input reset,
input [31:0] io_din,
input io_din_v,
input io_dout_r,
output io_din_r,
output reg [31:0] io_dout,
output reg io_dout_v
);
reg [0:31] memory[31:0];
reg [4:0] write_pointe... | 7.301571 |
module d_flipflop_sync_rst (
input D,
output reg Q,
input clk,
input reset
);
always @(posedge clk, posedge reset) begin
if (reset) Q <= 1'd0;
else Q <= D;
end
endmodule
| 6.851896 |
module dff_async_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------... | 7.171044 |
module D_FlipFiop (
CLK,
CLRN,
D,
Q,
QN
);
input wire CLK;
input wire CLRN;
input wire D;
output wire Q;
output wire QN;
wire SYNTHESIZED_WIRE_0;
reg DFF_3;
assign Q = DFF_3;
assign SYNTHESIZED_WIRE_0 = 1;
always @(posedge CLK or negedge CLRN or negedge SYNTHESIZED_WIRE_... | 7.366108 |
module D_FLIPFLOP (
clock,
d,
preset,
q,
qBar,
reset,
tick
);
/*******************************************************************************
** Here all module parameters are defined with a dummy value **
***********************************************************... | 8.171782 |
module d_flipflop_asyncrstlow (
input D, // Data Input
input clk, // Clock Signal
input reset, // Asynchronous Reset Low
output reg Q
); // Data Output
always @(posedge clk or negedge reset) begin
if (reset == 1'b0) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.984263 |
module d_flipflop_asyncset (
input D, // Data Input
input clk, // Clock Signal
input preset, // Asynchronous Set
output reg Q
); // Data Output
always @(posedge clk or posedge preset) begin
if (preset == 1'b1) Q <= 1'b1;
else Q <= D;
end
endmodule
| 6.984263 |
module d_flipflop_asyncset_reset (
input D, // Data Input
input clk, // Clock Signal
input preset, // Asynchronous Set
input reset, //Asynchronous Reset Low
output reg Q
); // Data Output
always @(posedge clk or posedge preset or negedge reset) begin
if (preset == 1'b1) Q <= 1'b1;
e... | 6.984263 |
module DFF (
D,
rst,
clk,
q
);
input D, rst, clk;
output q;
reg q;
always @(posedge clk) begin
if (rst == 1) begin
q <= 0;
end else begin
q <= D;
end
end
endmodule
| 6.795644 |
module d_flipflop_set_reset #(
parameter DELAY = 10
) (
input wire clk1,
pr1_n,
clr1_n,
D1,
input wire clk2,
pr2_n,
clr2_n,
D2,
output wire q1,
output wire q1_n,
output wire q2,
output wire q2_n
);
reg q1_reg;
reg q2_reg;
always @(posedge clk1, negedge pr1_n... | 6.507777 |
module: d_flipflop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module d_flipflop_tb;
// Inputs
reg D;
reg clk;
// Outputs
wire Q;
// Instantiate the Unit Under Test (UUT)
d_fl... | 7.584818 |
module d_flipflop_test;
reg clock, d;
wire q, q_bar;
d_flipflop dff_1 (
q,
q_bar,
clock,
d
);
initial begin
clock = 0;
d = 0;
#1 clock = 1;
d = 0;
#1 clock = 0;
d = 1;
#1 clock = 1;
d = 1;
#1 clock = 0;
d = 0;
#1 clock = 1;
d = 0;
#... | 7.227054 |
module d_flip_flop_gate (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar
); //
// INTERNAL WIRES
wire s, r;
wire s1, r1;
assign s = d;
// NOT1
not (r, s);
// SR FLIP-FLOP ---------------------------------
// NAND3
nand (s1, s, clk);
// NAND4
... | 8.394132 |
module d_flip_flop_dataflow (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar
); //
assign s = d;
assign r = ~d;
// SR FLIP-FLOP ---------------------------------
// INTERNAL WIRES
wire s1, r1;
// NAND3
assign s1 = ~(s & clk);
// NAND4
assign r1 = ... | 7.482547 |
module d_flip_flop_behavioral (
input clk, // Clock
input d, // Inputs
output reg q, // Output
output qbar
); //
parameter DATA0 = 1'b0, DATA1 = 1'b1;
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case ({
d
})
DATA0: q <= 1'b0;
... | 7.800385 |
module D_flip_flop_7474 (
q,
qN,
d,
p
);
input d, p;
output q, qN;
wire c;
Clock clock (c);
assign p = c;
wire r0, s0, y0, yN0;
Latch_SR Latch_SR_0 (
y0,
yN0,
s0,
r0
);
wire r1, s1, y1, yN1;
Latch_SR Latch_SR_1 (
y1,
yN1,
s1,
r1
)... | 7.029237 |
module D_Flip_Flop_behavior (
output reg Q,
input D,
En,
rst
);
always @(posedge En, negedge rst) begin
if (!rst) Q <= 1'b0;
else Q <= D;
end
endmodule
| 7.857323 |
module D_flip_flop_c #(
parameter WIDTH = 8
) (
input clk,
input reset,
input clear,
input enable,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk, posedge reset)
if (reset || clear) q <= 0;
else if (enable) q <= d;
endmodule
| 8.135373 |
module d_flip_flop_pos_edge_sync_en_behavioral (
input clk, // Clock
input en, // Enable
input d, // Data
output reg q, // Output
output qbar
); //
assign qbar = ~q;
// D FLIP-FLOP WITH SYNC ENABLE
always @(posedge clk) begin
if (en) begin
q <= d;
e... | 7.558774 |
module D_FLIP_FLOP_POS_EDGE_SYNC_EN_TB ();
// INPUT PROBES
reg EN;
reg D;
// OUTPUT PROBES
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
d_flip_flop_pos_edge_sync_en_... | 7.538639 |
module d_flip_flop_pulse_triggered_gate (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar
); //
// INTERNAL WIRES
wire clk1;
//NOT 3
not (clk1, clk);
// D-FLIP FLOP (BOSS)
// INTERNAL WIRES
wire s1, r1;
wire s2, r2;
assign s1 = d;
// NOT2
no... | 7.558774 |
module d_flip_flop_pulse_triggered_dataflow (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar
); //
// INTERNAL WIRES
wire clk1;
// NOT3
assign clk1 = ~clk;
// D-FLIP FLOP (BOSS)
// INTERNAL WIRES
wire s1, r1;
wire s2, r2;
assign s1 = d;
// NO... | 7.558774 |
module d_flip_flop_pulse_triggered_behavioral (
input clk, // Clock
input d, // Inputs
output reg q, // Output
output qbar
); //
parameter DATA0 = 1'b0, DATA1 = 1'b1;
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case ({
d
})
DATA0: ... | 7.558774 |
module D_FLIP_FLOP_PULSE_TRIGGERED_TB ();
// INPUT PROBES
reg D;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (ga... | 7.538639 |
module D_flip_flop_Reg (
d,
q,
reset_
);
input reset_;
input d;
output q;
wire c;
Clock clock (c);
reg D_EDGE;
assign q = D_EDGE;
always @(reset_ == 0) #1 D_EDGE <= 0;
always @(posedge c) if (reset_ == 1) #3 D_EDGE <= (c == 1) ? d : D_EDGE;
endmodule
| 6.988503 |
module D_Flip_Flop_t;
// input and output signals
reg clk = 1'b0;
reg d = 1'b0;
wire q;
// generate clk
always #(1) clk = ~clk;
// test instance instantiation
D_Flip_Flop DFF (
.clk(clk),
.d (d),
.q (q)
);
// uncommment and add "+access+r" to your nverilog command to dump f... | 7.212332 |
module D_FLIP_FLOP_TB ();
// INPUT PROBES
reg D;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
d_flip_flo... | 7.715274 |
module DFlipFlopTest ();
reg c, d;
wire q, nq;
DFlipFlop dff (
.C (c),
.D (d),
.Q (q),
.nQ(nq)
);
initial begin
$monitor("%g Clock:%b Data:%b Q:%b NotQ:%b", $time, c, d, q, nq);
assign c = 1;
assign d = 1;
#10 assign c = 0;
assign d = 0;
#10 assign c = 1;
#1... | 6.567486 |
module d_flop (
d,
clk,
q
);
// данные для записи в регистр
input [31:0] d;
// сигнал синхронизации
input clk;
// сам регистр
output reg [31:0] q;
// изначально заполнен нулем
initial begin
q <= 32'b0;
end
// запись на фронте сигнала синхронизации
always @(posedge clk) q <= d;
e... | 7.13745 |
module D_flop_n (
Di,
Clk,
Qa,
Rst
);
input Di, Clk, Rst;
output reg Qa;
always @(negedge Clk)
if (Rst) Qa = 1'b0;
else Qa = Di;
endmodule
| 7.69716 |
module D_flop_p (
Di,
Clk,
Qa,
Rst
);
input Di, Clk, Rst;
output reg Qa;
always @(posedge Clk)
if (Rst) Qa = 1'b0;
else Qa = Di;
endmodule
| 7.933684 |
module d_fullsub (
a,
b,
bin,
bout,
d
);
input a, b, bin;
output bout, d;
wire w, d1, b1, b2;
assign d = (a ^ b) ^ bin;
assign bout = ((~a) & bin) | ((~a) & b) | (b & bin);
endmodule
| 6.55851 |
module d_f_f (
Q,
CLK,
RESET,
SET,
D,
Qn
);
input CLK;
wire CLK;
input RESET;
wire RESET;
input SET;
wire SET;
input D;
wire D;
output Q;
reg Q;
output Qn;
wire Qn;
assign Qn = ~Q;
always @(posedge CLK or negedge SET or negedge RESET) begin
if (!RESET) Q <= 0;... | 6.613303 |
module d_halfadder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
assign sum = a ^ b, cout = a & b;
endmodule
| 6.605096 |
module sub_HexSeg (
DATA_IN,
SEG_OUT
);
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//----------------------//
// INPUTS ... | 7.51565 |
module D_Latch2 (
clk,
in,
out
);
parameter n = 24999999;
parameter m = 1;
input clk;
wire rst;
assign rst = 0;
reg [25:0] cnt;
input [m-1:0] in;
output [m-1:0] out;
reg [m-1:0] out;
reg clk_out;
always @(posedge clk)
if (rst == 1) begin
cnt <= 0;
clk_out <= 0;
end... | 6.966564 |
module D_LATCHTB;
reg CLK;
reg D;
reg ENABLE;
wire Q;
wire QBAR;
D_LATCH uut (
.d(D),
.enable(ENABLE),
.clk(CLK),
.q(Q),
.qbar(QBAR)
);
initial begin
CLK <= 0;
D <= 0;
ENABLE <= 0;
end
always #50 CLK = ~CLK;
initial begin
ENABLE = 0;
D = 0;... | 7.001485 |
module d_latch_1_tb;
reg ena, rst;
reg d;
wire q;
reg test_true = 1'b1;
d_latch_1 test1 (
.ena(ena),
.rst(rst),
.d (d),
.q (q)
);
initial begin
rst = 0;
ena = 1;
d = 0;
#100 test_true = (q == 1'b0);
rst = 0;
ena = 1;
d = 1;
#100 test_true =... | 6.581686 |
module D_Latch_basic_gate (
output [1:0] Q,
input D,
En,
rst
);
wire [2:0] w;
not G0 (w[0], D);
nand G1 (w[1], D, En);
nand G2 (w[2], w[0], En);
nand G3 (Q[0], w[1], Q[1]);
nand G4 (Q[1], Q[0], w[2], rst);
endmodule
| 7.060358 |
module D_Latch_behavior (
output reg Q,
input D,
En,
rst
);
always @(D, En, rst) begin
if (!rst) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.655056 |
module d_latch_gates (
d,
clk,
q,
q_bar
);
input d, clk;
output q, q_bar;
wire n1, n2, n3;
not (n1, d);
nand (n2, d, clk);
nand (n3, n1, clk);
nand (q, q_bar, n2);
nand (q_bar, q, n3);
endmodule
| 7.691161 |
module not_switch (
out,
in
);
output out;
input in;
supply1 power;
supply0 ground;
pmos (out, power, in);
nmos (out, ground, in);
endmodule
| 6.600466 |
module d_latch_switch (
clk,
d,
q
);
input clk, d;
output q;
wire clkn, net1, qn;
not_switch i1 (
clkn,
clk
);
pmos p1 (d, q, clkn);
nmos n1 (d, q, clk);
pmos p2 (q, net1, clk);
nmos n2 (q, net1, clkn);
not_switch i2 (
qn,
q
);
not_switch i3 (
net1,... | 7.073948 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.