code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module d_latch_test;
reg clock, d;
wire q, q_bar;
d_latch dl (
q,
q_bar,
clock,
d
);
initial begin
clock = 0;
d = 0;
#1 clock = 1;
d = 0;
#1 clock = 0;
d = 1;
#1 clock = 1;
d = 1;
#1 clock = 0;
d = 0;
#1 clock = 1;
d = 0;
#1 clock = ... | 7.21522 |
module D_latch_try_2 (
D,
E,
Q,
Qnot
); //declares module
input wire D, E; //defines input wires D, E
output Q, Qnot; //defines output Q, Qnot
reg rQ, rQnot; //defines rQ, rQnot
always @(*) begin //initiates always @
if (E) begin //if statement triggered by E
rQ <= D; //defi... | 6.57665 |
module d_line(//input
pulse_clk,
sys_rst_l,
Xe,
Ye,
change_readyH,
//output
X_acc,
Y_acc,
X_dec,
Y_dec,
draw_overH
);
parameter LO = 1'b0,
HI = 1'b1,
X = 1'bx;
input pulse_clk;
input sys_rst_l;
input [15:0] Xe;
input [15:0] Ye;
input change_readyH;... | 6.819986 |
module DLPN ( /* IN */
L,
/* OUT */ PB,
Pa
);
input [13:0] L;
output [13:0] PB, Pa;
reg [13:0] Lp, Ln;
reg Sb;
always @(L) begin
casex (L)
14'b1?????????????: Lp[13:0] = 14'b11111111111111;
14'b01????????????: Lp[13:0] = 14'b01111111111111;
14'b001???????????: Lp[13:0] =... | 7.163956 |
module d_mem (
input wire clk,
input wire rst,
input wire write,
input wire [`ADDR_BUS] addr,
input wire [`DATA_BUS] data_i,
output reg [`DATA_BUS] data_o,
output reg error
);
reg [`BYTE0] mem[0:`MEM_SIZE];
initial begin
error = `FALSE;
data_o = `DATA_ZERO;
end
always @(... | 7.989453 |
module D_memory (
input [`MEM_SPACE-1:0] address, // address input
input [ `DSIZE-1:0] data_in, // data input
output reg [ `DSIZE-1:0] data_out, // data output
input clk,
input rst,
input write_en
);
reg [`D... | 7.724386 |
module d_mem_icecream_v1 #(
parameter [ 7:0] d_addr_width = 8'd8,
parameter [31:0] d_mem_length = 32'd64
) (
input clk,
input d_req,
input d_dir,
input [d_addr_width-1:0] d_addr,
input [7:0] d_wdata,
output d_ack,
output [7:0] d_rdata
);
`include "macros/direction.vh"
reg [7:0... | 8.462441 |
module d_mem_sim #(
parameter [ 7:0] d_addr_width = 8'd8,
parameter [31:0] d_mem_length = 32'd64
) (
input clk,
input d_req,
input d_dir,
input [d_addr_width-1:0] d_addr,
input [7:0] d_wdata,
output d_ack,
output [7:0] d_rdata
);
`include "macros/direction.vh"
reg [7:0] memory... | 7.984428 |
module d_mem_tang #(
parameter [ 7:0] d_addr_width = 8'd8,
parameter [31:0] d_mem_length = 32'd64
) (
input clk,
input d_req,
input d_dir,
input [d_addr_width-1:0] d_addr,
input [7:0] d_wdata,
output d_ack,
output [7:0] d_rdata
);
`include "macros/direction.vh"
wire write_en;
... | 8.111036 |
module d_mem_upduino2 #(
parameter [ 7:0] d_addr_width = 8'd8,
parameter [31:0] d_mem_length = 32'd64
) (
input clk,
input d_req,
input d_dir,
input [d_addr_width-1:0] d_addr,
input [7:0] d_wdata,
output d_ack,
output [7:0] d_rdata
);
`include "macros/direction.vh"
reg [7:0] m... | 7.465073 |
module d_m_areg ( //input
clk,
rst,
d_flits_m,
v_d_flits_m,
mem_done_access,
//output
d_m_areg_flits,
v_d_m_areg_flits,
d_m_areg_state
);
//input
input clk;
input rst;
input [143:0] d_flits_m;
input v_d_flits_m;
input mem_done_access;
//output
output [175:0] d_m_areg... | 8.173424 |
module D_NPC (
input [31:0] F_PC,
input [31:0] D_PC,
input [25:0] imm26,
input [31:0] rs_data,
input need_b,
input [2:0] NPCop,
output [31:0] NPC
);
assign NPC = (NPCop == 0) ? F_PC + 4 :
(NPCop == 1 && need_b) ? {{14{imm26[15]}}, imm26[15:0], 2'b00} + D_PC + 4 :
... | 6.78157 |
module d_pipereg (
clk,
f_icode,
f_ifun,
f_rA,
f_rB,
f_valC,
f_valP,
d_icode,
d_ifun,
d_rA,
d_rB,
d_valC,
d_valP
);
parameter n = 64;
input clk;
input [3:0] f_icode, f_ifun;
input [3:0] f_rA, f_rB;
input [n-1:0] f_valC;
input [n-1:0] f_valP;
output reg ... | 7.140016 |
module D_pipe_reg (
input clk,
input reset,
input Stall,
input MD_Stall,
input [31:0] IR_F,
input [31:0] PC4_F,
output reg [31:0] IR_D,
output reg [31:0] PC4_D
);
initial begin
IR_D = 0;
PC4_D = 0;
end
always @(posedge clk) begin
if (reset == 1) begin
IR_D = 0... | 8.177983 |
module D_PRAM #(
parameter WIDTH_DATA = 48,
WIDTH_ADDR = 8
) (
///write block signals//
input i_wclk,
input i_wr_en,
input [WIDTH_ADDR-1:0] i_WADDR,
input [WIDTH_DATA-1:0] i_WDATA,
///read block signals //
input i_rdclk,
input i_rd_en,
input [WIDTH_ADDR-1:0] i_RADDR,
out... | 8.653048 |
module d_p_ff (
clk,
rst,
din,
q,
qb
);
input clk, rst, din;
output reg q;
output qb;
assign qb = ~q;
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else begin
q <= din;
end
end
endmodule
| 6.562172 |
module d_ram (
din,
w_addr,
w_en,
r_addr,
r_en,
clk,
dout
);
initial begin
$readmemh("soc/src/memory/d_ram_synth.hex", mem);
end
parameter addr_width = 11;
parameter data_width = 8;
input [addr_width-1:0] w_addr;
input [addr_width-1:0] r_addr;
input [data_width-1:0] din;
... | 8.190832 |
module d_rca32 (
input [31:0] a,
b,
input cin,
output [31:0] sum,
output cout
);
wire [31:0] c;
wire [31:0] x1;
wire [31:0] x2;
wire [31:0] o;
genvar i;
assign x1[0] = a[0] ^ b[0], x2[0] = a[0] & b[0];
assign sum[0] = cin ^ x1[0], o[0] = cin & x1[0];
assign c[0] = o[0] | x2[0]... | 6.731507 |
module D_reg (
input wire clk,
en,
clr,
Reset,
input wire [31:0] RD,
PCPlus4F,
output reg [31:0] InstrD,
PCPlus4D
);
always @(posedge clk, negedge Reset) begin
if (!Reset) begin
InstrD <= 0;
PCPlus4D <= 0;
end else if ((clr == 1) && !en) begin
InstrD <=... | 7.863929 |
module RegEnable (
input clock,
input reset,
input [31:0] io_in,
input io_en,
output [31:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_; // @[RegEnable.scala 21:22]
assign io_out = reg_; // @[RegEnable.scala 2... | 6.779288 |
module RegEnable_2 (
input clock,
input reset,
input io_in,
input io_en,
output io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[RegEnable.scala 21:22]
assign io_out = reg_; // @[RegEnable.scala 25:12]
always @(posedge clock) begin
... | 6.543778 |
module sub_SegDriver (
CLK_50MHZ,
MASTER_RST,
DATA_IN,
SEG_OUT,
SEG_SEL
);
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
//-... | 7.23348 |
module D_signal_delay (
clk,
D,
D_o
);
input clk;
input wire D;
output reg D_o;
reg [1:0] bits;
always @(posedge clk) begin
D_o <= bits[1];
bits <= {bits[0], D};
end
endmodule
| 6.736031 |
module d_sram2sraml (
input wire clk,
rst,
//sram
input wire data_sram_en,
input wire [31:0] data_sram_addr,
output wire [31:0] data_sram_rdata,
input wire [3:0] data_sram_wen,
input wire [31:0] data_sram_wdata,
output wire d_stall,
input wire longest_stall,
//sram like
... | 7.177083 |
module d_sram_to_sram_like (
input wire clk,
rst,
//sram
input wire data_sram_en,
input wire [31:0] data_sram_addr,
output wire [31:0] data_sram_rdata,
input wire [3:0] data_sram_wen,
input wire [31:0] data_sram_wdata,
output wire d_stall,
//sram like
output wire data_req, ... | 7.384637 |
module D_ssd (
output reg [7:0] D_ssd,
input [3:0] i
);
always @*
case (i)
4'd0: D_ssd = `SS_0;
4'd1: D_ssd = `SS_1;
4'd2: D_ssd = `SS_2;
4'd3: D_ssd = `SS_3;
4'd4: D_ssd = `SS_4;
4'd5: D_ssd = `SS_5;
4'd6: D_ssd = `SS_6;
4'd7: D_ssd = `SS_7;
4'd8: D_... | 7.01211 |
module D_Stage_Reg (
input clk,
rst,
input [31:0] instrF,
input [31:0] pc_plus4F,
output reg [31:0] instrD,
output reg [31:0] pc_plus4D
);
always @(negedge clk, posedge rst) begin
if (rst) begin
instrD <= 0;
pc_plus4D <= 0;
end else begin
instrD <= inst... | 7.868408 |
module d_stat (
input wire [`icodeBus] icode,
input wire cnd,
input wire imem_error,
output reg [`statBus] d_stat
);
always @(*) begin
case ({
icode, 4'h0
})
`halt: begin
d_stat = `stop;
end
`nop: begin
d_stat = `OK;
end
`rrmovq: begin
... | 6.849863 |
modules: DisplayControl.v , SpeakerControl.v
// Board: BASYS3 By Digilent
//------------------------------------------------------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: JCT Jerusalem College of technology
// Engineer:
//
// Cre... | 7.347068 |
module DTest_v;
task passTest;
input actualOut, expectedOut;
input [`STRLEN*8:0] testType;
inout [7:0] passed;
if (actualOut == expectedOut) begin
$display("%s passed", testType);
passed = passed + 1;
end else $display("%s failed : %d should be %d", testType, actualOut, expectedOut);
... | 7.333062 |
module d_test_circ_2 (
N0,
N1,
N2,
N7
);
input N0, N1, N2;
output N7;
wire N25, N26;
and AND2_4 (N25, N0, N1);
nand NAND2_5 (N26, N1, N2);
nor NOR2_6 (N7, N25, N26);
endmodule
| 7.023878 |
module d_tlb (
input wire [31:0] inst_va,
input wire [31:0] inst_va2,
input wire [31:0] data_va,
input wire [31:0] data_va2,
output wire [31:0] data_pa,
output wire [31:0] data_pa2,
output wire [31:0] inst_pa,
output wire [31:0] inst_pa2,
output wire no_cache_d,
output wire no_... | 6.620635 |
module D_to_E (
input wire clk,
rst,
input wire stallE,
input wire flushE,
input wire [31:0] pcD,
input wire [31:0] rd1D,
rd2D,
input wire [4:0] rsD,
rtD,
rdD,
input wire [31:0] immD,
input wire [31:0] pc_plus4D,
input wire [31:0] instrD,
input wire [31:0] pc_bran... | 6.725864 |
module d_ff_reset (
input wire clk,
reset,
input wire d,
output reg q
);
// body
always @(negedge clk)
if (reset) q <= 1'b0;
else q <= d;
endmodule
| 6.930152 |
module srff_tb ();
reg d, clk;
wire q, qb;
d_sr L0 (
q,
qb,
d,
clk
);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
clk = 0;
d = 0;
#20;
d = 1;
#100;
$finish;
end
always #10 clk = !clk;
endmodule
| 6.562944 |
module d_wsram_1k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [5:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.263668 |
module d_wsram_2k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.441582 |
module d_wsram_2k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.322502 |
module d_wsram_2k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.196377 |
module d_wsram_2k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.302807 |
module d_wsram_4k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.531948 |
module d_wsram_4k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.571882 |
module d_wsram_4k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.397342 |
module d_wsram_4k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Stro... | 7.352116 |
module teste;
wire a, b, c, d, e;
wire anot, bnot, cnot, dnot, enot; //saidas com valores indeterminados. Nao sei o motivo
wire an, bn, cn, dn, en;
wire x, y, w, z;
reg j, k;
reg pulse;
initial begin
j = 1;
k = 0;
pulse = 1;
end
jkff JKFFe (
e,
enot,
j,
k,
... | 7.490834 |
module teste;
wire a, b, c, d, e, f;
wire anot, bnot, cnot, dnot, enot, fnot; //saidas nao confiaveis
wire an, bn, cn, dn, en, fn;
reg j, k;
reg pulse;
initial begin
j = 0;
k = 1;
pulse = 1;
end
jkff JKFFa (
a,
cnot,
j,
k,
pulse
);
jkff JKFFb (
b,
... | 7.490834 |
module teste;
wire a, b, c, d, e, f;
wire anot, bnot, cnot, dnot, enot, fnot; //saidas nao confiaveis
wire an, bn, cn, dn, en, fn;
reg j, k;
reg pulse;
initial begin
j = 0;
k = 1;
pulse = 1;
end
jkff JKFFa (
a,
cnot,
j,
k,
pulse
);
jkff JKFFb (
b,
... | 7.490834 |
module teste;
wire a, b, c, d;
wire anot, bnot, cnot, dnot;
wire an, bn, cn, dn;
reg preset, pulse;
reg clear;
tff TFFa (
a,
anot,
1,
bn,
preset,
clear
);
tff TFFb (
b,
anot,
1,
cn,
preset,
clear
);
tff TFFc (
c,
an... | 7.490834 |
module
module testbed;
// Declare variables for stimulating input
reg CLK, CLEAR_BAR;
wire [3:0] NUM;
// Monitor changes in NUM and print once a change happens
initial
$monitor($time," Count : %d",NUM);
//Instantiate the design block counter
//NUM is the 4-bit output from the counter
//CLK is the clock... | 7.009919 |
module sr_latch (
q,
qbar,
sbar,
rbar,
preset,
clear
);
//port declaration
output q, qbar;
input sbar, rbar, clear, preset;
//implementation
nand (q, sbar, qbar, preset);
nand (qbar, rbar, q, clear);
endmodule
| 7.007228 |
module with clear and preset
module d_latch(q,qbar,d,en,preset,clear);
//port declaration
output q,qbar;
input d,en,clear,preset;
//implementation
wire s,r;
nand (s,d,en);
nand (r,~d,en);
sr_latch srl(q,qbar,s,r,preset,clear);
endmodule
| 7.000657 |
module d_ff (
q,
d,
clk,
preset,
clear
);
//port declaration
output q;
input d, clk, clear, preset;
//implementation
wire y, ybar, l;
//master d latch
d_latch master (
y,
ybar,
d,
clk,
1'b1,
clear
);
//slave d latch
d_latch slave (
q,
... | 7.310086 |
module t_ff (
q,
t,
clk,
preset,
clear
);
//port declaration
output q;
input t, clk, clear, preset;
//implementation
wire a;
xor (a, t, q);
d_ff dddd (
q,
a,
clk,
preset,
clear
);
endmodule
| 6.889794 |
module rippleCounter4 (
NUM,
CLK,
CLEAR_BAR
);
//port declaration
output [3:0] NUM;
input CLK, CLEAR_BAR;
//implementation
t_ff t1 (
NUM[0],
1'b1,
CLK,
1'b1,
CLEAR_BAR
);
t_ff t2 (
NUM[1],
1'b1,
NUM[0],
1'b1,
CLEAR_BAR
);
t_ff t... | 6.686191 |
module E1_1_FullAdder_1bit (
ain,
bin,
cin,
sout, // sum bit
cout // carry bit
);
input ain, bin, cin;
output sout, cout;
wire sum_1, carry_1, carry_2;
assign cout = carry_1 | carry_2;
Adder Adder_inst_1 (
.ain (ain),
.bin (bin),
.sout(sum_1),
.cout(carr... | 6.572664 |
module E1_2_FullAdder_4bits (
ain,
num1_in,
num2_in,
aout,
sout
);
input wire ain;
input wire [3:0] num1_in;
input wire [3:0] num2_in;
output wire aout;
output wire [3:0] sout;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
E1_1_FullAdder_1bit b2... | 6.655644 |
module e1_buf_if_wb_tb;
// Signals
reg rst = 1;
reg clk = 1;
// Wishbone master
wire [13:0] wb_addr;
wire [31:0] wb_rdata;
wire [31:0] wb_wdata;
wire [ 3:0] wb_wmsk;
wire wb_cyc;
wire wb_we;
reg wb_ack;
// Buffer interface
wire [15:0] buf_rx_data;
wir... | 6.87357 |
module e1_crc4 #(
parameter INIT = 4'h0,
parameter POLY = 4'h3
) (
// Input
input wire in_bit,
input wire in_first,
input wire in_valid,
// Output (updated 1 cycle after input)
output wire [3:0] out_crc4,
// Common
input wire clk,
input wire rst
);
reg [3:0] state;
wi... | 7.70491 |
module e1_crc4_tb;
// Signals
reg rst = 1;
reg clk = 1;
reg [31:0] data;
wire in_bit;
reg in_valid;
reg in_first;
wire [3:0] crc;
// Setup recording
initial begin
$dumpfile("e1_crc4_tb.vcd");
$dumpvars(0, e1_crc4_tb);
end
// Reset pulse
initial begin
#31 rst = 0;
#20000 $... | 6.983105 |
module e1_rx #(
parameter integer LIU = 0,
parameter integer MFW = 7
) (
// IO pads
// Raw PHY
input wire pad_rx_hi_p,
input wire pad_rx_hi_n,
input wire pad_rx_lo_p,
input wire pad_rx_lo_n,
// LIU
input wire pad_rx_data,
input wire pad_rx_clk,
// Buffer interface
o... | 7.62117 |
module e1_rx_clock_recovery (
// Input
input wire in_hi,
input wire in_lo,
input wire in_stb,
// Output
output wire out_hi,
output wire out_lo,
output wire out_stb,
// Common
input wire clk,
input wire rst
);
reg [5:0] cnt;
reg enabled;
always @(posedge clk)
if ... | 7.259182 |
module e1_rx_filter (
// Input
input wire in_hi,
input wire in_lo,
// Output
output reg out_hi,
output reg out_lo,
output reg out_stb, // Strobe on any 0->1 transition
// Common
input wire clk,
input wire rst
);
// Signals
reg in_hi_r;
reg in_lo_r;
reg [1:0] cnt_hi;
... | 7.093974 |
module e1_rx_liu (
// Pads
input wire pad_rx_data,
input wire pad_rx_clk,
// Output
output reg out_data,
output reg out_valid,
// Common
input wire clk,
input wire rst
);
wire rx_data;
wire rx_clk;
reg rx_data_r;
reg rx_clk_r;
// IOBs (registered)
SB_IO #(
.P... | 7.634302 |
module e1_rx_phy (
// IO pads
input wire pad_rx_hi_p,
input wire pad_rx_hi_n, // Unused in ice40
input wire pad_rx_lo_p,
input wire pad_rx_lo_n, // Unused in ice40
// Output
output wire rx_hi,
output wire rx_lo,
// Common
input wire clk,
input wire rst
);
SB_IO #(
... | 6.68439 |
module e1_tb;
// Signals
reg rst = 1;
reg clk_16m = 0;
reg clk_30m72 = 0;
reg [7:0] in_file_data;
reg in_file_valid;
reg in_file_done;
wire e1_in_tip;
wire e1_in_ring;
wire e1_bit;
wire e1_valid;
wire e1_out_tip;
wire e1_out_ring;
wire df_valid;
wire [7:0] df_data;
wire [4:0] df_ts... | 7.281636 |
module e1_tx #(
parameter integer LIU = 0,
parameter integer MFW = 7
) (
// IO pads
// Raw PHY
output wire pad_tx_hi,
output wire pad_tx_lo,
// LIU
output wire pad_tx_data,
output wire pad_tx_clk,
// Buffer interface
input wire [7:0] buf_data,
output wire [4:0] buf_ts,
... | 8.432745 |
module e1_tx_framer_tb;
// Signals
reg rst = 1;
reg clk_30m72 = 0;
wire [7:0] in_data;
wire [1:0] in_crc_e;
wire [3:0] in_frame;
wire [4:0] in_ts;
wire in_mf_first;
wire in_mf_last;
wire in_req;
wire in_rdy;
wire out_bit;
wire out_valid;
// Setup recording
initial begin
$dumpfile("... | 6.634145 |
module e1_tx_liu (
// Pads
input wire pad_tx_data,
input wire pad_tx_clk,
// Intput
input wire in_data,
input wire in_valid,
// Common
input wire clk,
input wire rst
);
// Signals
reg [5:0] cnt_cur;
reg [5:0] cnt_nxt;
reg tx_data;
wire tx_clk;
// Counters
always @(p... | 7.749881 |
module e1_tx_phy (
// IO pads
output wire pad_tx_hi,
output wire pad_tx_lo,
// Input
input wire tx_hi,
input wire tx_lo,
// Common
input wire clk,
input wire rst
);
SB_IO #(
.PIN_TYPE(6'b010100),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS"... | 6.823531 |
module to implement Clock control
//
// ====================================================================
`include "e203_defines.v"
module e203_clk_ctrl (
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed... | 8.470867 |
module to implement the core's general purpose registers file
//
// ====================================================================
`include "e203_defines.v"
module e203_dec_regfile(
input [`E203_RFIDX_WIDTH-1:0] read_src1_idx,
input [`E203_RFIDX_WIDTH-1:0] read_src2_idx,
output [`E203_XLEN-1:0] read_src1... | 8.470867 |
module to implement DTCM SRAM
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_DTCM //{
module e203_dtcm_ram(
input sd,
input ds,
input ls,
input ... | 8.470867 |
module to implement the extended CSR
// current this is an empty module, user can hack it
// become a real one if they want
//
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_CSR_EAI//{
module e203_extend_csr(
// The Handshake Interface
... | 8.470867 |
module to implement the Conditional Branch Instructions,
// which is mostly share the datapath with ALU adder to resolve the comparasion
// result to save gatecount to mininum
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_bjp(
/////////... | 8.470867 |
module to implement the regular ALU instructions
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_rglr(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ... | 8.470867 |
module
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_NICE//{
module e203_exu_nice(
input nice_i_xs_off,
input nice_i_valid, // Handshake valid
output nice_i_ready, // Handshake ready
input [`E203_XLEN-1:0] nice_i_instr,
input [`E203... | 6.502821 |
module to implement the core's general purpose registers file
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_regfile(
input [`E203_RFIDX_WIDTH-1:0] read_src1_idx,
input [`E203_RFIDX_WIDTH-1:0] read_src2_idx,
output [`E203_XLEN-1:0] read_src1... | 8.470867 |
module to arbitrate the write-back request to regfile
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_wbck(
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
input alu_wbck_i_valid, // Handshake v... | 9.094163 |
module convert the fetch request to ICB (Internal Chip bus)
// and dispatch to different targets including ITCM, ICache or Sys-MEM.
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu_ift2itcm(
input clk,
input rst_n,
input ifu_req_valid, // Han... | 7.563307 |
module to decode the instruction in IFU
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
/////////////... | 7.343249 |
module
//
// ====================================================================
`include "e203_defines.v"
module e203_irq_sync #(
parameter MASTER = 1
) (
input clk,
input rst_n,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
input dbg_irq_a,
output ext_irq_r,
output sft_irq_r,... | 6.874151 |
module to implement ITCM SRAM
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_ITCM //{
module e203_itcm_ram(
input sd,
input ds,
input ls,
input ... | 8.470867 |
module to implement reset control
//
// ====================================================================
`include "e203_defines.v"
module e203_reset_ctrl #(
parameter MASTER = 1
)(
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The core's clk and ... | 8.470867 |
module to implement all SRAMs
//
// ====================================================================
`include "e203_defines.v"
module e203_srams(
`ifdef E203_HAS_ITCM //{
input itcm_ram_sd,
input itcm_ram_ds,
input itcm_ram_ls,
input itcm_ram_cs,
input ... | 8.470867 |
module
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_clint(
input clint_icb_cmd_valid,
output clint_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
input ... | 6.874151 |
module e203_subsys_gfcm (
input test_mode,
input clk0_rst_n,
input clk1_rst_n,
input sel1,
input clk0,
input clk1,
output clkout
);
wire clk0_sel = ~sel1;
wire clk1_sel = sel1;
localparam SYNC_LEVEL = 3;
wire clk0_sync_in;
reg [SYNC_LEVEL-1:0] clk0_sync_r;
always @(pos... | 6.73883 |
module, mainly include the PLL to generate clock
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_hclkgen(
input test_mode,
input hfclkrst,// To reset the PLL Clock
input hfextclk,// The original clock from crystal
input pllbypass ,
... | 6.863834 |
module to implement reset control
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_hclkgen_rstsync (
input clk, // clock
input rst_n_a, // async reset
input test_mode, // test mode
output rst_n
);
localparam RST_SYNC_L... | 8.470867 |
module, need to be replaced with real PLL in ASIC flow
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_pll(
input pll_asleep, // The asleep signal to PLL to power down it
input pllrefclk, // The reference clock into PLL
output plloutclk... | 6.553193 |
module, need to be replaced with real PLL in ASIC flow
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_pllclkdiv(
input rst_n,
input test_mode,
input divby1,
input [5:0] div,
input clk,// The PLL clock
output clkout // The divided C... | 6.553193 |
module to arbitrate the write-back request to regfile
//
// ====================================================================
`include "e203_defines.v"
module e203_wbck_wbck(
// input i_valid,
// output i_ready,
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interfa... | 9.094163 |
module T1_test;
reg clk, reset;
wire [9:0] count;
wire [1:0] in;
wire [3:0] sel, data, Rdata, DEdata;
wire [9:0] a;
wire frame, inframe;
T1 d1 (
clk,
reset,
data,
count,
sel,
in,
a,
frame,
inframe,
Rdata,
DEdata
);
initial begin
cl... | 6.682775 |
module
// DEPARTMENT : MM
// AUTHOR : John Guan
// AUTHOR'S EMAIL : zhiyong.guan@shhic.com
//------------------------------------------------------------------------
// Release history
// VERSION | Date | AUTHOR | DESCRIPTION
// 0.1 | 09/6/16 | John Guan |
//-----------------------------------------... | 8.923686 |
module E2_Counter (
clk,
rst_N,
en_SW,
modulo_SW,
digital_tube_3b,
LED
);
input clk, rst_N;
input en_SW, modulo_SW;
output [20:0] digital_tube_3b;
output LED;
wire [11:0] number_BCD;
wire clk_1Hz;
ClockDivider ClockDivider_inst (
.clkin (clk),
.clkout(clk_1Hz)
... | 6.993363 |
module E3_Sequence (
input clk,
input rst_n,
// input seq_in ,
// output seq_out ,
output LED_seq_out,
output [4:0] LED_seq_in,
output LED_seq_equal
);
wire s_clk_1Hz;
wire s_clk_1Hz_N;
wire s_data;
wire [15:0] sequence_generator;... | 7.381115 |
module e40_rx_pll (
input wire rst, // reset.reset
input wire refclk, // refclk.clk
output wire locked, // locked.export
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
e40_altera_iopll_160_gqiavfy e40_rx_pll (
.rst (rst), // rese... | 7.103732 |
module e40_tx_pll_644 (
input wire rst, // reset.reset
input wire refclk, // refclk.clk
output wire locked, // locked.export
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
e40_altera_iopll_160_h3enegy e40_tx_pll_644 (
.rst (rst), /... | 6.996484 |
module e4Encoder_8bitData_1bitControl (
dataIn,
worstCaseDeviationCode,
encoderOut
);
input [7:0] dataIn;
input [0:0] worstCaseDeviationCode;
output reg [7:0] encoderOut;
reg [7:0] M1encoderOut;
reg [7:0] M1dataIn;
always @(*) begin
case (worstCaseDeviationCode)
1'b0: begin
... | 8.044575 |
module E6_VGA (
input RST_N, // (i)
input CLK, // (i)
output VGA_CLK, // (o)
output VGA_HSYNC, // (o) VGA Horizontal SYNC
output VGA_VSYNC, // (o) VGA Vertical SYNC
output [7:0] VGA_R, // (o) VGA Red
output [7:0] VGA_G, // (o) VGA Green
output ... | 6.796042 |
module e8ba (
A,
B,
Cin,
sum,
carry
);
input [7:0] A, B;
output [7:0] sum;
input Cin;
output carry;
wire w0;
fba e8ba_0 (
A[3:0],
B[3:0],
Cin,
sum[3:0],
w0
);
fba e8ba_1 (
A[7:4],
B[7:4],
w0,
sum[7:4],
carry
);
endmodule
| 6.613006 |
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