code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cr_clkrst_top (
cpurst_b,
forever_cpuclk,
forever_cpuclk_nogated,
forever_jtgclk,
hadrst_b,
pad_cpu_rst_b,
pad_had_jtg_tclk,
pad_had_jtg_trst_b,
pad_had_rst_b,
pad_yy_test_mode,
pll_core_cpuclk,
trst_b
);
input pad_cpu_rst_b;
input pad_had_jtg_tclk;
input pad... | 6.784996 |
module cr_ifu_randclk (
randclk_ibuf_entry_data_mod_en_w16,
randclk_ibuf_pop_mod_en_w3,
randclk_ibuf_push_mod_en_w3
);
output [3:0] randclk_ibuf_entry_data_mod_en_w16;
output randclk_ibuf_pop_mod_en_w3;
output randclk_ibuf_push_mod_en_w3;
wire [3:0] randclk_ibuf_entry_data_mod_en_w16;
wire r... | 6.978987 |
module cr_iu_special (
ctrl_special_ex_sel,
ctrl_special_expt_vec,
ctrl_special_expt_vld,
decd_special_fencei,
special_pcgen_chgflw_vld,
special_rbus_expt_vec,
special_rbus_expt_vld,
special_rbus_flush,
special_rbus_req,
special_retire_inst_wsc,
wb_special_st_uncmplt,
wb_... | 6.573442 |
module cr_rst_top (
cpurst_b,
hadrst_b,
pad_cpu_rst_b,
pad_had_jtg_trst_b,
pad_had_rst_b,
pad_yy_test_mode,
trst_b
);
input pad_cpu_rst_b;
input pad_had_jtg_trst_b;
input pad_had_rst_b;
input pad_yy_test_mode;
output cpurst_b;
output hadrst_b;
output trst_b;
wire cpurst_b;
... | 7.365069 |
module cr_tcipif_dummy_bus (
bmu_tcipif_ibus_acc_deny,
bmu_tcipif_ibus_addr,
bmu_tcipif_ibus_req,
bmu_tcipif_ibus_write,
cpurst_b,
forever_cpuclk,
pad_yy_gate_clk_en_b,
pad_yy_test_mode,
tcipif_bmu_ibus_acc_err,
tcipif_bmu_ibus_data,
tcipif_bmu_ibus_data_vld,
tcipif_bmu_i... | 7.807747 |
module e902_gpio_io ();
`define b_pad_porta tb.x_soc.b_pad_gpio_porta[7:0]
initial begin
wait (`b_pad_porta == 8'hff);
$display("************gpio port a output test pass!************");
force `b_pad_porta = 8'hff;
end
endmodule
| 6.71011 |
module e906_mem_test_tb ();
wire bht_mem_test_pass;
initial begin
#100000;
if (bht_mem_test_pass) begin
$display("*************************************************\n");
$display("*************BHT MEMORY TEST PASS!!!*************\n");
$display("******************************************... | 6.815483 |
module EACAdder #(
parameter PARM_MANT = 23
) (
input [2*PARM_MANT + 1 : 0] CSA_sum_i,
input [2*PARM_MANT + 1 : 0] CSA_carry_i,
input Carry_postcor_i,
input Sub_Sign_i,
input A_Zero_i,
output [2*PARM_MANT + 1 : 0] low_sum_o,
output low_carry_o,
output [2*PARM_MANT + 1 : 0] low_sum_i... | 6.872356 |
module Each_Seven_Segment_Output (
TO_OUTPUT,
ENABLE
);
input [3:0] TO_OUTPUT;
output reg [6:0] ENABLE;
//控制7段数码管通断的编码
parameter ZERO_ENCODE = 7'b0000001;
parameter ONE_ENCODE = 7'b1001111;
parameter TWO_ENCODE = 7'b0010010;
parameter THREE_ENCODE = 7'b0000110;
parameter FOUR_ENCODE = 7'b100110... | 6.820406 |
module eACS_213.v
ACS Block for (2,1,3) backward label decoder
John O'Shea, joshea@emc.com
============================================================*/
`timescale 1 ns/1 ns
module eACS_213 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
ae, clock, rese... | 6.543881 |
module eACS_322.v
ACS Block for efficient (3,2,2) backward label decoder
============================================================*/
`timescale 1 ns/1 ns
module eACS_322 (acs_ppm_out, acs_Bx_out,
acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb,
acs_ppm_inc, HD_inc, acs_ppm_ind, HD_... | 6.570221 |
module eac_cla_adder (
in1,
in2,
cin,
sticky,
effectiveOperation,
sum,
cout
);
`include "parameters.v"
input [ADDER_WIDTH-1:0] in1, in2;
input cin;
input sticky, effectiveOperation;
output [ADDER_WIDTH-1:0] sum;
wire [ADDER_WIDTH-1:0] sum_basic;
wire [ADDER_WIDTH-1:0] sum_plus... | 6.866884 |
module EG_LOGIC_GSRN (
input gsrn,
input sync_clk
);
parameter GSRN_SYNC_SEL = "DISABLE";
parameter USR_GSRN_EN = "DISABLE";
endmodule
| 7.135082 |
module EG_LOGIC_FIFO(
input rst,
input [DATA_WIDTH_W-1:0] di,
output [DATA_WIDTH_R-1:0] do,
input clkw,
input we,
input clkr,
input re,
input ore,
input [2:0] csw,
input [2:0] csr,
output empty_flag,
output aempty_flag,
output full_flag,
output afull_flag
);
parameter DATA_WIDTH_W = 9;
p... | 7.06769 |
module EG_LOGIC_DRAM(
input [DATA_WIDTH_W-1:0] di,
input [ADDR_WIDTH_W-1:0] waddr,
input wclk,
input we,
output [DATA_WIDTH_R-1:0] do,
input [ADDR_WIDTH_R-1:0] raddr
);
parameter DATA_WIDTH_W = 9;
parameter ADDR_WIDTH_W = 10;
parameter DATA_DEPTH_W = 2 ** ADDR_WIDTH_W;
parameter DATA_WIDTH_R = 9;
... | 6.595207 |
module EG_LOGIC_DRAM16X4(
input [3:0] di,
input [3:0] waddr,
input wclk,
input we,
input [3:0]raddr,
output [3:0]do
);
parameter INIT_D0=16'h0000;
parameter INIT_D1=16'h0000;
parameter INIT_D2=16'h0000;
parameter INIT_D3=16'h0000;
endmodule
| 6.595207 |
module EG_LOGIC_MULT (
output [OUTPUT_WIDTH-1:0] p,
input [INPUT_WIDTH_A-1:0] a,
input [INPUT_WIDTH_B-1:0] b,
input cea,
input ceb,
input cepd,
input clk,
input rstan,
input rstbn,
input rstpdn
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_... | 7.076172 |
module EG_PHY_FIFO (
input [8:0] dia,
input [8:0] dib,
input [2:0] csr,
input [2:0] csw,
input we,
input re,
input clkw,
input clkr,
input rst,
input rprst,
input orea,
input oreb,
output [8:0] dob,
output [8:0] doa,
output empty_flag,
output aempty_flag,
... | 7.16841 |
module EG_PHY_MULT18 (
output [17:0] acout,
output [17:0] bcout,
output [35:0] p,
input signeda,
input signedb,
input [17:0] a,
input [17:0] b,
input [17:0] acin,
input [17:0] bcin,
input cea,
input ceb,
input cepd,
input clk,
input rstan,
input rstbn,
inp... | 6.840466 |
module EG_PHY_CONFIG (
output jrstn,
output [1:0] jrti,
output jshift,
output jtck,
output jtdi,
output jupdate,
output [1:0] jscanen,
output jtms,
input [1:0] jtdo,
input [7:0] jtag8_ipa,
input [7:0] jtag8_ipb,
output done,
output highz,
output cclk,
input cc... | 7.409754 |
module EG_PHY_SDRAM_2M_32 (
input clk,
input ras_n,
input cas_n,
input we_n,
input [10:0] addr,
input [1:0] ba,
inout [31:0] dq,
input cs_n,
input dm0,
input dm1,
input dm2,
input dm3,
input cke
);
endmodule
| 6.761017 |
module EG_LOGIC_BRAM (
output [DATA_WIDTH_A-1:0] doa,
output [DATA_WIDTH_B-1:0] dob,
input [DATA_WIDTH_A-1:0] dia,
input [DATA_WIDTH_B-1:0] dib,
input cea,
input ocea,
input clka,
input wea,
input rsta,
input ceb,
input oceb,
input clkb,
input web,
input rstb,
... | 6.912035 |
module eand (
q,
s,
d
);
parameter WIDTH = 8;
output [WIDTH-1 : 0] q;
input s;
input [WIDTH-1 : 0] d;
assign q = {WIDTH{s}} & d;
endmodule
| 7.760379 |
module earb ( /*AUTOARG*/
// Outputs
emwr_rd_en,
emrq_rd_en,
emrr_rd_en,
emm_tx_access,
emm_tx_write,
emm_tx_datamode,
emm_tx_ctrlmode,
emm_tx_dstaddr,
emm_tx_srcaddr,
emm_tx_data,
// Inputs
clock,
reset,
emwr_rd_data,
emwr_empty,
emrq_rd_data,
em... | 7.148395 |
module early_debounce (
input clk,
rst_n,
input sw_low, //active low input
output reg db //active high output
);
//FSM declarations
localparam[2:0] start=3'd0,
one=3'd1,
delay1=3'd2,
delay2=3'd3,
zero=3'd4,
delay3=3'd5;
reg [2:0] state_reg, state_nxt;
/... | 7.827846 |
module mem2 (
clk,
mem_out0,
mem_out1
);
input clk;
output [6:0] mem_out0;
output [6:0] mem_out1;
fakeram45_64x7 mem0 (
.clk(clk),
.rd_out(mem_out0)
);
fakeram45_64x7 mem1 (
.clk(clk),
.rd_out(mem_out1)
);
endmodule
| 6.766342 |
module easy_axilite_master #(
parameter ADDR_LEN = 8,
parameter DATA_LEN = 32
) (
//clk and rst
input wire clk,
input wire rst,
//user interface
input wire [ADDR_LEN-1:0] addr,
input wire [DATA_LEN-1:0] wdata,
input wire [1:0] opcode,
output wire [DATA_LEN-1:0] rdata,
output ... | 7.456014 |
module EASY_AXI_TB ();
reg clk;
reg rst_n;
reg txn_start;
reg [1:0] txn_type; // 00->none 01->write transacation 10->read transacation 11->reserved
wire txn_done;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst_n = 0;
txn_start =... | 7.822025 |
module EA_ALU ( /*------------------ Inputs -------------------*/
DSPCLK,
GO_E,
GO_C,
EX_en,
EX_enc,
R_in_E,
condAM_E,
DIVQ_E,
DIVS_E,
DOUBLE_E,
MTAR_E,
MTAX0_E,
MTAX1_E,
MTAY0_E,
MTAY1_E,
BYPASSR_D,
MFAR_E,
MFAX0_E,
MFAX1_E,
MFAY0_E,
... | 6.910134 |
module eb1_5 #(
parameter WIDTH = 8,
parameter S0 = 3'o0,
parameter S1 = 3'o1,
parameter S2 = 3'o2,
parameter S3 = 3'o3,
parameter S4 = 3'o4
) (
input clk,
reset_n,
input [WIDTH-1:0] t0_data,
input t0_valid,
output logic t0_ready,
o... | 7.965353 |
module eb1 #(
parameter WIDTH = 8
) (
input clk,
reset_n,
input [WIDTH-1:0] t0_data,
input t0_valid,
output logic t0_ready,
output logic [WIDTH-1:0] i0_data,
output logic i0_valid,
input i0_ready
);
// acknowla... | 6.642358 |
module ebaz4205_clock_gen (
input wire i_clk,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(48),
.CLKIN1_PERIOD(30.000300003), // 33.333 MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(... | 6.689995 |
module ebi_dffr #(
parameter WIDTH = 8
) (
input clk,
input rstn,
input [WIDTH-1:0] d,
output [WIDTH-1:0] q
);
reg [WIDTH-1:0] dff_q;
always @(posedge clk) begin
if (rstn) begin
dff_q <= {WIDTH{1'b1}};
end else begin
dff_q <= d;
end
end
a... | 6.751404 |
module eBMU_213.v
Branch Metric Computation Unit for (2,1,3) backward label Viterbi Decoder.
John O'Shea, joshea@emc.com.
===========================================================================*/
module eBMU_213(HD1, HD2, HD3, HD4,
HD5, HD6, HD7, HD8,
HD9, HD10, HD... | 6.502791 |
module ebr8x16 (
clk_i,
rst_i,
clk_en_i,
wr_en_i,
wr_data_i,
addr_i,
rd_data_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
input clk_i;
input rst_i;
input clk_en_i;
input wr_en_i;
input [15:0] wr_data_i;
input [7:0] addr_i;
output [15:0] rd_data_o;
endmodule
| 6.56861 |
module EC11 (
input sys_clk,
input rst_n,
input key_a, //A管脚(模块上的CLK脚)
input key_b, //B管脚(模块上的DT脚)
input key_sw, //D管脚（模块上的SW脚）
output Left_pulse_q, //左旋转脉冲输出
output Right_pulse_q, //右旋转脉冲输出
output SW_pulse, //按动脉冲输出
output [3:0] led_q
);
parameter cnt_500us = 25000; ... | 7.866408 |
module ECC (
input [31:0] data_in,
output [31:0] data_out,
output err_2_bit
);
wire [4:0] xor_sum;
hamming_detect decectionOfErrorBits (
.data_in (data_in),
.err_2bit(err_2_bit),
.xor_sum (xor_sum)
);
hamming_correct correctionOfErrorBits (
.data_in (data_in),
.err_2b... | 6.629333 |
module ecc16_encoder (
enc_in,
parity_out
);
//-------------------------------------------------------------------------------------------------------------------
// Ports
//-------------------------------------------------------------------------------------------------------------------
input [15:0] e... | 7.975848 |
module ecc32_encoder (
enc_in,
parity_out
);
//-------------------------------------------------------------------------------------------------------------------
// Ports
//-------------------------------------------------------------------------------------------------------------------
input [31:0] e... | 7.582242 |
module ecc_decode_2bit (
c,
d,
err_flag
);
input [5:0] c;
output [1:0] d;
output [2:0] err_flag;
reg [1:0] d;
reg [2:0] err_flag;
always @(c) begin
case (c)
// bit distance to codes 0 .. 3
6'h00: {d, err_flag} = {2'b00, 3'b001}; // 0 4 4 4
6'h01: {d, err_flag} = {2'b00, 3'... | 6.559477 |
module ecc_block_tb;
reg [31:0] PH_in;
wire [23:0] PH_out;
wire no_error, corrected_error, error;
reg [23:0] PH_out_exp;
reg error_exp;
reg clk;
integer fd, status;
ecc_block DUT (
PH_in,
PH_out,
no_error,
corrected_error,
error
);
// clock
initial clk = 0;
al... | 6.636742 |
module ecc_buf #(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64
) (
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk,
rst,
rd_d... | 7.908704 |
module ecc_code_control #(
parameter loop = 32,
parameter N = 9216,
parameter K = 8192,
parameter M = 1024
) (
input clk,
input rst_n,
input [ 31:0] data_in, //
input ecc_code_req, //cod
input wr_en, ... | 7.326668 |
module ecc_code_top (
input clk,
input rst_n,
input ecc_code_req,
input wr_en,
input rd_en,
input [31:0] data_in,
output wire ecc_code_rdy,
output wire [31:0] data_out,
output wire ecc_code_over,
... | 8.122251 |
module ecc_controller (
///input ///
clk,
rst_n,
data_in, //32 bits
en,
///output///
addr,
ecc_gen,
reset_gen,
data8, //8 bits
count,
ecc_load,
ecc_ack
);
input clk;
input rst_n;
output [8:0] addr;
input [31:0] data_in;
input en;
output reset_gen;
... | 6.755286 |
module ecc_decode_control #(
parameter loop = 32, //迭代循环次数上限
parameter N = 9216,
parameter K = 8192,
parameter M = 1024
) (
input clk,
input rst_n,
input [31:0] data_in, //flash读出的data，前8192bit为数据位，后1024位为ecc校验位
input ecc_decode_req, //decode开始总信号，decode开始后始终拉高
input wr_en, //相对于... | 8.469211 |
module ecc_decode_top (
input clk,
input rst_n,
input ecc_decode_req,
input wr_en,
input rd_en,
input [31:0] data_in,
output wire ecc_decode_rdy,
output wire [31:0] data_out,
output wire ecc_decode_o... | 7.72706 |
module ecc_dec_fix #(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8
) (
/*AUTOARG*/
// Outputs
rd_data,
ecc_single,
ecc_multiple,
// Inputs... | 7.511075 |
module ecc_enc (
input wire clk, // clock
input wire rstn, // reset
input wire [63:0] data_in, // data input
output reg [63:0] data_out, // data output
output reg [ 7:0] ecc_out // ecc output
);
localparam DATA_WIDTH = 64;
localparam ECC_WIDTH = 8;
localpar... | 7.581754 |
module ecc_enc_dec
//parameters declaration
#(
parameter AMBA_WORD = 32, //size of the bus
parameter AMBA_ADDR_WIDTH=20, //address size changes if we will work with more registers in the future
parameter DATA_WIDTH = 32
) // the data width size for us to work with
//I/O PORT DECLARTION
(
input wire c... | 7.831199 |
module ecc_gen #(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
) (
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial(input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index = 2; index... | 8.012926 |
module ecc_encode_16bit (
d,
c
);
input [15:0] d;
output [21:0] c;
wire [21:0] c;
wire [ 1:0] help_c0;
xor6 help_c0_0 (
help_c0[0],
d[0],
d[1],
d[3],
d[4],
d[6],
d[8]
);
xor6 help_c0_1 (
help_c0[1],
d[10],
d[11],
d[13],
d[15... | 6.509158 |
module ecc_syndrome_16bit (
clk,
rst,
c,
s
);
// optional register on the outputs
// of bits 0..6 and back one level in bit 7
parameter REGISTER = 0;
input clk, rst;
input [21:0] c;
output [5:0] s;
reg [5:0] s;
// 11 terms
wire [1:0] help_s0;
xor6 help_s0_0 (
help_s0[0],
... | 7.891894 |
module ecc_correction_16bit (
s,
e,
fatal
);
input [5:0] s;
output [15:0] e;
output fatal;
wire [15:0] e;
// decode the syndrome
reg [63:0] d;
wire [63:0] dw /* synthesis keep */;
always @(s) begin
d = 64'b0;
d[{!s[5], s[4:0]}] = 1'b1;
end
assign dw = d;
// Identify uncorr... | 6.683387 |
module ecc_raw_data_16bit (
clk,
rst,
c,
d
);
parameter REGISTER = 0;
input clk, rst;
input [21:0] c;
output [15:0] d;
reg [15:0] d;
wire [15:0] d_int;
// pull out the pure data bits
assign d_int = {
c[20],
c[19],
c[18],
c[17],
c[16],
c[14],
c[13],
c[12... | 7.322512 |
module ecc_decode_16bit (
clk,
rst,
c,
d,
no_err,
err_corrected,
err_fatal
);
// optional pipeline registers at the halfway
// point and on the outputs
parameter MIDDLE_REG = 0;
parameter OUTPUT_REG = 0;
input clk, rst;
input [21:0] c;
output [15:0] d;
output no_err, err_co... | 7.755075 |
module ecc_encode_32bit (
d,
c
);
input [31:0] d;
output [38:0] c;
wire [38:0] c;
wire [ 2:0] help_c0;
xor6 help_c0_0 (
help_c0[0],
d[0],
d[1],
d[3],
d[4],
d[6],
d[8]
);
xor6 help_c0_1 (
help_c0[1],
d[10],
d[11],
d[13],
d[15... | 6.524133 |
module ecc_syndrome_32bit (
clk,
rst,
c,
s
);
// optional register on the outputs
// of bits 0..6 and back one level in bit 7
parameter REGISTER = 0;
input clk, rst;
input [38:0] c;
output [6:0] s;
reg [6:0] s;
// 19 terms
wire [3:0] help_s0;
xor6 help_s0_0 (
help_s0[0],
... | 7.891894 |
module ecc_correction_32bit (
s,
e,
fatal
);
input [6:0] s;
output [31:0] e;
output fatal;
wire [ 31:0] e;
// decode the syndrome
reg [127:0] d;
wire [127:0] dw /* synthesis keep */;
always @(s) begin
d = 128'b0;
d[{!s[6], s[5:0]}] = 1'b1;
end
assign dw = d;
// Identify un... | 6.683387 |
module ecc_raw_data_32bit (
clk,
rst,
c,
d
);
parameter REGISTER = 0;
input clk, rst;
input [38:0] c;
output [31:0] d;
reg [31:0] d;
wire [31:0] d_int;
// pull out the pure data bits
assign d_int = {
c[37],
c[36],
c[35],
c[34],
c[33],
c[32],
c[30],
c[29... | 7.322512 |
module ecc_decode_32bit (
clk,
rst,
c,
d,
no_err,
err_corrected,
err_fatal
);
// optional pipeline registers at the halfway
// point and on the outputs
parameter MIDDLE_REG = 0;
parameter OUTPUT_REG = 0;
input clk, rst;
input [38:0] c;
output [31:0] d;
output no_err, err_co... | 8.172401 |
module ecc_correction_64bit (
s,
e,
fatal
);
input [7:0] s;
output [63:0] e;
output fatal;
wire [63:0] e;
// decode the lower part of syndrome
reg [63:0] d;
wire [63:0] dw /* synthesis keep */;
always @(s) begin
d = 64'b0;
d[s[5:0]] = 1'b1;
end
assign dw = d;
// Identify u... | 6.683387 |
module ecc_raw_data_64bit (
clk,
rst,
c,
d
);
parameter REGISTER = 0;
input clk, rst;
input [71:0] c;
output [63:0] d;
reg [63:0] d;
wire [63:0] d_int;
// pull out the pure data bits
assign d_int = {
c[70],
c[69],
c[68],
c[67],
c[66],
c[65],
c[64],
c[62... | 7.322512 |
module ecc_decode_64bit (
clk,
rst,
c,
d,
no_err,
err_corrected,
err_fatal
);
// optional pipeline registers at the halfway
// point and on the outputs
parameter MIDDLE_REG = 0;
parameter OUTPUT_REG = 0;
input clk, rst;
input [71:0] c;
output [63:0] d;
output no_err, err_co... | 8.12734 |
module ecc_encode_8bit (
d,
c
);
input [7:0] d;
output [12:0] c;
wire [12:0] c;
assign c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6];
assign c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6];
assign c[2] = d[0];
assign c[3] = d[1] ^ d[2] ^ d[3] ^ d[7];
assign c[4] = d[1];
assign c[5] = d[2];
assign ... | 7.2659 |
module ecc_syndrome_8bit (
clk,
rst,
c,
s
);
// optional register on the outputs
// of bits 0..6 and back one level in bit 7
parameter REGISTER = 0;
input clk, rst;
input [12:0] c;
output [4:0] s;
reg [4:0] s;
// 6 terms
wire [0:0] help_s0;
xor6 help_s0_0 (
help_s0[0],
... | 7.891894 |
module ecc_correction_8bit (
s,
e,
fatal
);
input [4:0] s;
output [7:0] e;
output fatal;
wire [ 7:0] e;
// decode the syndrome
reg [31:0] d;
wire [31:0] dw /* synthesis keep */;
always @(s) begin
d = 32'b0;
d[{!s[4], s[3:0]}] = 1'b1;
end
assign dw = d;
// Identify uncorrec... | 6.683387 |
module ecc_raw_data_8bit (
clk,
rst,
c,
d
);
parameter REGISTER = 0;
input clk, rst;
input [12:0] c;
output [7:0] d;
reg [7:0] d;
wire [7:0] d_int;
// pull out the pure data bits
assign d_int = {c[11], c[10], c[9], c[8], c[6], c[5], c[4], c[2]};
// conditional output register
gen... | 7.322512 |
module ecc_decode_8bit (
clk,
rst,
c,
d,
no_err,
err_corrected,
err_fatal
);
// optional pipeline registers at the halfway
// point and on the outputs
parameter MIDDLE_REG = 0;
parameter OUTPUT_REG = 0;
input clk, rst;
input [12:0] c;
output [7:0] d;
output no_err, err_corr... | 7.946328 |
module ecc_merge_enc #(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
... | 7.15222 |
module ECC_tb ();
reg [31:0] data_in_tb;
reg [31:0] data_out_tb_exp;
wire [31:0] data_out_tb_actual;
reg err_2_bit_tb_exp;
wire err_2_bit_tb_actual;
ECC DUT (
.data_in (data_in_tb),
.data_out (data_out_tb_actual),
.err_2_bit(err_2_bit_tb_actual)
);
integer n_tests, n_tests_passed;
... | 6.552995 |
module ecdhp384_wrapper (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [ 7:0] address,
input wire [31:0] write_data,
output wire [31:0] read_data
);
//
// Address Decoder
//
localparam ADDR_MSB_REGS = 1'b0;
localparam ADDR_MSB_CORE = 1'b1;
w... | 7.229088 |
module ecdsa256 (
input wire clk,
input wire rst_n,
input wire next,
output wire valid,
input wire bus_cs,
input wire bus_we,
input wire [ 4:0] bus_addr,
input wire [31:0] bus_data_wr,
output wire [31:0] bus_data_rd
);
//
// Memory Banks
//
localparam [... | 7.09155 |
module ecdsa256_core_top (
input wire clk,
input wire rst_n,
input wire next,
output wire valid,
input wire bus_cs,
input wire bus_we,
input wire [ 4:0] bus_addr,
input wire [31:0] bus_data_wr,
output wire [31:0] bus_data_rd
);
//
// Memory Banks
//
loc... | 7.263624 |
module ecdsa256_modulus_distmem (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
(* ram_style="distributed" *)
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_add... | 7.018747 |
module ecdsa384 (
input wire clk,
input wire rst_n,
input wire next,
output wire valid,
input wire bus_cs,
input wire bus_we,
input wire [ 5:0] bus_addr,
input wire [31:0] bus_data_wr,
output wire [31:0] bus_data_rd
);
//
// Memory Banks
//
localparam [... | 7.696869 |
module ecdsa384_modulus_distmem (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
(* ram_style="distributed" *)
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_add... | 7.217913 |
module ecdsa384_wrapper (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [ 6:0] address,
input wire [31:0] write_data,
output wire [31:0] read_data
);
//
// Address Decoder
//
localparam ADDR_MSB_REGS = 1'b0;
localparam ADDR_MSB_CORE = 1'b1;
w... | 7.492398 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
modul... | 7.349016 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
wire anot, bnot, cnot, dnot, w1, w2, w3, w4;
not (anot, a);
not (bnot, b);
not (cnot, c);
not (dnot, d);
and (w1, c, d);
and (w2, anot, bnot, c);
or (out_sop, w1, w2);
or (w3, d, an... | 7.203305 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
//2's complement for a binary number is found by inverting the numbers and adding 1
// i.e: 2'scomplement of 0011 is : 1100+0001 = 1101
//
//Also remember that MSB of the 2's complement number repre... | 7.203305 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[3] = c & d;
assign mux_in[2] = ~d;
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg state, next_state;
parameter [3:0] A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
always @(*) begin
case (state)
A:
if (s == 3'b001) begin
next_state = B;... | 7.203305 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
reg [7:0] Q = 0;
always @(posedge clk) begin
if (enable) begin
Q <= {Q[6:0], S};
end
end
assign Z = Q[{A, B, C}];
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | (~a) & (~b) & c;
assign out_pos = c & ((~a) | (~c) | d) & (a | (~b) | (~c) | d);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
... | 7.203305 |
module top_module (
input clk,
input j,
input k,
output Q
);
wire old = Q;
always @(posedge clk) begin
if (j ^ k) begin
Q = j;
end else begin
Q = j ? ~old : old;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
parameter idle = 2'd0, one = 2'd1, two = 2'd2, three = 2'd3;
reg [1:0] state, next_state;
always @(*) begin
case ({
state, x
})
{idle, 1'b0} : next_state = idle;
{idl... | 7.203305 |
module top_module (
input clk,
input aresetn,
input x,
output reg z
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter S=0, S1=1, S10=2;
... | 7.203305 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
EightBitsAdder ins (
a,
b,
s,
overflow
);
endmodule
| 7.203305 |
module FullAdder (
input a,
b,
cin,
output sum,
cout
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.610141 |
module EightBitsAdder (
input [7:0] x,
input [7:0] y,
output [7:0] s,
output overflow
);
wire [7:0] cout1;
FullAdder ins0 (
x[0],
y[0],
0,
s[0],
cout1[0]
);
FullAdder ins1 (
x[1],
y[1],
cout1[0],
s[1],
cout1[1]
);
FullAdder ins2 (
... | 6.935249 |
module top_module (
input clk,
input x,
output z
);
reg out1 = 0, out2, out3;
initial z = 1;
always @(posedge clk) begin
out1 = x ^ out1;
out2 = x & ~out2;
out3 = x | ~out3;
z = ~(out1 | out2 | out3);
end
endmodule
| 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter S0 = 0, S1 = 1, S2 = 2;
reg [1:0] state;
reg [1:0] next_state;
always @(*) begin
case (state)
S0: begin
next_state = x ? S1 : S0;
z = 1'b0;
end
S1: begin
next_state = x... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
localparam S0 = 0, S1 = 1;
reg [1:0] state;
reg [1:0] next_state;
always @(*) begin
next_state = 2'b0;
case (1'b1)
state[S0]: begin
next_state[S1] = x ? 1'b1 : 1'b0;
next_state[S0] = x ? 1'b0 : 1'... | 7.203305 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
wire [3:0] Q_tmp;
assign c_enable = enable;
assign c_d = c_load ? 1 : 0;
always @(posedge clk) begin
if (reset) begin
Q <= 1;
Q_tmp <= 1;
... | 7.203305 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
);
wire [3:0] q0, q1, q2;
bcdcount counter0 (
.clk(clk),
.reset(reset),
.enable(c_enable[0]),
.Q(q0)
);
bcdcount counter1 (
.clk(clk),
.reset(reset),
.enable(c_enable[1... | 7.203305 |
module top_module (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
always @(posedge clk) begin
if (reset) Q <= 4'd0;
else if (enable) begin
if (Q == 9) Q <= 4'd0;
else Q <= Q + 1'b1;
end
end
endmodule
| 7.203305 |
module ECE429_ALU (
inputA,
inputB,
inputSHAMT,
ALUop,
takeBranch,
ALUOutput
);
input [0:31] inputA;
input [0:31] inputB;
input [0:4] inputSHAMT;
input [0:`ALUOP_LEN_BITS-1] ALUop;
output takeBranch;
output [0:31] ALUOutput;
reg takeBranch;
reg [0:31] ALUOutput;
always @(in... | 6.580381 |
module ECE429_Decode_tb ();
reg clock;
reg parseEnable;
wire[0:31] parseAddr; // A 32-bit address to put into the memory
wire[0:31] memAddr;
wire[0:31] memData; // A 32-bit piece of data to write to memory
wire[0:1] parseAccessSize; // The access size to write to the memory using
wire[0:1] memAccessS... | 8.473058 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.