code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ECE429_Fetch (
clk_in,
pc_out,
pc_decode_out,
rw_out,
stall_in,
access_size_out
);
input clk_in;
input stall_in;
output [0:31] pc_out;
output [0:31] pc_decode_out;
output rw_out; // 0 to read, 1 to write
output [0:1] access_size_out; // 11 for word, 10 for half-word, 01/00... | 6.680361 |
module ECE429_Fetch (
clk_in,
pc_in,
pc_out,
pc_decode_out,
rw_out,
stall_in,
access_size_out
);
input clk_in;
input [0:31] pc_in;
input stall_in;
output [0:31] pc_out;
output [0:31] pc_decode_out;
output rw_out; // 0 to read, 1 to write
output [0:1] access_size_out; // 11 ... | 6.680361 |
module ECE429_Fetch_tb ();
reg clock;
reg parseEnable;
wire[0:31] parseAddr; // A 32-bit address to put into the memory
wire[0:31] memAddr;
wire[0:31] memData; // A 32-bit piece of data to write to memory
wire[0:1] parseAccessSize; // The access size to write to the memory using
wire[0:1] memAccessSi... | 8.615733 |
module ECE429_Fetch_tb ();
reg clock;
reg parseEnable;
wire[0:31] parseAddr; // A 32-bit address to put into the memory
wire[0:31] memAddr;
wire[0:31] memData; // A 32-bit piece of data to write to memory
wire[0:1] parseAccessSize; // The access size to write to the memory using
wire[0:1] memAccessSi... | 8.615733 |
module ECE429_Memory (
clock,
address,
datain,
dataout,
access_size,
r_w
);
input clock;
input [0:31] address;
input [0:31] datain;
input [0:1] access_size; // 11 for word, 10 for half-word, 01/00 byte
input r_w; // 0 to read, 1 to write
output [0:31] dataout;
wire [0:31] mod_... | 7.1542 |
module ECE429_Memory (
clock,
address,
datain,
dataout,
access_size,
r_w
);
input clock;
input [0:31] address;
input [0:31] datain;
input [0:1] access_size; // 11 for word, 10 for half-word, 01/00 byte
input r_w; // 0 to read, 1 to write
output [0:31] dataout;
wire [0:31] mod_... | 7.1542 |
module ECE429_Memory_tb ();
reg clock;
reg [0:31] address;
reg [0:31] datain;
reg [0:1] access_size; // 11 for word, 10 for half-word, 01/00 byte
reg r_w; // 0 to read, 1 to write
wire [0:31] dataout;
initial begin
$display("time\tclock\taddress\tdatain\taccess_size\tr_w\tdataout");
$monitor... | 7.1542 |
module ECE429_RegFile (
clock,
rsIn,
rsOut,
rtIn,
rtOut,
rdIn,
rd_dataIn,
control
);
input clock;
input [0:4] rsIn;
input [0:4] rtIn;
input [0:4] rdIn;
input [0:`CONTROL_BITS_END] control;
input [0:31] rd_dataIn;
output [0:31] rsOut;
output [0:31] rtOut;
reg [0:31] ... | 6.985179 |
module ECE429_SRECParser_tb ();
reg clock;
reg parseEnable;
wire[0:31] parseAddr; // A 32-bit address to put into the memory
wire[0:31] memAddr;
wire[0:31] memData; // A 32-bit piece of data to write to memory
wire[0:1] parseAccessSize; // The access size to write to the memory using
wire[0:1] memAcc... | 8.322532 |
module tb_top ();
parameter CLK_PHASE = 5;
//---------------------------------------------------------------------------
// General
//
reg clk;
wire reset;
reg xxx__dut__go;
//---------------------------------------------------------------------------
// Interface
//
dut_ifc dut_if (.clk(cl... | 6.964239 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
| 7.203305 |
module func9 (
x1,
y1,
zero1,
x2,
y2,
zero2,
x3,
y3,
zero3
);
input [`WIDTH:0] x1, y1, x2, y2;
input zero1; // asserted if P1 == 0
input zero2; // asserted if P2 == 0
output [`WIDTH:0] x3, y3;
output zero3; // asserted if P3 == 0
assign zero3 = zero1 & zero2;
genva... | 7.410522 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module func1 (
S,
R,
q,
out
);
input [`WIDTH+2:0] S, R;
input [1:0] q;
output [`WIDTH+2:0] out;
wire [`WIDTH+2:0] t;
func4 f (
R,
q,
t
); // t == q*R
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_sub s1 (
S[i+1:i],
... | 7.258845 |
module func2 (
A,
out
);
input [`WIDTH+2:0] A;
output [`WIDTH+2:0] out;
assign out = {A[`WIDTH:0], 2'd0};
endmodule
| 6.95158 |
module func4 (
A,
aa,
C
);
input [`WIDTH+2:0] A;
input [1:0] aa;
output [`WIDTH+2:0] C;
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_mult m (
A[i+1:i],
aa,
C[i+1:i]
);
end
endgenerate
endmodule
| 7.077584 |
module which generates the output telling the maximum bits required to represent any of the four input samples. Used in other submodules.
// DATE : 27/05/2020
//================================================================
module Bits_required (Bits_req, sample_1,sample_2,sample_3,sample_4,ecgidx);
//=====... | 6.687535 |
module which generates the output signal telling whether the Data part in the encoded ECG is active or not. This signal is used by many other submodules.
// DATE : 26/05/2020
//===================================================
module ecg_DataActive (DataActive,ecgidx,sub_sample_info,component_idx,component_skip);
... | 6.687535 |
module which generates the output signal telling whether the Group skip flag is kept active in encoded ECG. This signal is used by other submodules.
// DATE : 26/05/2020
//===================================================
module ecg_skip (Data_Active,Bits_req,Group_Skip_Flag);
//================================... | 6.687535 |
module ECG (
CLK_50M,
ADC_OUT,
DAC_CS,
DAC_CLR,
SPI_SCK,
AMP_CS,
SPI_MOSI,
AD_CONV,
LED,
LCD_DB,
LCD_E,
LCD_RS,
LCD_RW
);
input CLK_50M;
input ADC_OUT;
output DAC_CS;
output DAC_CLR;
output SPI_SCK;
output SPI_MOSI;
output AMP_CS;
output AD_CONV;
... | 7.752812 |
module Echo (
input clk,
input rst,
input AUD_BCLK,
input AUD_DACLRCK,
input AUD_ADCLRCK,
input [31:0] audioIn,
output reg [31:0] audioOut
);
reg [14:0] currentSample;
reg [14:0] lastSample;
//RAM Module
//I forget why I named it Rambo but Rambo it is
reg [14:0] address;
reg ... | 6.636366 |
module echowire2 (
input wire dtr,
input wire rts,
input wire rx,
input wire tx2,
output wire tx,
output wire rx2,
output wire D1,
output wire D2
);
//-- Sacar senal dtr y rts por los leds
assign D1 = dtr;
assign D2 = rts;
//-- Sacar señales tx y rx al exterior
assign r... | 6.99006 |
module echo_integration_testbench ();
parameter SYSTEM_CLK_PERIOD = 8;
parameter SYSTEM_CLK_FREQ = 125_000_000;
reg sys_clk = 0;
reg sys_rst = 0;
always #(SYSTEM_CLK_PERIOD / 2) sys_clk <= ~sys_clk;
// UART Signals between the on-chip and off-chip UART
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
// Off-chip... | 6.73328 |
module echo_server_application_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 6.815584 |
module echo_server_application_m_axis_close_connection_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] closeConnection_V_V_din,
output w... | 6.815584 |
module echo_server_application_m_axis_close_connection_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input ... | 6.815584 |
module echo_server_application_m_axis_close_connection_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master s... | 6.815584 |
module echo_server_application_m_axis_listen_port_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] listenPort_V_V_din,
output wire ... | 6.815584 |
module echo_server_application_m_axis_listen_port_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 6.815584 |
module echo_server_application_m_axis_listen_port_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_server_application_m_axis_open_connection_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [47:0] TDATA,
// User signals
input wire [47:0] openConnection_V_din,
output wire ... | 6.815584 |
module echo_server_application_m_axis_open_connection_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master si... | 6.815584 |
module echo_server_application_m_axis_read_package_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [31:0] TDATA,
// User signals
input wire [31:0] readRequest_V_din,
output wire ... | 6.815584 |
module echo_server_application_m_axis_read_package_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_server_application_m_axis_tx_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input... | 6.815584 |
module echo_server_application_m_axis_tx_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
o... | 6.815584 |
module echo_server_application_m_axis_tx_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] txMetaData_V_V_din,
output wire ... | 6.815584 |
module echo_server_application_m_axis_tx_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 6.815584 |
module echo_server_application_m_axis_tx_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_server_application_s_axis_listen_port_status_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [0:0] listenPortStatus_V_dout,
output wire ... | 6.815584 |
module echo_server_application_s_axis_listen_port_status_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input... | 6.815584 |
module echo_server_application_s_axis_listen_port_status_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master... | 6.815584 |
module echo_server_application_s_axis_notifications_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [87:0] TDATA,
// User signals
output wire [80:0] notifications_V_dout,
output wire ... | 6.815584 |
module echo_server_application_s_axis_notifications_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side... | 6.815584 |
module echo_server_application_s_axis_open_status_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [23:0] TDATA,
// User signals
output wire [16:0] openConStatus_V_dout,
output wire ... | 6.815584 |
module echo_server_application_s_axis_open_status_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_server_application_s_axis_rx_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
outpu... | 6.815584 |
module echo_server_application_s_axis_rx_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
o... | 6.815584 |
module echo_server_application_s_axis_rx_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] rxMetaData_V_V_dout,
output wire ... | 6.815584 |
module echo_server_application_s_axis_rx_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 6.815584 |
module echo_server_application_s_axis_rx_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_server_application_s_axis_tx_status_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [23:0] TDATA,
// User signals
output wire [16:0] txStatus_V_V_dout,
output wire tx... | 6.815584 |
module echo_server_application_s_axis_tx_status_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 6.815584 |
module echo_server_application_s_axis_tx_status_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
... | 6.815584 |
module echo_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
localparam BAUD_RATE = 115_200;
localparam BAUD_PERIOD = 1_000_000_000 / BAUD_RATE; // 8680.55 ns
localparam CHAR0 = 8'h61; // ~ 'a'
localparam NUM_CHARS = 10;
localp... | 7.705315 |
module for icache and dcache.
*/
module eco32f_cache (
input rst,
input clk,
input [31:0] read_addr,
input [31:0] match_addr,
output [31:0] read_data,
output miss,
input [31:0] write_addr,
input [31:0] write_data,
input write_en,
input invalidate
);
wire [20:0] ta... | 6.956043 |
module eco32f_mmu (
input rst,
input clk,
input [31:0] psw,
// Read/write access to tlbs
input [ 4:0] tlb_index,
input [31:0] tlb_entry_hi,
input tlb_entry_hi_we,
input [31:0] tlb_entry_lo,
input tlb_entry_lo_we,
output [31:0] tlb_entry_hi_rd_data,
output... | 6.590325 |
module eco32f_simple_dpram_sclk #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter ENABLE_BYPASS = 1
) (
input clk,
input [ADDR_WIDTH-1:0] raddr,
input re,
input [ADDR_WIDTH-1:0] waddr,
input we,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout... | 7.336391 |
module.
Copyright (C) 2022 Ken Lowe
Econet_AtoMMC is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is ... | 7.356259 |
module ECP (
input wire x1,
x2,
x3,
x4,
input wire cin,
output wire cout,
output wire sum,
output wire carry
);
wire s;
assign cout = (x1 ^ x2) & x3 | x1 & x2;
assign s = x1 ^ x2 ^ x3;
assign sum = s ^ x4 ^ cin;
assign carry = (s ^ x4) & cin | s & x4;
endmodule
| 7.267249 |
module AND2 (
A,
B,
Z
); //synthesis syn_black_box
input A;
input B;
output Z;
endmodule
| 6.989894 |
module BBPU (
I,
T,
O,
B
); //synthesis syn_black_box black_box_pad_pin="B"
input I;
input T;
output O;
inout B;
endmodule
| 6.911182 |
module MUX161 (
D15,
D14,
D13,
D12,
D11,
D10,
D9,
D8,
D7,
D6,
D5,
D4,
D3,
D2,
D1,
D0,
SD4,
SD3,
SD2,
SD1,
Z
); //synthesis syn_black_box
input D15;
input D14;
input D13;
input D12;
input D11;
input D10;
input D9;
input ... | 6.55909 |
module MUX21 (
D1,
D0,
SD,
Z
); //synthesis syn_black_box
input D1;
input D0;
input SD;
output Z;
endmodule
| 6.794245 |
module MUX321 (
D31,
D30,
D29,
D28,
D27,
D26,
D25,
D24,
D23,
D22,
D21,
D20,
D19,
D18,
D17,
D16,
D15,
D14,
D13,
D12,
D11,
D10,
D9,
D8,
D7,
D6,
D5,
D4,
D3,
D2,
D1,
D0,
SD5,
SD4,
SD3,... | 6.920809 |
module NR2 (
A,
B,
Z
); //synthesis syn_black_box
input A;
input B;
output Z;
endmodule
| 6.853296 |
module OR2 (
A,
B,
Z
); //synthesis syn_black_box
input A;
input B;
output Z;
endmodule
| 6.754634 |
module LUT5 (
Z,
A,
B,
C,
D,
E
); //synthesis syn_black_box
parameter [31:0] init = 32'h00000000;
input A;
input B;
input C;
input D;
input E;
output Z;
endmodule
| 6.595582 |
module ROM16X1A (
AD3,
AD2,
AD1,
AD0,
DO0
); //synthesis syn_black_box
parameter [15:0] initval = 16'h0000;
input AD3;
input AD2;
input AD1;
input AD0;
output DO0;
endmodule
| 6.716296 |
module ROM256X1A (
AD7,
AD6,
AD5,
AD4,
AD3,
AD2,
AD1,
AD0,
DO0
); //synthesis syn_black_box
parameter [255:0] initval = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input AD7;
input AD6;
input AD5;
input AD4;
input AD3;
input AD2;
input AD... | 6.523574 |
module CIDDLLB (
CLKI,
CLKFB,
RSTN,
ALUHOLD,
INCI,
GRAYI5,
GRAYI4,
GRAYI3,
GRAYI2,
GRAYI1,
GRAYI0,
CLKOP,
CLKOS,
LOCK
); //synthesis syn_black_box
input CLKI, CLKFB, RSTN, ALUHOLD, INCI;
input GRAYI5, GRAYI4, GRAYI3, GRAYI2, GRAYI1, GRAYI0;
output CLKOP, CL... | 6.544042 |
module IDDRXD (
D,
SCLK,
ECLKDQSR,
DDRCLKPOL,
QA,
QB
); //synthesis syn_black_box
input D, SCLK, ECLKDQSR, DDRCLKPOL;
output QA, QB;
parameter SCLKLATENCY = 1;
parameter DELAYMODE = "ALIGNED";
endmodule
| 6.528332 |
module ecp5_pll (CLKI, RST, CLKOP, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute ecp5_pll dont_touch true
input wire CLKI;
input wire RST;
output wire CLKOP;
output wire LOCK;
wire REFCLK;
wire CLKOP_t;
wire scuba_vhi;
wire scuba_vlo;
VHI s... | 6.550864 |
module implements the md5
* hashing accelerator.
*
* Target Board: Lattice ECP5-5G Evaluation Board
*
* Modified by : Patrick Lloyd
* Original by : Brandon Blodget
* Create Date : 11/3/2018
*
* Updates:
* 01/25/2019 : Updated to support parallel 8 interface
* 02/04/2019 : Project modified to synthesize for ECP5
*
***... | 7.842559 |
module ecpddrcmd #(parameter NWIDE = 4)
(input wire i_clk, i_reset,
input wire i_memclk,
input wire [2*NWIDE-1:0] i_data,
output wire [NWIDE-1:0] o_pins);
generate for(k=0; k<NWIDE; k=k+1)
begin
/*
OSHX2A
gencmd(
.SCLK(i_clk),
.RST(i_reset),
.D0(NWIDE+k),
.D1(k),
//
.ECLK(i_mem_clk),
... | 6.823859 |
module ecuMesh #(
parameter X = 2,
Y = 2,
data_width = 129,
x_size = 1,
y_size = 1,
total_width = (x_size + y_size + data_width)
) (
input wire clk,
input wire rst,
//PE interfaces
output wire [ (X*Y-1)-1:0] r... | 6.971993 |
module ec_8 (
input [2:0] err_in,
input cin,
input carry_in,
output cout,
output carry_out,
output sout
);
wire summ;
cprs_3_2 U0 (
.in (err_in),
.out({carry_out, summ})
);
assign {cout, sout} = summ + cin + carry_in;
endmodule
| 6.634201 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module ed25519_mul_TOP (
input ICLK,
input IRSTN,
input IEN,
output OREADY,
output [2:0] OKADDR,
output [2:0] OQYADDR,
output OQYWREN,
input [31:0] IK,
output [31:0] OQY
);
ed25519_mul U1 (
.iClk (ICLK),
.iRstn(IRSTN),
.iEn(IEN),
.oReady(OREADY),
... | 7.202043 |
module ed25519_mul_TOP_wrapper (
input clk,
input rst_n,
input ena,
output rdy,
output [2:0] k_addr,
output [2:0] qy_addr,
output qy_wren,
input [31:0] k_din,
output [31:0] qy_dout
);
ed25519_mul_TOP U1_TOP (
.ICLK (clk),
.IRSTN(rst_n),
.IEN(ena),
.OREA... | 7.202043 |
module ed25519_sign_S_core_TOP (
input ICLK,
input IRST,
input IEN,
output OREADY,
output ODONE,
input [250:0] IHASHD_KEY,
input [511:0] IHASHD_RAM,
input [511:0] IHASHD_SM,
output [252:0] OSIGN
);
ed25519_sign_S_core uut (
.iClk (ICLK),
.iRst (IRST),
.iEn ... | 7.698814 |
module ed25519_sign_S_core_TOP_wrapper (
input clk,
input rst,
input core_ena,
output core_ready,
output core_comp_done,
input [511:0] hashd_key,
input [511:0] hashd_ram,
input [511:0] hashd_sm,
output [255:0] core_S
);
wire [252:0] sign;
ed25519_sign_S_core_TOP U1_TOP (
... | 7.698814 |
module ed25519_wrapper (
input clk,
input rst_n,
input cs,
input we,
input [ 4:0] address,
input [31:0] write_data,
output [31:0] read_data
);
//
// Address Decoder
//
localparam ADDR_MSB_REGS = 1'b0;
localparam ADDR_MSB_CORE = 1'b1;
wire [ 0:0] addr_msb = address[4];
wi... | 6.64212 |
module EDAC_SDRAM_Controller_Demo_altpll_0_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// s... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_altpll_0_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
EDAC_SDRAM_Controller_Demo_altpll_0_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_altpll_0_altpll_oub2 (
areset,
clk,
inclk,
locked
) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_altpll_0 (
address,
areset,
c0,
c1,
clk,
configupdate,
locked,
phasecounterselect,
phasedone,
phasestep,
phaseupdown,
read,
readdata,
reset,
scanclk,
scanclkena,
scandata,
scandataout,
scandone,
write,
... | 6.718188 |
module EDAC_SDRAM_Controller_Demo (
debug_err_counter_o,
debug_err_detect_o,
debug_healing_proc_run_o,
debug_mem_ready_o,
debug_scrubbing_proc_run_o,
debug_voted_data_o,
sdram_cke_o,
sdram_bank_o,
sdram_addr_o,
sdram_cs_o,
sdram_ras_o,
sdram_cas_o,
sdram_we_o,
sdr... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctr... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_f... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output ... | 6.718188 |
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