code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
o... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31... | 6.718188 |
module EDAC_SDRAM_Controller_Demo_onchip_memory2_0 (
// inputs:
address,
address2,
byteenable,
... | 6.718188 |
module edac_top (
clk,
reset_b,
Data_valid_08p,
DataParity_valid_12p,
Data_in_08p,
Data_out_10p,
Parity_out_10p,
Data_out_14p,
EDACerr1_14p,
EDACerr2_14p,
DataParity_in_12p
);
// local signals
parameter k = 128;
parameter r = 9;
input wire clk, reset_b, Data_valid_08p... | 8.764558 |
module eda_task_FIFO (
input SYSCLK,
input RST_B,
input WR_EN,
input RD_EN,
input [7:0] FIFO_IN,
output reg [7:0] FIFO_OUT,
output EMPTY,
output FULL
);
reg [7:0] stack[3:0];
reg [1:0] cnt;
always @(posedge SYSCLK or negedge RST_B) begin
if (~RST_B) begin
stack[0] <= 8... | 6.963162 |
module eda_task_FIFO_tb ();
reg SYSCLK;
reg RST_B;
reg WR_EN;
reg RD_EN;
reg [7:0] FIFO_IN;
wire EMPTY;
wire FULL;
wire [7:0] FIFO_OUT;
eda_task_FIFO eda_task_FIFO_test (
SYSCLK,
RST_B,
WR_EN,
RD_EN,
FIFO_IN,
FIFO_OUT,
EMPTY,
FULL
);
initial SYSC... | 6.963162 |
module EDG (
input clk,
rst,
y,
output p
);
reg [1:0] state, next_state;
parameter S0 = 0, S1 = 1, S2 = 2;
//output logic
assign p = (state == S1);
//state logic
always @(posedge clk, posedge rst) begin
if (rst) state <= S0;
else state <= next_state;
end
//next state logic
a... | 7.105668 |
module Edgcombe_SHA_algo_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXI
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 4
) (
// Users to add ... | 7.662392 |
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
wire [31:0] pre;
always @(posedge clk) begin
if (reset) begin
out <= 32'b0;
end else begin
out <= out | (pre & ~in);
end
pre <= in;
end
endmodule
| 7.203305 |
module edge_detect
(
input wire clk, reset, level;
output tick;
)
localparam [1:0] zero=2'b00, edg=2'b01, one=2'b10;
reg [1:0] state_reg, state_next;
always @(posedge clk or posedge reset) begin
if (reset)
state_reg <= zero;
else
state_reg <= state_next
end
always @(*) begin
state_next = state_reg;
tick = 1'... | 7.110712 |
module Edge (
input wire nReset, // Common to all
input wire Clk,
input wire [7:0] PixelIn,
input wire FrameIn,
input wire LineIn,
input wire [7:0] Width,
output reg [7:0] PixelOut,
output reg FrameOut,
output reg LineOut
);
// Buffe... | 7.594537 |
module EdgeCalculator (
clock,
reset,
enable,
donedge,
xcenter,
ycenter,
depth,
donesquare,
xstart,
xend,
ystart,
yend,
etype
);
input clock, reset, enable, donedge;
input [8:0] xcenter, ycenter;
input [5:0] depth;
output donesquare;
output [2:0] etype; /... | 6.596792 |
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
// 通过outval将输出进行锁存
reg [31:0] last, outval;
always @(posedge clk) begin
if (reset) begin
// 同步reset，可以用非阻塞赋值
last <= in;
outval <= 32'd0;
out <= 0;
end else begin
// 这里需要用阻塞赋值，否... | 7.203305 |
module edgeD (
clk,
rst,
w,
z
);
input clk, rst, w;
output z;
reg [1:0] state, nextState;
// States Encoding
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;
// Next state Logic
always @(w or state)
case (state)
A: if (w) nextState = B;
else nextState = A;
B: if (w) nextSt... | 7.589167 |
module edgedet (
input wire clk,
input wire i,
output wire o
);
reg last_i;
always @(posedge clk) last_i <= i;
assign o = (!last_i) && i;
endmodule
| 7.325958 |
module is
// fully moore-tyle, the output is isolated from the
// input by a single flip-flop.
// Params: width: The number of samples of the
// input signal to examine
// upwidth: The number of consecutive high
// samples which must appear before
// the edge is signaled.
// type: number type
// ... | 7.39478 |
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] last;
always @(posedge clk) begin
last <= in;
anyedge <= in ^ last;
end
endmodule
| 7.203305 |
module readCounters (
clk,
n_rst,
executeRead,
rowCount,
colCount,
offsetCount,
cols_rollover_flag
);
output [1:0] rowCount;
output [9:0] colCount;
output [8:0] offsetCount;
input clk, n_rst, executeRead;
output cols_rollover_flag;
wire rows_rollover_flag, cols_rollover_flag_Temp... | 7.313243 |
module edgeDetector (
input wire clk,
reset,
input wire level,
output reg out
);
localparam [1:0] // 3 states are required for Moore
zeroMoore = 2'b00, edgeMoore = 2'b01, oneMoore = 2'b10, delay = 2'b11;
reg [1:0] stateMoore_reg, stateMoore_next;
always @(posedge clk, posedge reset) begin... | 8.299453 |
module: EdgeDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EdgeDetectorTb;
// Outputs
wire ;
// Instantiate the Unit Under Test (UUT)
EdgeDetector uut (
.()
);
i... | 7.192487 |
module EdgeHessian_2D (
input iclk,
input irst_n,
input signed [ 8:0] idxx,
input signed [ 8:0] idyy,
input signed [ 8:0] idxy,
output reg signed [ 9:0] otr,
output reg signed [16:0] odet
);
reg [ 8:0] r_tr;
reg [16:0] data1;
reg [1... | 7.042745 |
module EdgeJKFlipFlop (
input J,
input K,
input CLK,
output reg Q,
output notQ
);
assign notQ = ~Q;
always @(posedge CLK) begin
case ({
J, K
})
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
end
endmodule
| 7.045114 |
module: EdgeJKFlipFlop
//
// Dependencies: EdgeJKFlipFlop
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EdgeJKFlipFlopTest;
// Inputs
reg J;
reg K;
reg CLK;
// Outputs
wire Q;
wire notQ;
//... | 6.704503 |
module edgepuffer2 (
input wire clock,
input wire Prescale_EN, // DW 2005.06.21 Prescale Enable
input wire reset,
input wire rx, // aussen
output wire puffer // smpldbit_reg
);
//tmrg default triplicate
//tmrg tmr_error false
reg buff; // buf in buff geaendert (rese... | 7.235267 |
module edgetrigger (
input wire clk,
input wire in,
output wire out
);
reg triggered = 0;
assign out = in && !triggered;
always @(posedge clk) begin
if (in) begin
triggered <= 1;
end else begin
triggered <= 0;
end
end
endmodule
| 7.139991 |
module edgeTriggeredDFlipFlop (
SW,
KEY,
LEDR,
HEX0,
HEX4,
HEX5
);
input [9:0] SW;
input [0:0] KEY;
output [7:0] LEDR;
output [6:0] HEX0; //HEX0 value of Date(A)
output [6:0] HEX4; //4 least significant bits of register
output [6:0] HEX5; //4 most significant bits of register
re... | 7.147945 |
module hexDecoder (
SW,
HEX
);
input [3:0] SW;
reg [6:0] result;
output [6:0] HEX;
always @(*) begin
case (SW[3:0])
4'b0000: result[6:0] = 7'b1000000;
4'b0001: result[6:0] = 7'b1111001;
4'b0010: result[6:0] = 7'b0100100;
4'b0011: result[6:0] = 7'b0110000;
4'b0100: resul... | 7.643178 |
module fourBitAdder (
SW,
LEDR
);
input [8:0] SW;
output [4:0] LEDR;
wire [2:0] cable;
fullAdder FA1 (
.a(SW[4]),
.b(SW[0]),
.cin(SW[8]),
.s(LEDR[0]),
.cout(cable[0])
);
fullAdder FA2 (
.a(SW[5]),
.b(SW[1]),
.cin(cable[0]),
.s(LEDR[1]),
.... | 8.486678 |
module edgeUnit (
windowIn,
threshold,
edgePixel
); // 3x3 Center Threshold Pattern Computation
function integer log2;
input integer value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter inputWidth = 8;
lo... | 6.928965 |
module EdgeUp (
clk,
reset,
in,
out
);
input clk, reset, in;
output out;
reg last = 1'b1; // init to "1" not to create false positive the first time the module is used
reg l_out;
always @(posedge clk)
if (reset == 1'b1) begin
last <= 1'b1;
l_out <= 1'b0;
end else begin
... | 6.838097 |
module edge_adder_switch #(
parameter DATA_TYPE = 32,
parameter NUM_IN = 4,
parameter SEL_IN = 2
) (
clk,
rst,
// reconfigurable control signal
i_add_en, // add enable
i_cmd, // command to add or forward
i_sel, // reduction mux select bits
o_vn, // vn output
o_vn_valid... | 7.3212 |
module edge_buffer (
input wire clock,
input wire set,
input wire reset,
input wire [bitwidth-1:0] data,
output reg [bitwidth-1:0] q = 0,
output reg avail = 0
);
parameter bitwidth = 24;
always @(posedge clock) begin
if (reset) avail <= 1'b0;
else if (set & (~avail)) begin
q[... | 6.691962 |
module edge_capture #(
parameter EDGE_TYPE = 0 //0 = rising edge, 1 = falling edge
) (
input clk,
input rst_n,
input signal_i,
output edge_captured_o
);
reg signal_1dff, signal_2dff;
generate
if (EDGE_TYPE == 0) begin
assign edge_captured_o = signal_1dff & (~signal_2dff);
end... | 8.332283 |
module edge_detct (
input wire rst,
input wire clk,
input wire i,
output reg rise,
output reg fall
);
reg ii;
always @(posedge clk)
if (rst) ii <= 1'b0;
else ii <= i;
always @(posedge clk)
if (rst) rise <= 1'b0;
else if (i == 0 && ii) rise <= 1'b1;
else rise <= 1'b0... | 7.339197 |
module, and provides and interface //
// to test the module from Python (MyHDL) //
// Date: Oct 2011 //
// Developer: Rurik Primiani & Wesley New //
// Licence: GNU General Public L... | 9.300519 |
module edge_detect1 #(
parameter WIDTH = 2,
parameter [WIDTH-1:0] ZERO = 2'b00,
ONE = 2'b11,
EDGE = 2'b10
) (
i_clk,
rst_n,
toggle,
level,
p_STATE
);
input i_clk;
input rst_n;
input level;
output toggle;
/////states //////
output reg [WIDTH-1:0] p_STATE;
reg [WIDTH-1:0... | 8.715269 |
module edge_detect1_tb ();
reg i_clk;
reg rst_n;
reg level;
wire toggle;
wire [1:0] p_STATE;
edge_detect1 DUT (
.i_clk (i_clk),
.rst_n (rst_n),
.toggle (toggle),
.level (level),
.p_STATE(p_STATE)
);
initial begin
i_clk = 1'b0;
rst_n = 1'b0;
level = 1'b0;
... | 7.228144 |
module edge_detection (
clk,
data_in,
data_out
);
input clk;
input data_in;
output data_out;
wire q1, q2, q3, q4;
dffo U1 (
clk,
data_in,
q1,
);
dffo U2 (
clk,
q1,
q2,
);
dffo U3 (
clk,
q2,
q3,
);
dffo U4 (
clk,
q3,
... | 6.873521 |
module dffo (
clk,
d,
q,
q_n
);
input wire clk, d;
output reg q, q_n;
always @(posedge clk) begin
q <= d;
q_n <= ~d;
end
endmodule
| 6.648079 |
module edge_detection (
clk,
rst,
en,
iRow,
iCol,
iHscan,
iVscan,
dataBW,
oRow,
oCol,
ofinish
);
input clk; //时钟信号
input en; //模块使能信号
input rst; //复位信号
input iHscan, iVscan; //行or列扫描标志
input [9:0] iRow, iCol; //当前像素点位于第几行第几列
input [9:0] dataBW; //输入的二值图像数据
... | 6.873521 |
module edge_detection_t ();
reg data_in, clk;
wire data_out;
edge_detection E1 (
clk,
data_in,
data_out
);
always #10 clk = ~clk;
initial begin
clk = 0;
data_in = 0;
end
initial begin
#12 data_in = 1;
#1 data_in = 0;
#1 data_in = 1;
#1 data_in = 0;
#1 d... | 6.873521 |
module edge_detection_TB;
reg clk;
reg rst;
reg ena;
reg [7:0] DataSource[0:640*480-1];
reg [9:0] pixel;
wire [19:0] oRow, oCol;
//读取数据
initial begin
$readmemh("imgdata5.txt", DataSource); //????
#20 $display("0x00: %h", DataSource[8'h00]);
end
//地址生成逻辑
reg [9:0] row, col;
reg [ 1:... | 6.873521 |
module edge_detection_wrapper (
clock,
reset,
hall_a,
hall_b,
hall_c,
hall_f_a,
hall_f_b,
hall_f_c
);
input clock;
input reset;
input hall_a;
input hall_b;
input hall_c;
output hall_f_a;
output hall_f_b;
output hall_f_c;
//hall a edge detection
edge_detection HA (
... | 6.873521 |
module edge_detect_mealy (
input wire clk,
reset,
input wire level,
output reg tick
);
// symbolic state declaration
localparam zero = 1'b0, one = 1'b1;
// signal declaration
reg state_reg, state_next;
// state register
always @(posedge clk, posedge reset)
if (reset) state_reg <= z... | 8.503577 |
module edge_detect_moore (
input wire clk,
reset,
input wire level,
output reg tick
);
// symbolic state declaration
localparam [1:0] zero = 2'b00, edg = 2'b01, one = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
// state register
always @(posedge clk, posedge reset)
... | 8.503577 |
module edge_detect_tb;
// signal declaration
localparam T = 10; //clk period
reg clk, reset;
reg level;
wire tick_mealy;
wire tick_moore;
// instance
edge_detect_moore edg_moore (
.clk (clk),
.reset(reset),
.level(level),
.tick (tick_moore)
);
// mealy edge detector inst... | 7.698943 |
module edge_dff (
q,
qbar,
d,
clk,
reset
);
// Inputs and outputs
output q, qbar;
input d, clk, reset;
reg q, qbar; //declare q and qbar are registers
always @(negedge clk) //assign value of q and qbar at active edge of clock
begin
q = d;
qbar = ~d;
end
always @(reset) //O... | 7.296102 |
module edge_generator #(
parameter MODE = "NORMAL" // FAST NORMAL BEST
) (
input clk,
input rst_n,
input in,
output raising,
output falling
);
reg in_d0;
reg in_d1;
reg raising_reg;
reg falling_reg;
always @(posedge clk /*,negedge rst_n*/) begin
if (~rst_n) begin
in_d0... | 7.035042 |
module edge_sync #(
parameter POSEDGE = 1
) (
input clk,
input rst,
input sig,
output trig
);
reg [1:0] delay;
always @(posedge clk)
if (rst) delay <= 2'b00;
else delay <= {delay[0], sig};
assign trig = POSEDGE ? (delay == 2'b01) : (delay == 2'b10);
endmodule
| 7.058513 |
module edge_to_flip #(
parameter TEMP0 = 16,
parameter TEMP1 = 5
) (
input clk,
input rstn,
input data_in,
output reg flip_output
);
reg data_in_reg;
always @(posedge clk) begin
if (~rstn) begin
data_in_reg <= 0;
flip_output <= 0;
end else begin
data_in_reg <= dat... | 7.11211 |
module edge_trigger (
input wire clk,
reset,
input wire level,
output wire tick
);
reg delay_reg;
always @(posedge clk, posedge reset) begin
if (reset) begin
delay_reg <= 1'b0;
end else begin
delay_reg <= level;
end
end
assign tick = ~delay_reg & level;
endmodule
| 6.77078 |
module Edge_Y (
input [199:0] image_in, //Input Matrix
output [ 7:0] pixel_out //Output Matrix
);
//For paralellization
wire [15:0] tmp;
//Directly writing the values for 5x5 kernel, where the values are hand-calculated
wire [15:0] first_col1 = -image_in[7:0] - 2 * image_in[47:40];
wire [15:0] f... | 6.533881 |
module edidram (
input wire clk,
input wire we,
input wire [14:0] waddr,
input wire [7:0] wdata,
input wire [14:0] raddr,
output reg [7:0] rdata
);
reg [7:0] RAM[32767:0];
always @(posedge clk) begin
if (we == 1'b1) begin
RAM[waddr] <= wdata;
end
rdata <= RAM[raddr];
end... | 7.196673 |
module EDID_I2C (
input wire clk,
input wire SCL_PIN,
inout wire SDA_PIN
);
// Archivo con el contenido de la memoria
parameter rom_init_file = "\"ERROR=PLEASE_SPECIFY_INIT_ROM_FILE\"";
// Cables/Buses para interconectar modulos
wire [15:0] ctrl_to_I2Cbus;
wire [ 7:0] ctrl_to_ROM;
wire [ 7:... | 6.747629 |
module edid_mem (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [7:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_... | 6.517509 |
module edid_ram (
input wire [7:0] data, // data.datain
output wire [7:0] q, // q.dataout
input wire [7:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
e... | 6.739596 |
module edid_ram (
input wire [7:0] data, // data.datain
output wire [7:0] q, // q.dataout
input wire [7:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
endm... | 6.739596 |
module vbox_hbox_edram (
clk,
clkREF1,
clkREF2,
rst,
port_en,
port_ref_plus2,
port_read_addr,
port_read_data,
port_write_addr,
port_write_data,
port_wen_plus3,
port_data_plus3
);
input clk;
input clkREF1;
input clkREF2;
input rst;
input port_en;
input port_re... | 6.711748 |
module: EdgeDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EDTestBench;
// Outputs
wire ;
// Instantiate the Unit Under Test (UUT)
EdgeDetector uut (
.()
);
init... | 7.192487 |
module edvr_edge_det #(
parameter EDGE = 1'b1
) (
input clk,
input rstn,
input din,
output dout_edge
);
reg din_d1;
always @(posedge clk or negedge rstn) begin
if (!rstn) din_d1 <= ~EDGE;
else din_d1 <= din;
end
assign dout_edge = EDGE ? din & ~din_d1 : ~din & din_d1;
endmodule... | 6.579438 |
module ED_USRP (
input clock,
input reset,
input strobe_in,
input set_stb,
input [ 7:0] set_addr,
input [31:0] set_data,
input [31:0] xn,
output strobe_out,
output [31:0] xk
);
wire reset_usr;
//FFT unit signals
wire [15:0] xk... | 7.582971 |
module ee201_clk_60Hz (
Clk,
Reset,
Clk60
);
// parameters
/**
TODO: fix width to allow for 60H z
use MINIMUM required WIDTH to allow 60Hz
**/
parameter WIDTH = 21;
/* INPUTS */
// Clock & Reset
input Clk, Reset;
/* OUTPUTS */
// output clock
output Clk60;
reg ClkReg;
assi... | 6.675973 |
module ee201_pulse_atN (
Clk,
Reset,
Pulse,
N
);
// parameters
/** TODO: update WIDTH = COUNTER width
use MINIMUM required WIDTH to count for N <= 1000 (decimal)
**/
parameter WIDTH = 10;
/* INPUTS */
// Clock & Reset
input Clk, Reset;
// Terminal count
input [WIDTH-1:0] N;
//... | 6.931504 |
module ee201_slowerclk (
Clk,
Reset,
Clk100K
);
// parameters
/**
TODO: fix width to allow for 60H z
use MINIMUM required WIDTH to allow 60Hz
**/
parameter WIDTH = 21;
/* INPUTS */
// Clock & Reset
input Clk, Reset;
/* OUTPUTS */
// output clock
output Clk60;
reg ClkReg;
as... | 6.559684 |
module mintermImplementation ( // module named mintermImplementation , here function is sum(0,1,3,8,9) 8038
output Q, // gives output as port Q 8038
input [3:0] A // takes input from port A, which is 4bit number with msb A[3] and lsb A[0] 8038
);
wire w1, w2, w3, w4, w5, w6; //w1,w2,w3,w3,w5,w6 ... | 7.05898 |
module fullAdder ( //module named fullAdder. 8038
output sum,
carryOut, //gives output in sum and carryOut . 8038
input carryIn,
bit1,
bit2 //takes input from carryIn bit1 and bit2 . 8038
);
assign {carryOut,sum} = carryIn + bit1 + bit2; //assigning value of carryIn + bit1 + bit2, to concate... | 6.756069 |
module fullAdder
module four_bit_signed_Adder( // module named four_bit_signed_Adder . 8038
output [3:0]s, // 4 bit output s, with msb s[3]
output zeroFlag, negFlag, overflowFlag, carryFlag, //all necessaray flags
input carryIn, ... | 7.748296 |
module mux_2x1 ( //module named mux_2x1 8038
output mux_2x1_op, //gives output as mux_2x1_op 8038
input select,
data1,
data0 //takes select, data0, and data1 as input 8038
);
wire w1, w2, w3; //w1,w2,w3 are intermediate wires 8038
not not_gate (w1, select); //not gate has ip->select and op->w... | 7.362147 |
module mux_2x1 8038
module mux_8x1 ( //module named mux_8x1 , it uses previous module to implement 8x1 mutlipexer 8038
output mux_8x1_op, //gives output as mux_8x1_op 8038
input [7:0]D, [2:0]sel //takes 8bit D, and 3 bit sel as input 8038
);
wire W1,W2,W3,W4,W5,W6; //W1, W2, W3, W4, W5, W6 are intermedia... | 7.095221 |
module Decimal2Gray ( //This starts a module named Decimal2Gray 8038
output [3:0] G, //with Output as G a 4 bit number (MSB G3) 8038
input [3:0] A //and Input as A a 4 bit number (MSB A3) 8038
);
xor gate1 (
G[2], A[3], A[2]
), //gate1 , a xor gate , Input ->A[3] and A[2], Output G[2] 8038
... | 6.870961 |
module booths ( // module named booths . 8038
output [15:0] result, //gives output to 16 bit result. 8038
output validity, //validity tells when the result is valid. i.e when validity is 0 means the answer is the final answer. 8038
input [7:0] num1,
num2, //takes input in 8 bit ... | 6.57637 |
module Datapath_for_Div ( // Datapath Module named Datapath_for_Div .8038
output less, // Gives output as less . 8038
input LoadD1,
LoadD2,
LoadC,
LoadP,
LdSAD,
clearC,
incC, // These are the inputs for the module ( 1 bit inputs). 8038
input [15:0] Data_in, // ... | 7.000728 |
module Datapath_for_Div. 8038
module PIPO1 ( // Module named PIPO1 . 8038
output reg [15:0]dout, // Output is a 16 bit dout . 8038
input [15:0]din1,din2, // inputs are 16 bit din1 and di... | 7.000728 |
module named PIPO1 . 8038
module PIPO2 ( // Module name for PIPO2 . 8038
output reg [15:0]dout, // Output is a register of 16 bits ( dout ). 8038
input ld,clock); // Inputs are a lo... | 6.546508 |
module PIP02 . 8038
module SAD ( // module named SAD . 8038
output reg [15:0]us, // gives 16bit output to a register us. 8038
input ld, // takes in input as load. 8038
... | 7.013291 |
module I_Counter_stage_reg (
rstb,
clk,
en,
i,
initial_i,
end_flag,
i_reg,
initial_i_reg,
end_flag_reg
);
input rstb, clk, en;
input [5:0] i;
input initial_i, end_flag;
output reg [5:0] i_reg;
output reg initial_i_reg, end_flag_reg;
always @(posedge clk, negedge rstb) ... | 6.669452 |
module T_S_Fetcher_stage_reg (
clk,
en,
rstb,
st2_i,
st2_initial_i,
st2_end_flag,
st2_Ti,
st2_s,
st2_i_reg,
st2_initial_i_reg,
st2_end_flag_reg,
st2_Ti_reg,
st2_s_reg
);
input rstb, clk, en;
input [5:0] st2_i;
input [4:0] st2_s;
input [31:0] st2_Ti;
input s... | 6.740915 |
module I_counter (
en,
clk,
rstb,
i
);
input en, clk, rstb;
output reg [5:0] i;
always @(posedge clk, negedge rstb) begin
if (rstb == 1'b0) begin
i = 6'b000000;
end else begin
if (en) begin
i = i + 1;
end
end
end
endmodule
| 6.525778 |
module Xk_Fetcher (
clk,
initial_i,
rst,
en,
curr_i_val,
output_Xk_value_wire
);
input clk, en, rst, initial_i;
input [5:0] curr_i_val;
reg [31:0] input_X_msg[15:0];
reg [3:0] output_k_value;
wire [3:0] output_k_value_wire;
reg [31:0] output_Xk_value;
reg toggle_flag;
output wire... | 6.621486 |
module combined_Func_calc_shift_adder (
clk,
i_input,
A_input,
B_input,
C_input,
D_input,
Xk_plus_Ti_input,
s_input,
input_shifter_base,
int_B_output
);
input clk;
input [5:0] i_input;
input [31:0] A_input, B_input, C_input, D_input, Xk_plus_Ti_input, input_shifter_base;
... | 6.6159 |
module pc (
en,
clk,
rstb,
pco
);
input en, clk, rstb;
output reg [7:0] pco;
always @(posedge clk, negedge rstb)
if (rstb == 1'b0) begin
pco <= 0;
end else if (en) begin
pco <= pco + 1;
end
endmodule
| 6.679635 |
module ins_mem (
a,
d_out
);
input [5:0] a;
output [31:0] d_out;
reg [31:0] memory[0:63];
assign d_out = memory[a];
endmodule
| 6.664043 |
module pipe_if_id_P1 (
rstb,
clk,
en,
id_za,
id_ya,
id_xa,
id_ra,
run,
instr_in,
instr_out
);
input rstb, clk, en;
input [31:0] instr_in;
output reg [31:0] instr_out;
output reg [3:0] id_za, id_ya, id_xa, id_ra;
output reg run;
always @(posedge clk, negedge rstb) begi... | 6.81388 |
module pipe_if_id_P3 (
rstb,
clk,
en,
id_xa,
id_ra,
add1,
add4,
sub3,
mov,
instr_in,
instr_out
);
input rstb, clk, en;
input [31:0] instr_in;
output reg [31:0] instr_out;
output reg [3:0] id_xa, id_ra;
output reg add1, add4, sub3, mov;
always @(posedge clk, negedg... | 6.859381 |
module register_file (
r1a,
r2a,
r3a,
wa,
wd,
reg_write,
r1d,
r2d,
r3d,
clk
);
input clk, reg_write;
input [3:0] r1a, r2a, r3a, wa;
input [15:0] wd;
output [15:0] r1d, r2d, r3d;
reg [15:0] reg_file[0:15];
assign r1d = reg_file[r1a];
assign r2d = reg_file[r2a];
a... | 6.605344 |
module comp_station_P1 (
ex2_ra,
ex1_ra,
id_za,
id_xa,
id_ya,
zmex2,
ymex2,
xmex2,
zmex1,
ymex1,
xmex1
);
input [3:0] ex2_ra, ex1_ra, id_za, id_ya, id_xa;
output reg zmex2, ymex2, xmex2, zmex1, ymex1, xmex1;
always @(ex2_ra, ex1_ra, id_za, id_ya, id_xa) begin : combina... | 7.004195 |
module comp_station_P3 (
ex2_ra,
ex1_ra,
id_xa,
xmex2,
xmex1
);
input [3:0] ex2_ra, ex1_ra, id_xa;
output reg xmex2, xmex1;
always @(ex2_ra, ex1_ra, id_xa) begin : combinational_block
// default assignments
xmex2 <= 1'b0;
xmex1 <= 1'b0;
// conditional over-riding of the defaul... | 7.004195 |
module ee465_gold_standard_srrc (
input sys_clk, //system clock
input sam_clk, //sampling clock
input signed [17:0] sig_in, //upsampled input value 1s17
output reg signed [17:0] sig_out //output of filter 1s17
);
always @(posedge sys_clk) if (sam_clk == 1'b1) sig_out <= sig_in;
endmodule
| 7.162374 |
module ham_15_11_encoder (input d[10:0],output c[14:0]);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 15-bit output
input [10:0] req_vector;
// Declare "reg" signals...
// Parity bits for Hamming encoding
reg [3:0] p;
// Declare "wire"... | 7.781916 |
modules (defined below). This
policy will apply to lecture, discussion, lab, project, and problem
sets. This way of specification matches our RTL model of circuit,
i.e., all specifications are nothing but a set of interconnected
combinational logic blocks and state elements. The goal is to
simplify the use of V... | 8.103781 |
module REGISTER_CE (
q,
d,
ce,
clk
);
parameter N = 1;
output reg [N-1:0] q;
input [N-1:0] d;
input ce, clk;
initial q = {N{1'b0}};
always @(posedge clk) if (ce) q <= d;
endmodule
| 6.957371 |
module REGISTER_R (
q,
d,
rst,
clk
);
parameter N = 1;
parameter INIT = {N{1'b0}};
output reg [N-1:0] q;
input [N-1:0] d;
input rst, clk;
initial q = INIT;
always @(posedge clk)
if (rst) q <= INIT;
else q <= d;
endmodule
| 7.237064 |
module REGISTER_R_CE (
q,
d,
rst,
ce,
clk
);
parameter N = 1;
parameter INIT = {N{1'b0}};
output reg [N-1:0] q;
input [N-1:0] d;
input rst, ce, clk;
initial q = INIT;
always @(posedge clk)
if (rst) q <= INIT;
else if (ce) q <= d;
endmodule
| 6.754107 |
module ASYNC_ROM (
q,
addr
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input [AWIDTH-1:0] addr; // address
output [DWIDTH-1:0] q; // read data
(* rom_style = ... | 8.222369 |
module ASYNC_RAM (
q,
d,
addr,
we,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input [AWIDTH-1:0] addr; // address
input we; // writ... | 8.512407 |
module SYNC_ROM (
q,
addr,
en,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input en; // ram-enable
input [AWIDTH-1:0] addr; // address
... | 7.63125 |
module SYNC_RAM (
q,
d,
addr,
we,
en,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = 1 << AWIDTH; // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input [AWIDTH-1:0] addr; // address
input we; //... | 8.105496 |
module SYNC_ROM_DP (
q0,
addr0,
en0,
q1,
addr1,
en1,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input en0, en1; // ram-enable
... | 7.228411 |
module ASYNC_RAM_DP (
q0,
d0,
addr0,
we0,
q1,
d1,
addr1,
we1,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input [AWIDTH-... | 7.67963 |
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