code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SYNC_RAM_DP (
q0,
d0,
addr0,
we0,
en0,
q1,
d1,
addr1,
we1,
en1,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;... | 7.453851 |
module SYNC_RAM_WBE (
q,
d,
addr,
en,
wbe,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input [DWIDTH-1:0] d; // Data input
input [AWIDTH-1:0] ... | 7.407098 |
module SYNC_RAM_DP_WBE (
q0,
d0,
addr0,
en0,
wbe0,
q1,
d1,
addr1,
en1,
wbe1,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = (1 << AWIDTH); // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
inpu... | 7.119119 |
module ASYNC_RAM_1W2R (
d0,
addr0,
we0,
q1,
addr1,
q2,
addr2,
clk
);
parameter DWIDTH = 8; // Data width
parameter AWIDTH = 8; // Address width
parameter DEPTH = 256; // Memory depth
parameter MIF_HEX = "";
parameter MIF_BIN = "";
input clk;
input [DWIDTH-1:0] d0; // D... | 7.435371 |
module EEPROM_avs (
input clk_50,
input reset_n,
//avs
output reg [1:0] avs_response_reg = 2'b00,
output reg avs_waitrequest_reg,
input [7:0] avm_addr,
input [31:0] avm_data_write,
output [31:0] avm_data_read_receive,
input avm_datawrite_en,
input avm__dataread_en
);
E... | 7.445199 |
module eeprom_byte_rd_wr (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
input wire key_wr, //按键写
input wire key_rd, //按键读
inout wire sda, //串行数据
output wire scl, //串行时钟
output wire stcp, //输出数据存储器时钟
output wire shcp, //移位寄存器的时钟输入
outpu... | 8.168759 |
module EEPROM_I2C_RAM #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
(* ramstyle = "M9K" *) reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
... | 8.666326 |
module n64_eeprom_fifo(
// input clk_read,
// input clk_write,
// input rst_n,
// input sclr,
// input rdreq,
// input wrreq,
// input [width-1:0] data,
//... | 7.038452 |
module EEPROM_RAM #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 9
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we,
clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
(* ramstyle = "M9K" *) reg [DATA_WIDTH-1:0] ram[2... | 7.984503 |
module eeprom_top (
input clk,
input rst_n,
input [ 7:0] addr,
input [ 7:0] data,
input read_n,
input write_n,
output [15:0] display,
output complete,
inout i2c_SCL,
inout i2c_SDA
);
///////////////////////////////////
... | 6.909396 |
module eep_i2c_scl (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire cl... | 6.587551 |
module eep_i2c_sda (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout bidir_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire... | 6.619713 |
module eep__i2c_scl (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire c... | 6.51251 |
module ee_589_MPC_tb ();
parameter word_size = 32;
reg i_clk;
reg i_reset_n;
reg [word_size-1:0] i_Vpv;
reg [word_size-1:0] i_Ipv;
reg [word_size-1:0] i_Vout;
reg i_calc_DV; //goes high based on the sampling rate
wire o_switch;
MPC UUT (
.i_clk(i_clk),
.i_reset_n(i_reset_n),
.i_... | 6.624843 |
module ee_589_project_TB ();
reg i_clk;
reg i_reset_n;
reg signed [31:0] i_Vpv;
reg signed [31:0] i_Vout;
wire signed [31:0] o_MPC_DC;
wire [31:0] debug;
wire [31:0] debug1;
wire signed [31:0] IPV = UUT.IPV;
wire signed [31:0] IPV_plus = UUT.IPV_plus;
wire signed [31:0] IPV_minus = UUT.IPV_minus;
... | 6.56011 |
module ee_589_project (
input i_clk,
input i_reset_n,
input signed [31:0] i_Vpv,
input signed [31:0] i_Vout,
output reg signed [31:0] o_MPC_DC,
output signed [31:0] debug,
output signed [31:0] debug1,
output signed [31:0] debug2,
output signed [31:0] debug3
);
parameter word_siz... | 6.56011 |
module EFA (
input x1,
x2,
cin,
output sum,
cout
);
wire s, c1, c2;
EHA HA0 (
.x1 (x1),
.x2 (x2),
.sum (s),
.cout(c1)
);
EHA HA1 (
.x1 (s),
.x2 (cin),
.sum (sum),
.cout(c2)
);
assign cout = c1 | c2;
endmodule
| 7.29165 |
module effect ( /*AUTOARG*/
// Outputs
i2c_clk,
i2c_dat,
dacdat,
clk,
// Inputs
clkfast,
clkfast2,
reset_dirty,
bclk,
adclrc,
adcdat,
daclrc,
distortionon,
choruson,
vibratoon
);
output i2c_clk, i2c_dat;
input clkfast, clkfast2; //50M input
input ... | 6.962572 |
module effective_op (
input a_sign,
input b_sign,
input sub,
output reg eff_op
);
always @(*) begin
case ({
sub, a_sign, b_sign
})
3'b000: eff_op = 0;
3'b001: eff_op = 1;
3'b010: eff_op = 1;
3'b011: eff_op = 0;
3'b100: eff_op = 1;
3'b101: eff_op = 0;
... | 6.660985 |
module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
`include "no_effect.v"
//top module
`include "effect_module.v"
module effect_tb#( parameter
data_width = 16 ... | 7.759536 |
module effect_decoder (
input [15:0] flags,
input [2:0] effect,
output store
);
assign store =
effect == 3'h0 ? flags[0] :
effect == 3'h1 ? ~flags[0] :
effect == 3'h2 ? flags[1] :
effect == 3'h3 ? ~flags[1] & ~flags[0] :
effect == 3'h4 ? 1 :
effect == 3'h5 ?... | 6.808359 |
module effect_decoder_tb;
// Setup registers for the inputs
reg [15:0] flags;
reg [2:0] effect;
// Setup a wire for the outputs
wire store;
// Instantiate the unit under test
effect_decoder effect_decoder (
.flags (flags),
.effect(effect),
.store (store)
);
initial begin
// I... | 6.808359 |
module effect_module #(
parameter d_width = 16 // data width
) (
input clk,
input reset,
input [ 1:0] sw, // effect control switches
input [ 13:0] i_treshhold, // treshhold from switches
input ... | 7.554127 |
module represents a 2D (n x n) memory which contains
// the weights of the efferent connections from
// a neuron to all other neurons. Weights of 0
// indicate that no connection exists between neurons
// support row (src neuron tag) select and column (dst neuron tag) select
// todo - support data load in sequential f... | 7.311982 |
module simple_dual_port_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter OUTPUT_REG = "TRUE",
parameter RAM_INIT_FILE = ""
) (
input wire [(DATA_WIDTH-1):0] wdata,
input wire [(ADDR_WIDTH-1):0] waddr,
raddr,
input wire we,
wclk,
re,
rclk,
output wire [... | 8.990829 |
module true_dual_port_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter WRITE_MODE_1 = "READ_FIRST", // WRITE_FIRST, READ_FIRST, NO_CHANGE
parameter WRITE_MODE_2 = "READ_FIRST",
parameter OUTPUT_REG_1 = "FALSE",
parameter OUTPUT_REG_2 = "FALSE",
parameter RAM_INIT_FILE = ... | 9.063194 |
module eflags (
clk,
reset,
valid,
eflags_in,
set_eflags,
eflags_out
);
input clk;
input reset;
input valid;
input [6:0] eflags_in;
input [6:0] set_eflags;
output [6:0] eflags_out;
//latch$ DF(.d(eflags_in[6]), .en(set_eflags[6]), .q(eflags_out[6]));
//latch$ OF(.d(eflags_in[5]... | 6.689947 |
module efm #(
parameter WIDTH = 24
) (
input clk,
input rst_n,
input [WIDTH-1:0] x_i,
output y_o,
output [WIDTH-1:0] e_o
);
wire [ WIDTH:0] sum;
reg [WIDTH-1:0] error_r;
assign sum = x_i + error_r;
// always @(posedge clk or negedge rst_n) begin
// if (!rst_n) begin
// ... | 7.538213 |
module sky130_fd_sc_hd__inv (
Y,
A
);
output Y;
input A;
assign Y = ~A;
endmodule
| 7.212805 |
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
reg buffers_0;
reg buffers_1;
initial begin
buffers_0 = 0;
buffers_1 = 0;
end
assign io_dataOut = buffers_1;
always @(posedge toplevel_io_a... | 6.712921 |
module BufferCC_1_ (
input io_dataIn,
output io_dataOut,
input toplevel_io_axiClk,
input toplevel_resetCtrl_systemReset
);
reg buffers_0;
reg buffers_1;
initial begin
buffers_0 = 0;
buffers_1 = 0;
end
assign io_dataOut = buffers_1;
always @(posedge toplevel_io_axiClk) begin
... | 7.044402 |
module BufferCC_2_ (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
reg [7:0] buffers_0;
reg [7:0] buffers_1;
initial begin
buffers_0 = 0;
buffers_1 = 0;
end
assign io_dataOut = buffers_1;
always @(posedge toplevel_io_... | 7.089398 |
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_defaultEncoding_type io_config_frame_stop,
input `UartParityType_defaultEncoding_type io_config_frame_parity,
input [19:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_p... | 7.177325 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
wire [0:0] _zz_1_;
wire [31:0] _zz_2_;
reg [31:0] counter;
wire limitHit;
reg inhibitFull;
initial begin
... | 6.729771 |
module Timer_1_ (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
wire [0:0] _zz_1_;
wire [15:0] _zz_2_;
reg [15:0] counter;
wire limitHit;
reg inhibitFull;
initial begin... | 6.570036 |
module InterruptCtrl (
input [7:0] io_inputs,
input [7:0] io_clears,
input [7:0] io_masks,
output [7:0] io_pendings,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
reg [7:0] pendings;
initial begin
pendings = 0;
end
assign io_pendings = (pendings & io_masks);
alwa... | 7.510624 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:... | 7.046487 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input _zz_1_,
input toplevel_io_axiClk,
input toplevel_resetCtrl_systemRes... | 7.790686 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [2:0] io_axi_arw_payload_size,
input [3:0] io_axi_arw_payload_cache,
input [2:0] io_axi_arw_payload_prot,
input io_axi_arw_payload_write,
input io_axi_w_valid,
o... | 6.942764 |
module StreamArbiter (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [14:0] io_inputs_0_payload_addr,
input [3:0] io_inputs_0_payload_id,
input [7:0] io_inputs_0_payload_len,
input [2:0] io_inputs_0_payload_size,
input [1:0] io_inputs_0_payload_burst,
input io_inputs_0_payload... | 6.929245 |
module StreamFifoLowLatency_1_ (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input toplevel_io_axiClk,
input toplevel_resetCtrl_axiReset
);
wire [0:0] _zz_1_;
wire [1:0] _zz_2_;
wire [0:0] _zz_3_... | 7.046487 |
module StreamArbiter_1_ (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [3:0] io_inputs_0_payload_id,
input [7:0] io_inputs_0_payload_len,
input [2:0] io_inputs_0_payload_size,
input [1:0] io_inputs_0_payload_burst,
input io_inputs_0_payl... | 6.929245 |
module StreamArbiter_2_ (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [31:0] io_inputs_0_payload_addr,
input [7:0] io_inputs_0_payload_id,
input [3:0] io_inputs_0_payload_region,
input [7:0] io_inputs_0_payload_len,
input [2:0] io_inputs_0_payload_size,
input [1:0] io_inputs... | 6.929245 |
module BufferCC_3_ (
input io_dataIn,
output io_dataOut,
input toplevel_io_axiClk
);
reg buffers_0;
reg buffers_1;
initial begin
buffers_0 = 0;
buffers_1 = 0;
end
assign io_dataOut = buffers_1;
always @(posedge toplevel_io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= bu... | 7.324384 |
module Apb3InterruptCtrl (
input [3:0] io_bus_PADDR,
input [0:0] io_bus_PSEL,
input io_bus_PENABLE,
output io_bus_PREADY,
input io_bus_PWRITE,
input [31:0] io_bus_PWDATA,
output reg [31:0] io_bus_PRDATA,
output io_bus_PSLVERROR,
input [7:0] io_inputs,
output [7:0] io_pendings,
... | 6.519145 |
module add (
input a,
b,
output sum,
cout
);
assign {cout, sum} = a + b;
endmodule
| 6.686118 |
module full_add (
input a,
b,
cin,
output sum,
cout
);
wire s, carry1, carry2;
add add_inst1 (
.a(a),
.b(b),
.sum(s),
.cout(carr1)
);
add add_inst2 (
.a(s),
.b(cin),
.sum(sum),
.cout(carr2)
);
assign cout = carry1 | carry2;
endmodule
| 7.176667 |
module d_ff (
input clk,
d,
output reg q
);
always @(posedge clk) q <= d;
endmodule
| 6.958195 |
module d_ff_r (
input clk,
rst_n,
d,
output reg q
);
always @(posedge clk) begin
if (rst_n == 0) q <= 1'b0;
else q <= d;
end
endmodule
| 7.515571 |
module d_ff_s (
input clk,
rst_n,
d,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) q <= 1'b0;
else q <= d;
end
endmodule
| 7.747515 |
module EG4S20SDRAM // EG4S20SDRAM.v(14)
(
addr,
ba,
cas_n,
cke,
clk,
cs_n,
dm0,
dm1,
dm2,
dm3,
ras_n,
we_n,
dq
);
input [10:0] addr; // EG4S20SDRAM.v(19)
input [1:0] ba; // EG4S20SDRAM.v(20)
input cas_n; // EG4S20SDRAM.v(17)
input cke; // EG4S20SDRAM.v(2... | 6.900552 |
module eg4_ram16k (
doa,
dia,
addra,
clka,
wea
);
output [15:0] doa;
input [15:0] dia;
input [12:0] addra;
input [1:0] wea;
input clka;
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(16),
.ADDR_WIDTH_A(13),
.DATA_DEPTH_A(8192),
.DATA_WIDTH_B(16),
.ADDR_WIDTH_B(13),
.... | 6.5904 |
module eg4_ram32k (
doa,
dia,
addra,
clka,
wea
);
output [15:0] doa;
input [15:0] dia;
input [13:0] addra;
input [1:0] wea;
input clka;
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(16),
.ADDR_WIDTH_A(14),
.DATA_DEPTH_A(16384),
.DATA_WIDTH_B(16),
.ADDR_WIDTH_B(14),
... | 6.705711 |
module wbc_mem (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
eg4_ram16k ... | 6.731494 |
module wbc_mem_32k (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
eg4_ram... | 7.187448 |
module REG4 (
input clk,
rst_n,
input [3:0] D_IN,
output reg [3:0] D_OUT
);
always @(posedge clk) begin
if (rst_n == 0) D_OUT <= 4'b0;
else D_OUT <= D_IN;
end
endmodule
| 7.587531 |
module RGE4 (
input clk,
rst_n,
output reg [3:0] CNT
);
always @(posedge clk) begin
if (rst_n == 0) CNT <= 4'b0;
else CNT <= CNT + 4'b1;
end
endmodule
| 6.712867 |
module hex_decoder (
data,
segments
);
input [3:0] data;
output [6:0] segments;
reg [6:0] segments;
parameter BLANK = 7'b111_1111;
parameter ZERO = 7'b100_0000;
parameter ONE = 7'b111_1001;
parameter TWO = 7'b010_0100;
parameter THREE = 7'b011_0000;
parameter FOUR = 7'b001_1001;
parameter F... | 7.584821 |
module egg_timer #(
parameter SIZE = 4
) (
input clk,
input rst,
input start,
input [SIZE-1:0] max,
output [SIZE-1:0] led
);
/* clk - epected to be a 1Khz signal */
/* rst - stop the alarm and reset internal counter and counting state to 0 */
/* st... | 6.840265 |
module egg_timer_test ();
localparam SIZE = 4;
reg rst, start, clk;
reg [SIZE-1:0] max;
wire [SIZE-1:0] led;
vlog_tb_utils vlog_tb_utils0 ();
initial begin
max = 4'b0111;
rst = 0;
start = 0;
clk = 0;
end
always #1 clk = !clk;
egg_timer #(
.SIZE(SIZE)
) egg_timeri ... | 7.004327 |
module egress (
clk,
rstN,
int2eg_data,
eg2int_data,
int_datavalid,
int_datardy,
eg_datain,
eg_ad_dataout,
eg_valid,
eg_ready
);
input clk, rstN;
// Addr and data from the internal bridge
// For addr, 6:0 is the address and bit 7 is read_write information
input int_data... | 7.408043 |
module egr_oflow #(
parameter drop_thr = `TX_FIFO_DEPTH - 128
) (
input clk,
input reset,
input c_srdy,
output reg c_drdy,
input [`PFW_SZ-1:0] c_data,
input [`TX_USG_SZ-1:0] tx_usage,
output reg p_srdy,
input p... | 7.402341 |
module eg_cnt (
input clk,
input clk_en,
input rst,
input [14:0] eg_cnt,
input [2:0] state_IV,
input [5:0] rate_IV,
output reg [2:0] state_V,
output reg [5:0] rate_V,
output [2:0] cnt_V,
output reg sum_up
);
localparam ATTACK = 3'd0, DECAY1 = 3'd1, DECAY2 = 3'd2, RELEASE = 3'... | 8.377114 |
module eg_mux (
input clk,
input clk_en,
input rst,
input [14:0] eg_cnt,
input [2:0] state_IV,
input [5:0] rate_IV,
output reg [2:0] state_V,
output reg [5:0] rate_V,
output reg [2:0] cnt_V,
output reg sum_up
);
localparam ATTACK = 3'd0, DECAY1 = 3'd1, DECAY2 = 3'd2, RELEASE ... | 7.693408 |
module EG_PHY_SDRAM_2M_32 (
clk,
ras_n,
cas_n,
we_n,
addr,
ba,
dq,
cs_n,
dm0,
dm1,
dm2,
dm3,
cke
);
input clk;
input ras_n;
input cas_n;
input we_n;
input [10:0] addr;
input [1:0] ba;
inout [31:0] dq;
input cs_n;
input dm0;
input dm1;
input dm2;
... | 6.761017 |
module eg_step (
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK = 3'd0, DECAY1 = 3'd1, DECAY2 = 3'd2, RELEASE = 3'd7, HOLD = 3'd3;
reg [7:0] step_idx;
always @(*) begin : rate_step
if (rate_V[5:4] == 2'b11) begin // 0 means 1x, 1 means 2x
... | 8.723247 |
module eg_step_ram (
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK = 3'd0, DECAY1 = 3'd1, DECAY2 = 3'd2, RELEASE = 3'd7, HOLD = 3'd3;
reg [7:0] step_idx;
reg [7:0] step_ram;
always @(*)
case ({
rate_V[5:4] == 2'b11, rate_V[1:0]
... | 8.429926 |
module simulation
module eg_test;
localparam EG_WIDTH = 8;
localparam NUM_UNITS = 4;
reg aud_clk;
reg aud_rst;
reg [EG_WIDTH-1:0] attack_reg [NUM_UNITS-1:0];
reg [EG_WIDTH-1:0] decay_reg [NUM_UNITS-1:0];
reg [EG_WIDTH-1:0] sustain_reg [NUM_UNITS-1:0];
reg [EG_WIDTH-1:0] rel... | 7.09115 |
module eh2_dec_trigger
import eh2_pkg::*;
#(
`include "eh2_param.vh"
) (
input eh2_trigger_pkt_t [pt.NUM_THREADS-1:0][3:0] trigger_pkt_any,
input wire [ 31:1] dec_i0_pc_d,
input wire [ 31:1] dec_i1_pc_d,
input eh2_alu_pkt_t ... | 6.67731 |
module eh2_ifu_ic_mem
import eh2_pkg::*;
#(
`include "eh2_param.vh"
) (
input wire clk,
input wire rst_l,
input wire clk_override,
input wire dec_tlu_core_ecc_disable,
input wire [ 31:1] ic_rw_addr,
input wire [ pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
inpu... | 6.633539 |
module eh2_btb_tag_hash #(
`include "eh2_param.vh"
) (
input wire [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
output logic [pt.BTB_BTAG_SIZE-1:0] hash
);
assign hash = {
(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+p... | 7.605754 |
module eh2_btb_tag_hash_fold #(
`include "eh2_param.vh"
) (
input wire [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,
output logic [pt.BTB_BTAG_SIZE-1:0] hash
);
assign hash = {
(
pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTA... | 7.605754 |
module eh2_btb_addr_hash #(
`include "eh2_param.vh"
) (
input wire [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash
);
if (pt.BTB_FOLD2_INDEX_HASH) begin : fold2
assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^
... | 7.862318 |
module eh2_lsu_trigger
import eh2_pkg::*;
#(
`include "eh2_param.vh"
) (
input wire scan_mode,
input wire rst_l,
input eh2_trigger_pkt_t [pt.NUM_THREADS-1:0][3:0] trigger_pkt_any,
input wire ... | 6.567852 |
module eh2_cmp_and_mux #(
parameter ID_BITS = 8,
INTPRIORITY_BITS = 4
) (
input wire [ ID_BITS-1:0] a_id,
input wire [INTPRIORITY_BITS-1:0] a_priority,
input wire [ ID_BITS-1:0] b_id,
input wire [INTPRIORITY_BITS-1:0] b_priority,
output logic [ ID_BITS-1:0] out_id,
... | 8.473211 |
module eh2_configurable_gw (
input wire clk,
input wire rst_l,
input wire extintsrc_req_sync,
input wire meigwctrl_polarity,
input wire meigwctrl_type,
input wire meigwclr,
output logic extintsrc_req_config
);
wire gw_int_pending_in;
wire gw_int_pending;
assign gw_int_pending_in =... | 6.789008 |
module EHA (
input x1,
x2,
output sum,
cout
);
assign sum = x1 ^ x2;
assign cout = x1 & x2;
endmodule
| 8.576976 |
module ehn_stopwatch_TEST (
input clk,
rst_n,
input up,
go,
output [7:0] seg_out,
output [5:0] sel_out
);
wire [4:0] in0, in1, in2, in3, in4, in5;
Enhanced_Stopwatch ehn_stopwatch (
.clk(clk),
.rst_n(rst_n),
.up(up),
.go(go),
.in0(in0),
.in1(in1),
.... | 7.228848 |
module ehourglass (
sw1,
btn0,
rst,
clk,
speed,
beep,
r_col,
g_col,
row,
seg_led,
seg_led_d,
lcd_rs,
lcd_rw,
lcd_e,
d
);
input sw1, btn0, rst, clk; //sw1为重力信号，btn0为暂停信号
input [1:0] speed; //速度选择信号
output lcd_rs, lcd_rw, lcd_e; //lcd的管脚
output [7:0... | 7.470558 |
module ehr (
rst_n,
rng_clk,
cpu_rng_pwdata,
cpu_rng_paddr,
cpu_ehr_wr,
crngt_dout,
crngt_valid,
trng_valid,
curr_test_err,
bits_counter,
collector_valid,
trng_crngt_bypass,
rst_trng_logic,
ehr_valid,
ehr_data,
trng_prng_ehr_data,
ehr_rd_collector
);
... | 6.505817 |
module eia232 (
clock,
reset,
speed,
send,
wrdata,
rx,
// outputs
tx,
cmd,
execute,
busy
);
parameter [31:0] FREQ = 100000000;
parameter [31:0] SCALE = 28;
parameter [31:0] RATE = 115200;
input clock;
input reset;
input [1:0] speed; // UART speed
input send; ... | 7.365413 |
module EICG_wrapper (
output out,
input en,
input test_en,
input in
);
reg en_latched /*verilator clock_enable*/;
always @(*) begin
if (!in) begin
en_latched = en || test_en;
end
end
assign out = en_latched && in;
endmodule
| 6.53335 |
module eic_wrapper (
input wire clk,
input wire rstn,
input wire [ `XLEN-1:0] p_addr, // byte addr
input wire p_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] p_acc,
output wire [ `BUS_WIDTH-1:0] p_rdata,
input wire [ `BUS_WIDTH-... | 7.000079 |
module Get_Inst (
clka,
rst,
Inst_code,
PC
);
input clka;
input rst;
output [31:0] Inst_code;
output reg [31:0] PC;
// R型指令的下一个PC
wire [31:0] PC_new;
assign PC_new = PC + 4;
always @(negedge clka or posedge rst) begin
if (rst) PC <= 32'h00000000; //清零
else PC <= PC_new;
end... | 7.068802 |
module LED (
clka,
clk_in,
rst,
choice,
AN,
seg,
ZF,
OF,
PC,
Inst_code,
rd_data,
Data
);
input clka;
input clk_in;
input rst;
input [1:0] choice;
output [7:0] AN;
output [7:0] seg; //段选信号
output ZF, OF;
wire [2:0] ALU_OP; //操作符
wire Write_Reg; //是否写... | 6.596913 |
module show (
rst,
clk,
Data,
AN,
seg
);
input clk, rst;
input [31:0] Data;
//output reg [3:0] ds;
output reg [7:0] seg;
output reg [7:0] AN;
reg [2:0] BitSel;
reg [3:0] data;
always @(*) begin
case (data)
4'b0000: seg[7:0] <= 8'b00000011;
4'b0001: seg[7:0] <= 8'b10... | 6.947557 |
module eightBitCounter (
KEY,
SW,
HEX0,
HEX1,
LEDR
);
input [0:0] KEY; //Clock.
input [1:0] SW; //SW[0] for Clear_b, SW[1] for Enable.
output [6:0] HEX0;
output [6:0] HEX1;
output [7:0] LEDR;
wire [6:0] T;
assign T[0] = SW[1] & LEDR[0];
assign T[1] = T[0] & LEDR[1];
assign T[2] ... | 7.444134 |
module hexDecoder (
SW,
HEX
);
input [3:0] SW;
reg [6:0] result;
output [6:0] HEX;
always @(*) begin
case (SW[3:0])
4'b0000: result[6:0] = 7'b1000000;
4'b0001: result[6:0] = 7'b1111001;
4'b0010: result[6:0] = 7'b0100100;
4'b0011: result[6:0] = 7'b0110000;
4'b0100: resul... | 7.643178 |
module EightbitMangnitudeComparator (
Y,
A,
B
);
output [2:0] Y;
input [7:0] A, B;
wire [7:0] A, B;
reg [2:0] Y;
//always@(A or B or C)
initial begin
Y[2] = (A > B);
Y[1] = (A == B);
Y[0] = (A < B);
end
endmodule
| 7.076612 |
module EightbitMangnitudeComparator_tb;
wire [2:0] Y;
reg [7:0] A, B;
EightbitMangnitudeComparator EightbitMC (
Y,
A,
B
);
initial begin
#10;
A = 8'b00101111;
B = 8'b00000000;
#10;
A = 8'b11111111;
B = 8'b00000000;
#10;
A = 8'b00000000;
B = 8'b00000000;
... | 7.076612 |
module Eightbitparity (
input [7:0] inputbits,
output evenp,
output oddp
);
assign evenp = ^inputbits;
not (oddp, evenp);
endmodule
| 8.483338 |
module parity_tb;
reg [7:0] in;
wire op, ep;
Eightbitparity ebp_tb (
in,
ep,
op
);
initial begin
in = 8'b10101010;
#10 in = 8'b10101011;
#10 in = 8'b00000101;
#10 in = 8'b01001100;
end
initial $monitor($time, " input = %b; oddp = %b; evenp = %b;", in, op, ep);
endmodule... | 7.723264 |
module eightbitreg (
input [7:0] din,
input clk,
input rst,
output reg [7:0] gout
);
wire [7:0] g;
genvar j;
generate
for (j = 0; j <= 7; j = j + 1) begin : row
Dlatchreset UUT3 (
rst,
din[j],
clk,
g[j]
);
end
endgenerate
always @(pos... | 7.31295 |
module eightbitxor (
out,
in1,
in2
);
input [7:0] in1;
input [7:0] in2;
output [7:0] out;
xor (out[0], in1[0], in2[0]);
xor (out[1], in1[1], in2[1]);
xor (out[2], in1[2], in2[2]);
xor (out[3], in1[3], in2[3]);
xor (out[4], in1[4], in2[4]);
xor (out[5], in1[5], in2[5]);
xor (out[6], in1[... | 6.944138 |
module lab5Part1 (
input [1:0] SW,
input [0:0] KEY,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
assign LEDR[9:0] = 10'b0000000000; // all LEDs remain off
wire [7:0] Q_state; // current state of the counter circuit
/*
* KEY[0] is the clock signal
* SW[0] is the clear signal
... | 7.817871 |
module with asynchronous clear */
module t_flipFlop (input T, clock, clear, output reg Q, Q_p1);
// triggered on rising edge of the clock signal and falling edge of clear
always @(posedge clock, negedge clear)
begin
if (clear == 1'b0)
Q <= 1'b0; // active-low, asynchronous reset to 0
e... | 7.82962 |
module eightbit_usr (
input clk,
input sinr,
input sinl,
input clr,
input [1:0] op,
input [7:0] inp,
output [7:0] pout,
output soutr,
output soutl
);
wire sout1;
wire sout2;
fourbit_usr f1 (
clk,
sout2,
sinl,
clr,
op,
inp[3:0],
pout[3:... | 7.440676 |
module eightbyeight_sad (
clk,
aclr,
xpixels,
ypixels,
sad
);
input clk, aclr;
input [8*8*8-1:0] xpixels;
input [8*8*8-1:0] ypixels;
output reg [13:0] sad;
//////////////////////////////////
// difference pairs of pixels
// 32 units each costing 27 arithmetic cells = 864 cells
///... | 7.642803 |
module eightbyeight_sad_tb ();
reg clk, aclr;
reg [8*8*8-1:0] xpixels;
reg [8*8*8-1:0] ypixels;
wire [13:0] sad;
////////////////////////////////
// Test unit
eightbyeight_sad dut (
.clk(clk),
.aclr(aclr),
.xpixels(xpixels),
.ypixels(ypixels),
.sad(sad)
);
///////////... | 7.642803 |
module eightbyeight_sad_test (
clk,
aclr,
xin,
yin,
sad
);
input clk, aclr;
input xin, yin;
output [13:0] sad;
reg [8*8*8-1:0] xsr, ysr;
always @(posedge clk) begin
xsr <= (xsr << 1'b1) | xin;
ysr <= (ysr << 1'b1) | yin;
end
eightbyeight_sad dut (
.clk(clk),
.ac... | 7.642803 |
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