code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Eightb_dwn_cntr_top (
input wire load,
input wire [7:0] load_value,
input wire reset,
input wire CLOCK,
output reg CO
);
reg [7:0] count;
always @(posedge CLOCK or posedge reset) begin
if (reset) begin
count <= 8'b0;
end else begin
if (count == 8'... | 6.685988 |
module EightDataCompressUnit_tb;
reg clk;
reg reset;
reg wrtEn;
reg [32 * 8 - 1 : 0] dataIn;
reg [32 * 8 - 1 : 0] cprDataIn; // debug
reg [2 * 8 - 1 : 0] tagIn; // debug
wire [32 * 8 - 1 : 0] dataOut;
wire [2 * 8 - 1 : 0] tagOut;
initial b... | 7.131134 |
module EightDataCompressUnit_tb;
reg clk;
reg reset;
reg wrtEn;
reg [ 3 : 0] flags_in;
reg [32 * 8 - 1 : 0] dataIn;
wire [32 * 8 - 1 : 0] dataOut;
wire [2 * 8 - 1 : 0] tagOut;
wire [ 7 : 0] lenOut;
wire [ 3 : 0] flags_ou... | 7.131134 |
module EightDataCompressUnit_tb;
reg clk;
reg reset;
reg wrtEn;
reg validIn;
reg [32 * 8 - 1 : 0] dataIn;
reg [32 * 8 - 1 : 0] cprDataIn; // debug
reg [2 * 8 - 1 : 0] tagIn; // debug
wire [32 * 8 - 1 : 0] dataOut;
wire [2 ... | 7.131134 |
module EightDigitDisplay (
Clk,
Number,
out7,
en_out
);
input Clk;
input [31:0] Number;
output [6:0] out7; //seg a, b, ... g
output reg [7:0] en_out;
reg [3:0] in4;
reg [3:0] digit[7:0];
//--------- --------- --------- --------- //
//-- to use the module SevenSegment
SevenSegment m... | 7.999397 |
module CLK_Data (
rst,
clk_in,
clk_out
);
input rst, clk_in;
reg [20:0] counter;
output reg clk_out;
always @(posedge clk_in or posedge rst) begin
if (rst) begin
counter <= 21'b0;
clk_out <= 1'b0;
end
else if(counter == 21'd32)// 21'd10000000
begin
clk_out <= ~clk_out;... | 6.98207 |
module show (
rst,
clk,
Data,
ds,
seg
);
input clk, rst;
input [31:0] Data;
output reg [3:0] ds;
output reg [7:0] seg;
reg [2:0] BitSel;
reg [3:0] data;
always @(*) begin
case (data)
4'b0000: seg[7:0] <= 8'b00000011;
4'b0001: seg[7:0] <= 8'b10011111;
4'b0010: se... | 6.947557 |
module numerical (
stop,
rst,
clk,
data,
out
);
input rst;
input clk;
input stop;
output reg out;
output reg [3:0] data;
always @(posedge rst or posedge clk) begin
if (rst) begin
data <= 4'b0;
out <= 1'b0;
end else if (~stop) begin
if (data == 4'b1001) begin
... | 6.646604 |
module eightmux8_1 (
Out,
S,
InA,
InB,
InC,
InD,
InE,
InF,
InG,
InH
);
input [2:0] S;
input [15:0] InA, InB, InC, InD, InE, InF, InG, InH;
output [15:0] Out;
mux8_1 mux15 (
.Out(Out[15]),
.S (S[2:0]),
.InA(InA[15]),
.InB(InB[15]),
.InC(InC... | 6.644631 |
module EightToOneMux #(
parameter integer RV_BIT_NUM_EIGHT = `RV_BIT_NUM_EIGHT)
(
input [`MUX_WIDTH_EIGHT-1:0] sel,
input [(RV_BIT_NUM_EIGHT*`MUX_OPTION_EIGHT)-1 : 0] d,
output reg [RV_BIT_NUM_EIGHT-1:0]q);
always@(*) begin
case( sel )
`muxcaseeight(`MUX_WI... | 7.646945 |
module EIGHTtoONE_MUX16bit (
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
QA,
Q
);
input [15:0] R0; //input for each register that could propogate to the output
input [15:0] R1;
input [15:0] R2;
input [15:0] R3;
input [15:0] R4;
input [15:0] R5;
input [15:0] R6;
input [15:0] ... | 8.253844 |
module EightxOneMux #(
localparam WIDTH = 2,
DEPTH = 4
) (
input [ 2:0] RA,
input reg [DEPTH-1:0] Din0,
Din1,
Din2,
Din3,
Din4,
Din5,
Din6,
Din7, //4 registers of size 8 bits
output reg [DEPTH-1:0] RDout
);
always @(RA) begin
RDout = 4'd0; //reset on e... | 8.109988 |
module eight_adder (
input [7:0] A,
B, // input numbers
input Cin, // carry-in
output [7:0] S, // output sum
output Cout // carry-out
);
wire [6:0] carry; // for inter-stage carries
full_adder a0 (
A[0],
B[0],
Cin,
S[0],
carry[0]
);
full_adder a1 (
... | 6.876967 |
module eight_bitfull_adder (
A,
B,
Cin,
S,
carryout
);
input [7:0] A;
input [7:0] B;
input Cin;
output [7:0] S;
output carryout;
wire [6:0] Cout;
full_adder f1 (
.A(A[0]),
.B(B[0]),
.Cin(Cin),
.S(S[0]),
.Cout(Cout[0])
);
full_adder f2 (
.A(A[1]),... | 7.122288 |
module eight_bit_adder (
input cin,
// input a0,a1,a2,a3,a4,a5,a6,a7,
// input b0,b1,b2,b3,b4,b5,b6,b7,
// output s0,s1,s2,s3,s4,s5,s6,s7
input [15:0] a,
input [15:0] b,
output [15:0] s
);
wire t0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, ground;
FullAdder a... | 7.124161 |
module eight_bit_adder_7 (
input [7:0] x,
input [7:0] y,
input cin,
output reg [7:0] s,
output reg cout
);
wire [(4'h8+0)-1:0] M_fulladder_s;
wire [(4'h8+0)-1:0] M_fulladder_cout;
reg [(4'h8+0)-1:0] M_fulladder_x;
reg [(4'h8+0)-1:0] M_fulladder_y;
reg [(4'h8+0)-1:0] M_fulladder_cin;
... | 7.124161 |
module eight_bit_adder_reg (
input sys_clk,
input sys_rst_n,
input [7:0] in1,
input [7:0] in2,
input cn1,
output reg [8:0] results
);
reg [7:0] cnt;
wire [7:0] a;
wire [7:0] b;
assign a = cnt & in1;
assign b = cnt & in2;
wire [7:0] connect;
wire [7:0] out;
reg enable;
reg enab... | 7.124161 |
module eight_bit_adder_substractor (
input [7:0] a,
input [7:0] b,
input sel,
input enable,
output [7:0] s,
output cout
);
wire [1:7] c;
wire [7:0] w;
full_adder_substractor
g0 (
a[0],
b[0],
sel,
sel,
w[0],
c[1]
),
... | 7.124161 |
module eight_bit_alu (
input [7:0] a,
input [7:0] b,
input [10:0] op_code,
output reg [7:0] out, //should we save result for cumulative operations?
output reg [2:0] rem
);
//reg [2:0] remainder=0;
wire [7:0] out_add, out_sub, out_mult, out_div;
//wire add_c_out;
//eight_bit_adder EBA(.a(a),... | 6.984728 |
module: eight_bit_adder_substractor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module eight_bit_AS_tb;
// Inputs
reg [0:7] a;
reg [0:7] b;
reg sel;
reg enable;
// Outputs
wire... | 6.655034 |
module Eight_bit_block (
x,
y,
Cin,
Sout,
Gout,
Pout
);
input [7:0] x, y;
input Cin;
output [7:0] Sout;
output Gout, Pout;
wire p0, p1, p2, p3, p4, p5, p6, p7;
or p0_or (p0, x[0], y[0]);
or p1_or (p1, x[1], y[1]);
or p2_or (p2, x[2], y[2]);
or p3_or (p3, x[3], y[3]);
or p4_or... | 8.050123 |
module eight_bit_CLA (
Sum,
Cout,
A,
B,
Cin
);
input [7:0] A, B; // Make A and B 8-bit inputs
input Cin;
output [7:0] Sum; // Make Sum an 8-bit output
output Cout;
wire [7:0] G, P; // Create wires for the 8-bit generate and propagate values
wire C1, C2, C3, C4, C5, C6, C7; // Creat... | 7.248428 |
module eight_bit_claTB ();
reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;
//Instantiation
eight_bit_cla(
.A(a), .B(b), .C0(cin), .S(sum), .C8(cout)
);
initial begin : apply_stimulus
reg [7:0] invect;
cin = 1'b0;
for (invect = 0; invect < 129; invect = invect + 1) begin
i... | 6.50007 |
module eight_bit_comp (
input [7:0] a,
input [7:0] b,
output gt,
output eq,
output lt
);
wire [6:0] g;
wire [6:0] e;
wire [6:0] l;
reg xg = 1'b0;
reg xe = 1'b1;
reg xl = 1'b0;
one_bit_comp
c1 (
a[0],
b[0],
xg,
xe,
xl,
g[... | 7.255245 |
module eight_bit_comparator (
pb1,
pb2,
pb3,
pb4,
y,
lo,
go,
eo
);
input [3:0] y;
input pb1, pb2, pb3, pb4;
output lo, go, eo;
wire lo, go, eo;
wire l0, g0, e0, l1, g1, e1, l2, g2, e2;
wire l3, g3, e3, l4, g4, e4, l5, g5, e5;
wire l6, g6, e6;
reg [7:0] a, b;
always @(... | 7.255245 |
module: eight_bit_comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module eight_bit_comparator_tb;
// Inputs
reg [0:7] a;
reg [0:7] b;
reg enable;
// Outputs
wire G;
wire... | 7.828774 |
module: eight_bit_comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module eight_bit_comparator_top;
// Inputs
reg pb1;
reg pb2;
reg pb3;
reg pb4;
reg [3:0] y;
// Outputs
... | 7.828774 |
module Eight_Bit_Counter (
q,
clk,
reset
);
input reset, clk;
output [7:0] q;
ripple_carry_counter inst0 (
q,
clk,
reset
);
ripple_carry_counter inst1 (
q,
clk,
reset
);
endmodule
| 6.939472 |
module eight_bit_exponential_decay_lookup (
input wire [7:0] din,
output wire [7:0] dout
);
reg [0:7] exp_lookup[0:255];
initial $readmemh("picosoc/audio/exp_lookup_table.rom", exp_lookup);
assign dout = exp_lookup[din];
endmodule
| 7.336826 |
module eight_bit_multiplier(
input [7:0] A,
input [7:0] B,
output [16:0] Product
);
wire [8:0] pp_1 = {1'b1, !(A[7] && B[0]), (A[6] && B[0]), (A[5] && B[0]), (A[4] && B[0]), (A[3] && B[0]), (A[2] && B[0]), (A[1] && B[0]), (A[0] && B[0])};
wire [7:0] pp_2 = {!(A[7] && B[1]), (A[6]... | 7.284249 |
module eight_bit_parallel_register (
input [7:0] in,
input clk,
input enable,
input clear,
input preset,
output [7:0] out
);
//wire d[7:0];
wire outnot [7:0];
wire clkand;
and and0 (clkand, clk, enable);
//and and0(d[0],in[0],enable),
// and1(d[1],in[1],enable),
// and2(d[2],i... | 6.553039 |
module eight_bit_rca (
A,
B,
Cin,
S,
Cout
);
input [7:0] A, B;
input Cin;
output [7:0] S;
output Cout;
wire C1;
four_bit_rca f0 (
A[3:0],
B[3:0],
Cin,
S[3:0],
C1
);
four_bit_rca f1 (
A[7:4],
B[7:4],
C1,
S[7:4],
Cout
);
... | 6.852256 |
module eight_bit_rcaTB ();
reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;
//Instantiation
eight_bit_rca(
.A(a), .B(b), .Cin(cin), .S(sum), .Cout(cout)
);
initial begin : apply_stimulus
reg [7:0] invect;
cin = 1'b0;
for (invect = 0; invect < 129; invect = invect + 1) begin
... | 6.852256 |
module eight_bit_top (
input [7:0] a,
input [7:0] b,
input [10:0] op_code,
output reg [39:0] display
);
wire [7:0] out_math;
wire [9:0] pbcd1, pbcd2;
wire [2:0] rem;
parameter blank = 5'b11111; //good for 1 digits
eight_bit_alu EBA (
a,
b,
op_code,
out_math,
rem
... | 7.197805 |
module eight_colors (
output reg [7:0] redValue,
blueValue,
greenValue,
input pixelClock, // 50Mhz.
slowClock, // pixelClock/2^20 => 48Hz
input [10:0] XPixelPosition, // Position on x-axis. Increments on pixelClock with some deadzone at start and end.
YPixelPosition, // Position on y-axi... | 7.28263 |
module eight_mux (
A,
B,
C,
D,
E,
F,
G,
H,
CTRL,
Z
);
//parameter definitions
parameter N = 32; //define size of input or output buses
//port definitions - customize for different bit widths
input wire [N-1:0] A, B, C, D, E, F, G, H;
input wire [2:0] CTRL;
output w... | 8.134546 |
module eight_sign (
a,
b,
clk,
asign,
bsign,
m,
sign
);
input [7:0] a;
input [7:0] b;
input clk;
input asign;
input bsign;
output [15:0] m;
output sign;
wire s1, s2, s3, s4;
wire [7:0] f1;
wire [7:0] f2;
wire [7:0] f3;
wire [7:0] f4;
wire c1, c2, c3, c4, c5, c6, c7,... | 7.254869 |
module eight_sign_test;
reg [7:0] a;
reg [7:0] b;
reg clk;
reg asign;
reg bsign;
wire [15:0] m;
wire sign;
eight_sign PP (
a,
b,
clk,
asign,
bsign,
m,
sign
);
initial begin
a = 8'b00000011;
b = 8'b00000001;
asign = 1'b1;
bsign = 1'b1;
#10... | 7.038216 |
module eight_three (
n,
y
);
input [7:0] n;
output reg [2:0] y;
always @(*) begin
if (!n[7]) y = 3'b000;
else if (!n[6]) y = 3'b001;
else if (!n[5]) y = 3'b010;
else if (!n[4]) y = 3'b011;
else if (!n[3]) y = 3'b100;
else if (!n[2]) y = 3'b101;
else if (!n[1]) y = 3'b110;
e... | 6.577204 |
module eight_to_one (
dat,
sel,
out
);
parameter SEVEN_SEVEN_STYLE = 1'b0;
parameter FIVE_FIVE_STYLE = 1'b0;
input [7:0] dat;
input [2:0] sel;
output out;
wire out;
generate
if (SEVEN_SEVEN_STYLE) begin
wire cell_tail;
stratixii_lcell_comb lc_tail (
.datae(sel[1])... | 6.920789 |
module eight_to_one_line_mux (
input D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
S0,
S1,
S2,
output Q
);
assign Q = (D0&(~S0)&(~S1)&(~S2))|(D1&S0&(~S1)&(~S2))|(D2&(~S0)&S1&(~S2))|(D3&S0&S1&(~S2))|(D4&(~S0)&(~S1)&S2)|(D5&S0&(~S1)&S2)|(D6&(~S0)&S1&S2)|(D7&S0&S1&S2);
endmodule
| 6.584362 |
module eight_to_one_mux_8bit (
mux_out,
mux_in,
select
);
output reg [7:0] mux_out;
input [63:0] mux_in;
input [2:0] select;
always @(select, mux_in)
case (select)
3'b000: mux_out <= mux_in[7:0];
3'b001: mux_out <= mux_in[15:8];
3'b010: mux_out <= mux_in[23:16];
3'b011: ... | 6.584362 |
module eight_to_one_tb ();
reg [7:0] dat;
reg [2:0] sel;
reg fail = 0;
wire out_a, out_b, out_c;
eight_to_one a (
.dat(dat),
.sel(sel),
.out(out_a)
);
defparam a.SEVEN_SEVEN_STYLE = 1;
eight_to_one b (
.dat(dat),
.sel(sel),
.out(out_b)
);
defparam b.FIVE_FIVE_... | 6.584362 |
module eight_to_twenty #(
parameter WORD_LEN = 66
) (
input clk,
arst,
input [8*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output reg [20*WORD_LEN-1:0] dout,
input dout_ready,
output reg dout_valid
);
// Possible states :
// 0 : 20 out, no residue
// 1 : holdi... | 7.915108 |
module eim (
// EIM interface pins from CPU
input wire eim_bclk, // EIM burst clock. Started by the CPU.
input wire eim_cs0_n, // Chip select (active low).
inout wire [15 : 0] eim_da, // Bidirectional address and data port.
input wire [ 18:16] eim_a, // MSB part of ... | 8.268881 |
module eim_burstcnt (
input wire bclk,
// sync to bclk
input wire [15:0] bus_ad, // raw mux data
input wire [2:0] bus_a, // high address bits
input wire adv, // active high, so connect to !EIM_LBA
input wire rw, // low = write, high = read, so connect to EIM_RW
input wire cs, // active... | 7.193254 |
module for the EIM DA port.
//
//
// Author: Pavel Shatov
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain th... | 6.713113 |
module eim_indicator (
input wire sys_clk,
input wire sys_rst_n,
input wire eim_active,
output wire led_out
);
//
// Parameters
//
localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.
//
// Counter
//
reg [CNT_BITS... | 8.065689 |
module comm_regs (
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//-----------... | 8.701096 |
module ein_int(
input clk,
input reset,
output EMO_PAD,
output EDI_PAD,
output ECI_PAD,
input goc_mode,
input [31:0] CLK_DIV,
//Master input bus
input [7:0] ma_data,
input [7:0] ma_addr,
input ma_data_valid,
input ma_frame_valid,
inout sl_overflow,
//Slave output bus
input [8:0] sl_addr,
inout [8:... | 6.936239 |
module top (
input clk,
output uart_txd,
input uart_rxd,
output i2c_scl,
inout i2c_sda,
output spi_sclk,
output spi_mosi,
input spi_miso,
output spi_cs
);
wire [7:0] P1_out;
wire [7:0] P2_out;
wire i2c_scl;
wire i2c_sda_out;
wire i2c_sda_in;
wire i2c_sda_oen;
SB_... | 7.233807 |
module ej10;
reg [7:0] r8;
initial begin
r8 = 8'b0010_0110;
$display("Binario sin BIT de paridad: %b", r8);
r8[7] = ^r8[6:0];
$display("Binario con el BIT de paridad calculado: %b", r8);
end
endmodule
| 8.80149 |
module ej10;
reg [7:0] r8;
reg [7:0] paridad;
initial begin
r8 = 8'b0010_0110;
$display("Binario sin BIT de paridad: %b", r8);
paridad = ^r8; // Optenemos el bit de paridad que se almacena en la posicion 0
paridad = paridad << 7; // Movemos el bit 7 posicion para que se encuentre en la primera... | 8.80149 |
module ejer11;
initial begin
$display("Decimal del numero %h : %d", 'h1FEA, 'h1FEA);
$display("Decimal del numero %b : %d", 7'b1000101, 7'b1000101);
$display("Octal del numero %d : %o", 1234, 1234);
$display("Hexadecimal del numero binario %b :%h", 7'b1010011, 7'b1010011);
end
endmodule
| 7.618648 |
module ej13;
reg [15:0] reg16;
reg signed [15:0] reg16Signed;
reg signed [7:0] reg8Signed;
initial begin
reg16 = 2323;
$display("Numero %d en un registro de 16bits\nHexadecimal : %h \nBinario : %b", reg16, reg16,
reg16);
reg16 = 16'b1111_1111_1111_1111;
$display(
"\n\nMayor... | 9.357713 |
module ej20;
reg [15:0] reg16;
initial begin
reg16 = 16'b0000_1111_xxxx_zzzz;
$display("Registro con x y z en binario %b", reg16);
$display(
"Operaciones con el registro. \n\t suma = %d \n\tresta = %d \n\tMultiplicacion = %d \n\tDivision = %d",
reg16 + 1, reg16 - 1, reg16 * 1, reg16 / 1... | 8.568554 |
module ejemploPuertas;
reg [2:0] r;
wire salida, n1s, n2s, a1s, a2s, a3s, a4s, o1s, o2s;
not n1 (n1s, r[1]);
not n2 (n2s, r[0]);
and a1 (a1s, n1s, r[0]);
and a2 (a2s, r[1], r[0]);
and a3 (a3s, r[1], n2s);
and a4 (a4s, a3s, r[2]);
or o1 (o1s, r[0], a1s);
or o2 (o2s, a4s, a2s);
or o3 (salida, o1s... | 7.232544 |
module PB_debouncer #(
parameter N = 4
) (
input clock,
input reset,
input PB,
output reg PB_pressed_state,
output reg PB_pressed_pulse,
output reg PB_released_pulse,
// Las salidas state y counter se incluyen solo para depuracion y que puedan ser
// visualizadas en la simulacion del... | 8.452096 |
module can read and/or write data to a parallel I/O port based *
* on various user selected parameters. It has some predefined *
* configurations for some devices on the Altera DE boards. *
* *
*******... | 7.823047 |
module ejer2_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire... | 6.677166 |
module ejer2_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
in... | 6.677166 |
module ejer2_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] ... | 6.677166 |
module ejer2_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fi... | 6.677166 |
module can read and/or write data to a parallel I/O port based *
* on various user selected parameters. It has some predefined *
* configurations for some devices on the Altera DE boards. *
* *
*******... | 7.823047 |
module can read and/or write data to a parallel I/O port based *
* on various user selected parameters. It has some predefined *
* configurations for some devices on the Altera DE boards. *
* *
*******... | 7.823047 |
module ejtag_virtual_host (
TCK,
TMS,
TDO,
TDI,
TRST
);
input TDO;
output TCK, TDI, TMS, TRST;
reg [31:0] control;
reg [31:0] impcode;
reg [31:0] idcode;
reg [31:0] data;
reg [31:0] addr;
reg [31:0] pc;
reg TDI, TCK, TMS, TRST;
reg pracc;
reg prnw;
reg... | 6.649931 |
module EKF (
input signed [31:0] valpha,
vbeta,
ialpham,
ibetam,
input [31:0] nbSamples,
input clk,
reset,
output signed [31:0] omega,
theta,
output signed [31:0] ialphak,
ibetak,
kmatrix00,
kmatrix01,
kmatrix10,
kmatrix11,
kmatrix20,
kmatrix21,
km... | 6.991003 |
module EksBox (
CLK,
ARST_L,
SCLK,
SDATA,
HSYNC,
VSYNC,
RED,
GREEN,
BLUE,
SCLK_A,
SS,
INT1,
MISO,
MOSI,
MISO_PMOD,
MOSI_PMOD,
SS_PMOD,
SCLK_A_PMOD,
CLKOUT_DEBUG,
SWDB_INT_PMOD
);
input CLK, ARST_L, SCLK, SDATA, INT1, MISO;
output HSYNC,... | 6.807496 |
module elastic_buffer #(
parameter WIDTH = 32,
parameter SIZE = 256
) (
input clk,
input reset,
input [WIDTH-1:0] wr_data,
output reg [WIDTH-1:0] rd_data,
input ready_n,
input do_release_n
);
localparam ADDR_WIDTH = SIZE > 128 ? 7 :
SIZE > 64 ? 6 :
SIZE > 32 ? 5 :
SIZE > 16 ... | 10.453131 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module elbertv2_demo (
clkin,
dips,
segments,
anodes,
leds,
hsync,
vsync,
red,
green,
blue,
rxd,
txd
);
input clkin;
input [8:1] dips;
output [7:0] segments;
output [3:1] anodes;
output [8:1] leds;
output hsync, vsync;
output [2:0] red, green;
output [1:... | 7.926197 |
module ELB_IS_ERRO (
clk,
rstN,
out_a,
out_b,
sel
);
input clk, rstN, sel;
output reg [2:0] out_a, out_b;
reg [2:0] next_state;
logic log;
always_comb deassign log;
always @(posedge clk, negedge rstN) begin
if (~rstN) out_a <= 0;
else out_a <= next_state;
end
endmodule
| 6.761228 |
module Electric_Piano (
input clk_in, //system clock
input rst_n_in, //system reset
input [3:0] col,
output [3:0] row,
output piano_out
);
wire [15:0] key_out;
wire [15:0] key_pulse;
//Array_KeyBoard
Array_KeyBoard Array_KeyBoard_uut (
.clk_in (clk_in),
... | 6.965453 |
module elec_piano(
input clk,
input ps2_clk,
input ps2_data,
output reg [15:0] freq,
output reg [6:0] volume
);
wire [7:0] data;
reg [15:0] eight_note [7:0];
reg break;
ps2_keyboard pk(
.clk(clk),
.clrn(1),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.nextdata_n(0),
.data(data)
);
initial begin
freq <= 0;... | 9.29798 |
module Elemento_Contatore_Base_3 (
eu,
q3_q0,
ei,
clock,
reset_
);
input clock, reset_;
input ei;
output eu;
output [3:0] q3_q0;
reg [3:0] OUTR;
assign q = OUTR;
wire [3:0] a1_a0; // variabile di uscita dell'incrementatore
assign {a1_a0, eu} = ({q3_q0, ei} == 'B00000) ? 'B00000 :... | 7.032471 |
module Elemento_Contatore_Base_2(eu, q, ei, clock, reset_);
input clock, reset_;
input ei;
output eu, q;
reg OUTR;
assign q=OUTR;
wire a; // variabile di uscita dell'incrementatore
assign {a, eu} = ({q, ei} == 'B00)? 'B00:
({q, ei} == 'B10)? 'B10:
... | 7.032471 |
module Elemento_Contatore_Base_3 (
eu,
q1_q0,
ei,
clock,
reset_
);
input clock, reset_;
input ei;
output eu;
output [1:0] q1_q0;
reg [1:0] OUTR;
assign q = OUTR;
wire [1:0] a1_a0; // variabile di uscita dell'incrementatore
assign {a1_a0, eu} = ({q1_q0, ei} == 'B000)?'B000:
... | 7.032471 |
module e_Mat_mult (
A,
B,
Res
);
//input and output ports.
//The size 72 bits which is 3*3=9 elements,each of which is 8 bits wide.
input [71:0] A;
input [71:0] B;
output [71:0] Res;
//internal variables
reg [71:0] Res;
reg [ 7:0] A1 [0:2][0:2];
reg [ 7:0] B1 [0:2][0:2];
reg [... | 7.673214 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module music1 (
input clk,
input onoff,
input [6:0] note,
output o
);
parameter doo = (25000000 / 262 / 2);
parameter re = (25000000 / 294 / 2);
parameter mi = (25000000 / 330 / 2);
parameter fa = (25000000 / 349 / 2);
parameter sol = (25000000 / 392 / 2);
parameter la = (25000000 / 440 / 2)... | 7.609876 |
module ElevatorController #(
parameter CLK_PER_OPEN = 5,
CLK_PER_MOVE = 10,
CLK_PER_HOLD = 10
) (
input clk,
input reset,
input [11:0] newRealFloorButton,
input [ 9:1] newInternalButton1,
input [ 9:1] newInternalButton2,
input [ 9:1] newInternalButton3,
output... | 6.923948 |
module EleCont_Test;
// Inputs
reg clk;
reg reset;
reg [11:0] nRFB;
reg [ 9:1] nIB1;
reg [ 9:1] nIB2;
// Outputs
wire [ 2:0] currentFloor1;
wire [ 2:0] currentFloor2;
wire [ 1:0] currentDirection1;
wire [ 1:0] currentDirection2;
wire [11:0] currentRealFloorButton;
wire [ 9... | 7.685862 |
module ElevatorControlWCommunicator#(parameter CLKFRQ = 100000000,
BAUDRATE = 9600,
CLK_PER_OPEN = 5,
CLK_PER_MOVE = 10,
CLK_PER_HOLD = 5)
(
input clk,
input r... | 6.923948 |
module for Elevator Control project
This example code can also be found in Chapter 5.3 of the STEPFPGA tutorial book written by EIM Technology.
Website: www.eimtechnology.com
Copyright License: MIT
*/
module elevatorCtrl(
input clk, rst_n , // connect to system clock 12MHz and a pushbutton for reset
input ech... | 7.152559 |
module dff (
input clk,
D,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
| 7.174483 |
module divider_integer #(
parameter WIDTH = 24,
parameter N = 12000000
) (
input clk,
output reg clkout
);
reg [WIDTH-1:0] cnt;
always @(posedge clk) begin
if (cnt >= (N - 1)) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
clkout <= (cnt < N / 2) ? 1'b1 : 1'b0;
end
endmodule
| 6.687714 |
module bin_to_bcd (
input rst_n,
input [15:0] bin_code,
output reg [19:0] bcd_code
);
reg [35:0] shift_reg;
always @(bin_code or rst_n) begin
shift_reg = {20'h0, bin_code};
if (!rst_n) bcd_code = 0;
else begin
repeat (16) begin // repeat for 16 times
if (shift_reg[19:16] >... | 7.085337 |
module segment7 (
input wire [3:0] seg_data,
output reg [8:0] segment_led
// MSB~LSB = SEG, DP, g, f e, d, c, b, a
);
always @(seg_data) begin
case (seg_data)
4'b0000: segment_led = 9'h3f; // 0
4'b0001: segment_led = 9'h06; // 1
4'b0010: segment_led = 9'h5b; // 2
... | 6.533074 |
module for Elevator Control project
This example code can also be found in Chapter 5.3 of the STEPFPGA tutorial book written by EIM Technology.
Website: www.eimtechnology.com
Copyright License: MIT
*/
module elevatorCtrl(
input clk, rst_n , // connect to system clock 12MHz and a pushbutton for reset
input ech... | 7.152559 |
module elevatorfsm (
clk,
clr_,
w
);
input clk, clr_;
// The input for floors, is a 3 bit input
input [2:0] w;
// Represents current and new states
reg [2:0] y, Y;
// Each of our states for the floors of elevator
// Ground Floor, Floor 2, Floor 3, Floor 4
localparam A = 3'b001, B = 3'b01... | 7.708481 |
module elevatorTop (
clk,
reset,
open_btn,
close_btn,
B1U,
B2D,
B2U,
B3D,
B3U,
B4D,
BF1,
BF2,
BF3,
BF4,
door,
dir,
state
);
input clk, reset, open_btn, close_btn, B1U, B2D, B2U, B3D, B3U, B4D, BF1, BF2, BF3, BF4;
inout door, dir;
inout [2:0] stat... | 7.351755 |
module elevatorTop_tb;
reg
clk,
reset,
door_sensor,
open_btn,
close_btn,
B1U,
B2D,
B2U,
B3D,
B3U,
B4D,
BF1,
BF2,
BF3,
BF4;
wire door, dir;
wire [2:0] state;
elevatorTop UUT (
clk,
reset,
door_sensor,
... | 7.396948 |
module elevator_clk (
clk,
clock
);
input clk;
output reg clock;
reg [31 : 0] times;
reg flag;
initial begin
clock = 1'b0;
times = 32'd0;
flag = 1'b0;
end
always @(clk) begin
if(times < 32'd16 && flag == 1'b0) begin //产生1Hz信号 占空比80% 测试使用16 实际应为160000000
times <= times +... | 6.50844 |
module elevator_mux (
input sclk, //clk de un cuarto segundo
input elev,
input [1:0] floor,
output reg w0,
output reg w1,
output reg in0,
output reg in1,
output reg [1:0] addr
);
reg [1:0] counter;
wire [2:0] change = {floor, elev};
always @(sclk) begin
counter = counter + ... | 6.615871 |
module elevator_openDoor(clock,currentFloor,door);
parameter floor = 6;
input clock;
input currentFloor;
output [floor-1 :0] door;
reg flag = 1'b0; 先检测到低电平为1，高电平为0
reg [floor-1 :0] Door
initial begin
end
assign door = Door;
always @(clock)
if(!clock) begin
case(currentFloor)
1:Door <= 6'b000001;
2:Doo... | 6.88665 |
module elevator_tb ();
reg clk;
reg rst;
reg [3:0] des_floor;
output [3:0] cur_floor; // 1, 2, 3, 4
output is_open; // 0 close, 1 open
output [1:0] move; // 0 stop, 1 up, 2 down
output [3:0] clr;
initial begin
$dumpfile("wave.vcd"); //生成的vcd文件名称
$dumpvars(0, elevator_tb); //tb模块名称
clk ... | 6.647914 |
module elevator_test;
//reg clk; //电梯基准时钟
//reg [3 :0] outsideUp; //电梯外上升请求按钮
//reg [3 :0] outsideDown; //电梯外下降请求按钮
//reg [3 :0] insideFloor; //电梯内楼层按钮
//wire [3 :0] queueUp,queueDown,queueinside; //电梯请求楼层序列
//
//
//initial begin
// clk = 1'b0;
// outsideUp ... | 7.832202 |
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