code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module elevator_testbench;
// Inputs
reg CLK, RST;
reg [3:0] BCD_management;
reg [2:0] interior_movement, exterior_movement;
// Outputs
wire [1:0] engine;
wire [2:0] doors;
// Instantiate the Unit Under Test (UUT)
elevator uut (
.CLK(CLK),
.RST(RST),
.BCD_management(BCD_management... | 7.832202 |
module elevator_top (
input clk,
reset,
Dsensor,
Emergency,
Dopen,
Dclose,
F1,
F2,
F3,
F4,
F1up,
F2down,
F2up,
F3down,
F3up,
F4down,
output reg [6:0] floordisp, //7-segment display for current floor
output reg [6:0] statedisp, //7-segment display... | 6.785595 |
module Ele_each_test;
// Inputs
reg clk;
reg reset;
reg [13:0] newbutton;
reg [ 9:1] newIbutton;
reg [13:0] floorButton;
reg [ 9:1] internalButton;
// Outputs
wire [ 2:0] nextFloor;
wire [ 1:0] nextDirection;
wire [13:0] nextFloorButton;
wire [ 9:1] nextInternalButton;
wi... | 7.219861 |
module elink2_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire reset = ~aresetn;
// Remove param_coreid, it now seems to come from
// ecfg
// wire [11:0] param_coreid = 12'h810;
wire [2:0] done;
wire [2:0] error;
// Create an instance of the example tb
elink_testbench dut (
... | 7.612963 |
module elink_aligner (
input clk,
input [63:0] in,
input [7:0] mask,
output reg [111:0] out,
output reg out_valid,
output [7:0] b0,
output [3:0] ctrlmode,
output [31:0] dest_addr,
output write,
output access,
output [1:0] datamode,
output [31:0] data,
output [31:0] s... | 7.269849 |
module elink_cfg ( /*AUTOARG*/
// Outputs
txwr_gated_access,
etx_soft_reset,
erx_soft_reset,
clk_config,
chipid,
// Inputs
clk,
nreset,
txwr_access,
txwr_packet
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID =... | 7.710323 |
module e16_arbiter_priority ( /*AUTOARG*/
// Outputs
grant,
arb_wait,
// Inputs
clk,
clk_en,
reset,
hold,
request
);
parameter ARW = 99;
input clk;
input clk_en;
input reset;
input hold;
input [ARW-1:0] request;
output [ARW-1:0] grant;
output [ARW-1:0] arb_wait;
... | 7.436413 |
module e16_clock_divider ( /*AUTOARG*/
// Outputs
clk_out,
clk_out90,
// Inputs
clk_in,
reset,
div_cfg
);
input clk_in; // Input clock
input reset;
input [3:0] div_cfg; // Divide factor
output clk_out; // Divided clock phase aligned with clk_in
output clk_out90; // Divided... | 6.505541 |
module e16_mesh_interface ( /*AUTOARG*/
// Outputs
wait_out,
access_out,
write_out,
datamode_out,
ctrlmode_out,
data_out,
dstaddr_out,
srcaddr_out,
access_reg,
write_reg,
datamode_reg,
ctrlmode_reg,
data_reg,
dstaddr_reg,
srcaddr_reg,
// Inputs
cl... | 6.528562 |
module e16_mux7 ( /*AUTOARG*/
// Outputs
out,
// Inputs
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6
);
parameter DW = 99;
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [D... | 6.623983 |
module e16_pulse2pulse ( /*AUTOARG*/
// Outputs
out,
// Inputs
inclk,
outclk,
in,
reset
);
//clocks
input inclk;
input outclk;
input in;
output out;
//reset
input reset; //do we need this???
wire intoggle;
wire insync;
//pulse to toggle
pulse2toggle pulse2to... | 7.126322 |
module e16_pulse2toggle ( /*AUTOARG*/
// Outputs
out,
// Inputs
clk,
in,
reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset; //do we need this???
reg out;
wire toggle;
//if input goes high, toggle output
//note1: input can only be high for one cl... | 6.906659 |
module e16_synchronizer #(
parameter DW = 32
) ( /*AUTOARG*/
// Outputs
out,
// Inputs
in,
clk,
reset
);
//Input Side
input [DW-1:0] in;
input clk;
input reset; //asynchronous signal
//Output Side
output [DW-1:0] out;
reg [DW-1:0] sync_reg0;
reg [DW-1:0] sync_reg1;
... | 7.297594 |
module link_rxi_ctrl ( /*AUTOARG*/
// Outputs
lclk,
// Inputs
io_lclk,
rxi_cfg_reg
);
parameter DW = `CFG_DW;
//Input clock
input io_lclk; //link clock from IO
input [DW-1:0] rxi_cfg_reg; //used to deskew clock input
//Should we have a monitor pin for locking the timing?
//Delay... | 6.545612 |
module link_rxi_router ( /*AUTOARG*/
// Outputs
fifo_read_cvre,
read_out,
write_out,
dst_addr_out,
src_addr_out,
data_out,
datamode_out,
ctrlmode_out,
// Inputs
fifo_data_out_cvre,
fifo_empty_cvre,
wait_in
);
parameter AW = 32;
parameter MDW = 32;
parameter FW... | 7.228707 |
module link_txo_buffer ( /*AUTOARG*/
// Outputs
txo_data_even,
txo_data_odd,
txo_frame,
// Inputs
c0_tran_frame_tlc,
c0_tran_byte_even_tlc,
c0_tran_byte_odd_tlc,
c1_tran_frame_tlc,
c1_tran_byte_even_tlc,
c1_tran_byte_odd_tlc,
c2_tran_frame_tlc,
c2_tran_byte_even_tlc,... | 7.17364 |
module link_txo_channel ( /*AUTOARG*/
// Outputs
emesh_wait_out,
txo_launch_req_tlc,
txo_rotate_dis,
tran_frame_tlc,
tran_byte_even_tlc,
tran_byte_odd_tlc,
// Inputs
cclk,
cclk_en,
txo_lclk,
reset,
txo_rd,
txo_cid,
cfg_burst_dis,
emesh_tran_in,
emesh_... | 6.626665 |
module link_txo_interface ( /*AUTOARG*/
// Outputs
txo_data,
txo_frame,
txo_wr_wait_int,
txo_rd_wait_int,
// Inputs
txo_lclk,
reset,
txo_wr_data_even,
txo_wr_data_odd,
txo_wr_frame,
txo_wr_launch_req_tlc,
txo_wr_rotate_dis,
txo_rd_data_even,
txo_rd_data_odd,
... | 6.827353 |
module MX2X4A12TR (
A,
B,
S0,
Y
);
input A, B, S0;
output Y;
wire N3, N6;
and C1 (N3, S0, B);
and C3 (N6, S0__br_in_not, A);
not (S0__br_in_not, S0);
or C4 (Y, N3, N6);
endmodule
| 6.840785 |
module elink_lvds (
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock);
input [8:0] rx_in;
input rx_inclock;
output rx_locked;
output [71:0] rx_out;
output rx_outclock;
wire sub_wire0;
wire [71:0] sub_wire1;
wire sub_wire2;
wire rx_locked = sub_wire0;
wire [71:0] rx_out = sub_wire1[71:0];
w... | 6.831924 |
module elink_lvds (
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock
);
input [8:0] rx_in;
input rx_inclock;
output rx_locked;
output [71:0] rx_out;
output rx_outclock;
endmodule
| 6.831924 |
module elink_monitor ( /*AUTOARG*/
// Inputs
frame,
clk,
din
);
parameter AW = 32;
parameter PW = 2 * AW + 40;
input frame;
input clk;
input [7:0] din;
reg [ 3:0] cycle;
reg read;
reg [ 31:0] dstaddr;
reg [ 31:0] srcaddr;
reg [ 31:0] data;
reg [ 3:0] ctrlmode;
... | 7.059343 |
module elink_serdes_receiver (
input wire [7:0] in,
input wire frame_in,
input wire lclk,
output wire locked,
output wire pclk,
output wire [63:0] out,
output wire [ 7:0] out_mask
);
wire [71:0] data;
// Instantiate an ALTLVDS_RX hard IP with 600Mbit per channel, 9 bit input
// and... | 7.853687 |
module elink_testbench_wrapper (
aclk,
aresetn,
csysreq,
done0,
done1,
done2,
error0,
error1,
error2,
reset,
rx_cclk_n,
rx_cclk_p,
start
);
input aclk;
input aresetn;
input csysreq;
output done0;
output done1;
output done2;
output error0;
output error1... | 6.622931 |
module ELM_Mitchw2 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
wire [ 1:0] sign_factor;
wire [16:0] PP_2;
wire [14:0] PP_1;
wire [27:0] PP_0;
// Calculates PP_2 = Y*X1
PP_2_gen High (
.x1(x[15:13]),
.y(y),
.sign_factor(sign_factor[1]),
.PP(PP_2)
);
// Cal... | 7.480149 |
module PP_2_gen (
input [2:0] x1,
input [15:0] y,
output sign_factor,
output [16:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (x1[2]),
.y1 (x1[1]),
.y0 (x1[0])
);
// generation of PP
wire [16:0... | 7.200302 |
module PP_1_gen (
input [13:0] x,
input [2:0] y1,
output sign_factor,
output [14:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (y1[2]),
.y1 (y1[1]),
.y0 (y1[0])
);
// generation of PP
wire [14:0... | 7.531719 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module LOD14 (
input [13:0] data_i,
output zero_o,
output [13:0] data_o
);
wire [13:0] z;
wire [ 3:0] zdet;
wire [ 3:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = |(data_i[13:12]);
assign zdet[2] ... | 7.629931 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
//gates and IO assignments:
assign data_o[1] = data_i[1];
assign data_o[0] = (~data_i[1] & data_i[0]);
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module Muxes2in1Array2 (
input [1:0] data_i,
input select_i,
output [1:0] data_o
);
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_14 (
input [13:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
14'b00000000000001: code_o = 4'b0000;
14'b00000000000010: code_o = 4'b0001;
14'b00000000000100: code_o = 4'b0010;
14'b00000000001000: code_o = 4'b0011;
14'b00000000010000: cod... | 6.599169 |
module PriorityEncoder_14v2 (
input [13:0] data_i,
output [ 3:0] code_o
);
wire tmp10, tmp20, tmp30, tmp40;
assign tmp10 = ~(~(data_i[1] | data_i[3]) & ~data_i[5]);
assign tmp20 = ~(~(data_i[7] | data_i[9]) & ~data_i[11]);
assign code_o[0] = tmp10 & tmp20;
assign tmp30 = ~(~(data_i[2] | data_i[3])... | 6.599169 |
module LBarrel (
input [13:0] data_i,
input [13:0] shift_i,
output data_o
);
//assign data_o = ~&(~(data_i[11:0] & shift_i[12:1]));
wire [11:0] tmp1_l; //a,b
wire [ 5:0] tmp2_l; // c
wire [ 2:0] tmp3_l; //d
assign tmp1_l = ~(data_i[11:0] & shift_i[12:1]);
assign tmp2_l = ~(tmp1_l[11:6] & tmp... | 6.741724 |
module L1Barrel (
input [1:0] data_i,
input [3:0] shift_i,
output reg [17:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0... | 6.641517 |
module RBarell (
input data_i,
input shift_i,
output [1:0] data_o
);
assign data_o[1] = ~shift_i;
assign data_o[0] = shift_i | data_i;
endmodule
| 7.721933 |
module PP_add (
input [ 1:0] sign_factor,
input [16:0] PP_2,
input [14:0] PP_1,
input [27:0] PP_0,
output [31:0] p
);
// generate negative MSBs
wire [2:0] E_MSB;
assign E_MSB[0] = ~PP_0[27];
assign E_MSB[1] = ~PP_1[14];
assign E_MSB[2] = ~PP_2[16];
// Reduction
// First redu... | 6.806805 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ELM_Mitchw3 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
wire [ 1:0] sign_factor;
wire [16:0] PP_2;
wire [14:0] PP_1;
wire [27:0] PP_0;
// Calculates PP_2 = Y*X1
PP_2_gen High (
.x1(x[15:13]),
.y(y),
.sign_factor(sign_factor[1]),
.PP(PP_2)
);
// Cal... | 7.230423 |
module PP_2_gen (
input [2:0] x1,
input [15:0] y,
output sign_factor,
output [16:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (x1[2]),
.y1 (x1[1]),
.y0 (x1[0])
);
// generation of PP
wire [16:0... | 7.200302 |
module PP_1_gen (
input [13:0] x,
input [2:0] y1,
output sign_factor,
output [14:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (y1[2]),
.y1 (y1[1]),
.y0 (y1[0])
);
// generation of PP
wire [14:0... | 7.531719 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module LOD14 (
input [13:0] data_i,
output zero_o,
output [13:0] data_o
);
wire [13:0] z;
wire [ 3:0] zdet;
wire [ 3:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = |(data_i[13:12]);
assign zdet[2] ... | 7.629931 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
//gates and IO assignments:
assign data_o[1] = data_i[1];
assign data_o[0] = (~data_i[1] & data_i[0]);
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module Muxes2in1Array2 (
input [1:0] data_i,
input select_i,
output [1:0] data_o
);
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_14 (
input [13:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
14'b00000000000001: code_o = 4'b0000;
14'b00000000000010: code_o = 4'b0001;
14'b00000000000100: code_o = 4'b0010;
14'b00000000001000: code_o = 4'b0011;
14'b00000000010000: cod... | 6.599169 |
module PriorityEncoder_14v2 (
input [13:0] data_i,
output [ 3:0] code_o
);
wire tmp10, tmp20, tmp30, tmp40;
assign tmp10 = ~(~(data_i[1] | data_i[3]) & ~data_i[5]);
assign tmp20 = ~(~(data_i[7] | data_i[9]) & ~data_i[11]);
assign code_o[0] = tmp10 & tmp20;
assign tmp30 = ~(~(data_i[2] | data_i[3])... | 6.599169 |
module LBarrel (
input [13:0] data_i,
input [13:0] shift_i,
output [ 1:0] data_o
);
//assign data_o[1] = |(data_i[11:0] & shift_i[12:1]);
wire [11:0] tmp1_l; //a,b
wire [ 5:0] tmp2_l; // c
wire [ 2:0] tmp3_l; //d
assign tmp1_l = ~(data_i[11:0] & shift_i[12:1]);
assign tmp2_l = ~(tmp1_l[11:... | 6.741724 |
module L1Barrel (
input [2:0] data_i,
input [3:0] shift_i,
output reg [18:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0... | 6.641517 |
module RBarell (
input [1:0] data_i,
input [1:0] shift_i,
output [2:0] data_o
);
assign data_o[2] = ~(shift_i[0] | shift_i[1]);
assign data_o[1] = ~shift_i[1] | (data_i[1] & ~shift_i[0]);
assign data_o[0] = (~shift_i[0] & data_i[0]) | (~shift_i[0] & shift_i[1]) | (~shift_i[1] & shift_i[0] & data_i[... | 7.721933 |
module PP_add (
input [ 1:0] sign_factor,
input [16:0] PP_2,
input [14:0] PP_1,
input [27:0] PP_0,
output [31:0] p
);
// generate negative MSBs
wire [2:0] E_MSB;
assign E_MSB[0] = ~PP_0[27];
assign E_MSB[1] = ~PP_1[14];
assign E_MSB[2] = ~PP_2[16];
// Reduction
// First redu... | 6.806805 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ELM_Mitchw4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
wire [ 1:0] sign_factor;
wire [16:0] PP_2;
wire [14:0] PP_1;
wire [27:0] PP_0;
// Calculates PP_2 = Y*X1
PP_2_gen High (
.x1(x[15:13]),
.y(y),
.sign_factor(sign_factor[1]),
.PP(PP_2)
);
// Cal... | 7.811285 |
module PP_2_gen (
input [2:0] x1,
input [15:0] y,
output sign_factor,
output [16:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (x1[2]),
.y1 (x1[1]),
.y0 (x1[0])
);
// generation of PP
wire [16:0... | 7.200302 |
module PP_1_gen (
input [13:0] x,
input [2:0] y1,
output sign_factor,
output [14:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (y1[2]),
.y1 (y1[1]),
.y0 (y1[0])
);
// generation of PP
wire [14:0... | 7.531719 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module LOD14 (
input [13:0] data_i,
output zero_o,
output [13:0] data_o
);
wire [13:0] z;
wire [ 3:0] zdet;
wire [ 3:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = |(data_i[13:12]);
assign zdet[2] ... | 7.629931 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
//gates and IO assignments:
assign data_o[1] = data_i[1];
assign data_o[0] = (~data_i[1] & data_i[0]);
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module Muxes2in1Array2 (
input [1:0] data_i,
input select_i,
output [1:0] data_o
);
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_14 (
input [13:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
14'b00000000000001: code_o = 4'b0000;
14'b00000000000010: code_o = 4'b0001;
14'b00000000000100: code_o = 4'b0010;
14'b00000000001000: code_o = 4'b0011;
14'b00000000010000: cod... | 6.599169 |
module PriorityEncoder_14v2 (
input [13:0] data_i,
output [ 3:0] code_o
);
wire tmp10, tmp20, tmp30, tmp40;
assign tmp10 = ~(~(data_i[1] | data_i[3]) & ~data_i[5]);
assign tmp20 = ~(~(data_i[7] | data_i[9]) & ~data_i[11]);
assign code_o[0] = tmp10 | tmp20;
assign tmp30 = ~(~(data_i[2] | data_i[3])... | 6.599169 |
module LBarrel (
input [13:0] data_i,
input [13:0] shift_i,
output [ 2:0] data_o
);
//assign data_o[2] = |(data_i[11:0] & shift_i[12:1]);
wire [11:0] tmp1_l; //a,b
wire [ 5:0] tmp2_l; // c
wire [ 2:0] tmp3_l; //d
assign tmp1_l = ~(data_i[11:0] & shift_i[12:1]);
assign tmp2_l = ~(tmp1_l[1... | 6.741724 |
module L1Barrel (
input [3:0] data_i,
input [3:0] shift_i,
output reg [19:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0... | 6.641517 |
module RBarell (
input data_i,
input shift_i,
output [1:0] data_o
);
assign data_o[1] = ~shift_i;
assign data_o[0] = shift_i | data_i;
endmodule
| 7.721933 |
module PP_add (
input [ 1:0] sign_factor,
input [16:0] PP_2,
input [14:0] PP_1,
input [27:0] PP_0,
output [31:0] p
);
// generate negative MSBs
wire [2:0] E_MSB;
assign E_MSB[0] = ~PP_0[27];
assign E_MSB[1] = ~PP_1[14];
assign E_MSB[2] = ~PP_2[16];
// Reduction
// First redu... | 6.806805 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ELM_Mitchw4_v2 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
wire [ 1:0] sign_factor;
wire [16:0] PP_2;
wire [14:0] PP_1;
wire [27:0] PP_0;
// Calculates PP_2 = Y*X1
PP_2_gen High (
.x1(x[15:13]),
.y(y),
.sign_factor(sign_factor[1]),
.PP(PP_2)
);
// ... | 7.817446 |
module PP_2_gen (
input [2:0] x1,
input [15:0] y,
output sign_factor,
output [16:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (x1[2]),
.y1 (x1[1]),
.y0 (x1[0])
);
// generation of PP
wire [16:0... | 7.200302 |
module PP_1_gen (
input [13:0] x,
input [2:0] y1,
output sign_factor,
output [14:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (y1[2]),
.y1 (y1[1]),
.y0 (y1[0])
);
// generation of PP
wire [14:0... | 7.531719 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module LOD14 (
input [13:0] data_i,
output zero_o,
output [13:0] data_o
);
wire [13:0] z;
wire [ 3:0] zdet;
wire [ 3:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = |(data_i[13:12]);
assign zdet[2] ... | 7.629931 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
//gates and IO assignments:
assign data_o[1] = data_i[1];
assign data_o[0] = (~data_i[1] & data_i[0]);
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module Muxes2in1Array2 (
input [1:0] data_i,
input select_i,
output [1:0] data_o
);
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_14 (
input [13:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
14'b00000000000001: code_o = 4'b0000;
14'b00000000000010: code_o = 4'b0001;
14'b00000000000100: code_o = 4'b0010;
14'b00000000001000: code_o = 4'b0011;
14'b00000000010000: cod... | 6.599169 |
module PriorityEncoder_14v2 (
input [13:0] data_i,
output [ 3:0] code_o
);
wire tmp10, tmp20, tmp30, tmp40;
assign tmp10 = ~(~(data_i[1] | data_i[3]) & ~data_i[5]);
assign tmp20 = ~(~(data_i[7] | data_i[9]) & ~data_i[11]);
assign code_o[0] = tmp10 | tmp20;
assign tmp30 = ~(~(data_i[2] | data_i[3])... | 6.599169 |
module LBarrel (
input [13:0] data_i,
input [13:0] shift_i,
output [ 2:0] data_o
);
//assign data_o[2] = |(data_i[11:0] & shift_i[12:1]);
wire [11:0] tmp1_l; //a,b
wire [ 5:0] tmp2_l; // c
wire [ 2:0] tmp3_l; //d
assign tmp1_l = ~(data_i[11:0] & shift_i[12:1]);
assign tmp2_l = ~(tmp1_l[1... | 6.741724 |
module L1Barrel (
input [3:0] data_i,
input [3:0] shift_i,
output reg [19:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0... | 6.641517 |
module RBarell (
input data_i,
input shift_i,
output [1:0] data_o
);
assign data_o[1] = ~shift_i;
assign data_o[0] = shift_i | data_i;
endmodule
| 7.721933 |
module PP_add (
input [ 1:0] sign_factor,
input [16:0] PP_2,
input [14:0] PP_1,
input [27:0] PP_0,
output [31:0] p
);
// generate negative MSBs
wire [2:0] E_MSB;
assign E_MSB[0] = ~PP_0[27];
assign E_MSB[1] = ~PP_1[14];
assign E_MSB[2] = ~PP_2[16];
// Reduction
// First redu... | 6.806805 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module ELM_Mitchw5 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
wire [ 1:0] sign_factor;
wire [16:0] PP_2;
wire [14:0] PP_1;
wire [27:0] PP_0;
// Calculates PP_2 = Y*X1
PP_2_gen High (
.x1(x[15:13]),
.y(y),
.sign_factor(sign_factor[1]),
.PP(PP_2)
);
// Cal... | 7.775881 |
module PP_2_gen (
input [2:0] x1,
input [15:0] y,
output sign_factor,
output [16:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (x1[2]),
.y1 (x1[1]),
.y0 (x1[0])
);
// generation of PP
wire [16:0... | 7.200302 |
module PP_1_gen (
input [13:0] x,
input [2:0] y1,
output sign_factor,
output [14:0] PP
);
// encode
wire one, two, sign;
code encode_block (
.one (one),
.two (two),
.sign(sign),
.y2 (y1[2]),
.y1 (y1[1]),
.y0 (y1[0])
);
// generation of PP
wire [14:0... | 7.531719 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
one,
two,
sign,
p,
i
);
input x1, x0, sign, one, two;
output p, i;
wire [1:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o1 (p, k[1], k[0]);
endmodule
| 6.586499 |
module LOD14 (
input [13:0] data_i,
output zero_o,
output [13:0] data_o
);
wire [13:0] z;
wire [ 3:0] zdet;
wire [ 3:0] select;
//*****************************************
// Zero detection logic:
//*****************************************
assign zdet[3] = |(data_i[13:12]);
assign zdet[2] ... | 7.629931 |
module LOD2 (
input [1:0] data_i,
output [1:0] data_o
);
//gates and IO assignments:
assign data_o[1] = data_i[1];
assign data_o[0] = (~data_i[1] & data_i[0]);
endmodule
| 7.907297 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module Muxes2in1Array2 (
input [1:0] data_i,
input select_i,
output [1:0] data_o
);
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module PriorityEncoder_14 (
input [13:0] data_i,
output reg [3:0] code_o
);
always @*
case (data_i)
14'b00000000000001: code_o = 4'b0000;
14'b00000000000010: code_o = 4'b0001;
14'b00000000000100: code_o = 4'b0010;
14'b00000000001000: code_o = 4'b0011;
14'b00000000010000: cod... | 6.599169 |
module PriorityEncoder_14v2 (
input [13:0] data_i,
output [ 3:0] code_o
);
wire tmp10, tmp20, tmp30, tmp40;
assign tmp10 = ~(~(data_i[1] | data_i[3]) & ~data_i[5]);
assign tmp20 = ~(~(data_i[7] | data_i[9]) & ~data_i[11]);
assign code_o[0] = tmp10 | tmp20;
assign tmp30 = ~(~(data_i[2] | data_i[3])... | 6.599169 |
module LBarrel (
input [13:0] data_i,
input [13:0] shift_i,
output [ 3:0] data_o
);
//assign data_o[3] = |(data_i[11:0] & shift_i[12:1]);
wire [11:0] tmp1_l; //a,b
wire [ 5:0] tmp2_l; // c
wire [ 2:0] tmp3_l; //d
assign tmp1_l = ~(data_i[11:0] & shift_i[12:1]);
assign tmp2_l = ~(tmp1_l[1... | 6.741724 |
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