code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module L1Barrel (
input [4:0] data_i,
input [3:0] shift_i,
output reg [20:0] data_o
);
always @*
case (shift_i)
4'b0000: data_o = data_i;
4'b0001: data_o = data_i << 1;
4'b0010: data_o = data_i << 2;
4'b0011: data_o = data_i << 3;
4'b0100: data_o = data_i << 4;
4'b0... | 6.641517 |
module RBarell (
input data_i,
input shift_i,
output [1:0] data_o
);
assign data_o[1] = ~shift_i;
assign data_o[0] = shift_i | data_i;
endmodule
| 7.721933 |
module PP_add (
input [ 1:0] sign_factor,
input [16:0] PP_2,
input [14:0] PP_1,
input [27:0] PP_0,
output [31:0] p
);
// generate negative MSBs
wire [2:0] E_MSB;
assign E_MSB[0] = ~PP_0[27];
assign E_MSB[1] = ~PP_1[14];
assign E_MSB[2] = ~PP_2[16];
// Reduction
// First redu... | 6.806805 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
xor x1 (x, a, b);
xor x2 (sm, x, c);
and a1 (y, a, b);
and a2 (z, x, c);
or o1 (cy, y, z);
endmodule
| 7.593245 |
module elo211 (
input [3:0] D,
output reg [7:0] SEG
);
always @(*) begin
case (D)
4'd0: SEG <= 8'b01100001;
4'd1: SEG <= 8'b11100011;
4'd2: SEG <= 8'b00000011;
4'd3: SEG <= 8'b00100101;
4'd4: SEG <= 8'b10011111;
4'd5: SEG <= 8'b00100101;
default: SEG <= 8'b111111... | 7.102455 |
module EloDisplay (
Address,
Data,
ReadRedbus,
WriteRedbus,
Enable,
DisplayClock,
CursorEnable,
DisplayAddr,
DisplayChar,
KBIn,
KBWrite
);
input [15:0] Address;
inout [7:0] Data;
assign Data = ReadRedbus && Enable ? registers[Address] : 8'bZZZZZZZZ;
input ReadRedbus... | 7.322261 |
module EloIOExpander (
Address,
Data,
ReadRedbus,
WriteRedbus,
Enable,
IOPort
);
input [15:0] Address;
inout [7:0] Data;
input Enable;
input ReadRedbus;
input WriteRedbus;
reg [7:0] DataOut;
assign Data = (Enable & ReadRedbus) ? DataOut : 8'bZZZZZZZZ;
inout [15:0] IOPort;
re... | 6.875072 |
module pe_array (
reset,
clk,
pe_reset,
op,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3,
out0,
out1,
out2,
out3
);
input clk;
input reset;
input pe_reset;
input [1:0] op;
input [`DWIDTH-1:0] a0;
input [`DWIDTH-1:0] a1;
input [`DWIDTH-1:0] a2;
input [`D... | 6.732969 |
module processing_element (
reset,
clk,
in_a,
in_b,
op,
out
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
input [1:0] op;
output [`DWIDTH-1:0] out;
wire [`DWIDTH-1:0] out_mul;
wire [`DWIDTH-1:0] out_sum;
wire [`DWIDTH-1:0] out_sub;
assign o... | 6.504296 |
module seq_sub (
a,
b,
out,
reset,
clk
);
input [`DWIDTH-1:0] a;
input [`DWIDTH-1:0] b;
input reset;
input clk;
output [`DWIDTH-1:0] out;
reg [`DWIDTH-1:0] a_flopped;
reg [`DWIDTH-1:0] b_flopped;
wire [`DWIDTH-1:0] sub_out_temp;
reg [`DWIDTH-1:0] sub_out_temp_reg;
always @(... | 7.452798 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet;
// Output por... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module seq_mul (
a,
b,
out,
reset,
clk
);
input [`DWIDTH-1:0] a;
input [`DWIDTH-1:0] b;
input reset;
input clk;
output [`DWIDTH-1:0] out;
reg [`DWIDTH-1:0] a_flopped;
reg [`DWIDTH-1:0] b_flopped;
wire [`DWIDTH-1:0] mul_out_temp;
reg [`DWIDTH-1:0] mul_out_temp_reg;
always @(... | 6.589141 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module output_logic (
clk,
reset,
start_eltwise_op,
done_eltwise_op,
address_mat_c,
c_data_out,
c_addr,
c_data_available,
out0,
out1,
out2,
out3
);
input clk;
input reset;
input start_eltwise_op;
input done_eltwise_op;
input [`AWIDTH-1:0] address_mat_c;
outpu... | 6.831719 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`CU_SIZE*`DWIDTH-1:0] d0;
input [`CU_SIZE*`DWIDTH-1:0] d1;
input [`CU_SIZE-1:0] we0;
input [`CU_SIZE-1:0] we1;
output [`CU_SIZE*`DWIDTH-1:0] q0;
o... | 6.838627 |
module output_logic (
clk,
reset,
start_eltwise_op,
done_eltwise_op,
address_mat_c,
c_data_out,
c_addr,
c_data_available,
out0,
out1,
out2,
out3
);
input clk;
input reset;
input start_eltwise_op;
input done_eltwise_op;
input [`AWIDTH-1:0] address_mat_c;
outpu... | 6.831719 |
module pe_array (
reset,
clk,
pe_reset,
op,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3,
out0,
out1,
out2,
out3
);
input clk;
input reset;
input pe_reset;
input [1:0] op;
input [`DWIDTH-1:0] a0;
input [`DWIDTH-1:0] a1;
input [`DWIDTH-1:0] a2;
input [`D... | 6.732969 |
module processing_element (
reset,
clk,
in_a,
in_b,
op,
out
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
input [1:0] op;
output [`DWIDTH-1:0] out;
wire [`DWIDTH-1:0] out_mul;
wire [`DWIDTH-1:0] out_sum;
wire [`DWIDTH-1:0] out_sub;
assign o... | 6.504296 |
module seq_mul (
a,
b,
out,
reset,
clk
);
input [`DWIDTH-1:0] a;
input [`DWIDTH-1:0] b;
input reset;
input clk;
output [`DWIDTH-1:0] out;
reg [`DWIDTH-1:0] a_flopped;
reg [`DWIDTH-1:0] b_flopped;
wire [`DWIDTH-1:0] mul_out_temp;
reg [`DWIDTH-1:0] mul_out_temp_reg;
always @(... | 6.589141 |
module seq_sub (
a,
b,
out,
reset,
clk
);
input [`DWIDTH-1:0] a;
input [`DWIDTH-1:0] b;
input reset;
input clk;
output [`DWIDTH-1:0] out;
reg [`DWIDTH-1:0] a_flopped;
reg [`DWIDTH-1:0] b_flopped;
wire [`DWIDTH-1:0] sub_out_temp;
reg [`DWIDTH-1:0] sub_out_temp_reg;
always @(... | 7.452798 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module top (
input clk,
output elvds_p,
output elvds_n,
input key_i
);
wire key = key_i ^ `INV_BTN;
reg [24:0] ctr_q;
wire [24:0] ctr_d;
wire i_tick;
// Sequential code (flip-flop)
always @(posedge clk) ctr_q <= ctr_d;
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1... | 7.233807 |
module ema ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameter(s)-----------------------------
parameter IDLE = 4'b000, SUB = 4'b001, MULT = 4'b010, TRUNK = 4'b011, ADD = 4'b100, FIN = 4'b101;
parameter MSB_STATE = 2;
//-------------Input Port(s)----------------------------
input clk;
input... | 6.58241 |
module emac_rx_change (
Reset,
Clk_user,
//original interface
Rx_mac_ra,
Rx_mac_rd,
Rx_mac_data,
Rx_mac_BE,
Rx_mac_pa,
Rx_mac_sop,
Rx_mac_eop,
Rx_mac_err,
//to be modified interface
ff_rx_rdy,
ff_rx_data,
ff_rx_mod,
ff_rx_sop,
ff_rx_eop,
ff_rx_ds... | 6.811311 |
module emaregs ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input cfg_we;
input [MSB_REGS_ADDRESS:0] cfg_addr;
input [MSB:0] cfg_data_in;
input ematop_emaregs_reg_we0;
input ematop_emaregs_reg_we1;
input [MSB:0] ematop_emar... | 6.604015 |
module ematop ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameters---------------------
parameter IDLE = 2'b00, START = 2'b01, FIN = 2'b10;
//-------------Input Ports--------------------
input clk;
input rst_n;
input medtop_ematop_start;
input [MSB:0] medtop_ematop_data;
input cfg_we;
... | 6.776394 |
module emaxi_trans (
input clk,
input rstn,
input wr_access,
input [104-1:0] wr_packet,
input m_axi_awready,
input m_axi_wready,
output wr_wait,
output [104-1:0] m_axi_awid, // write address ID
output [ 31 : 0] m_axi_awaddr, // master interface write address
... | 9.170469 |
module emaxi_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (
.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_E... | 6.878331 |
module embedded_Memory (
input [9:0] SW,
input [0:0] KEY,
output [6:0] HEX0,
HEX2,
HEX4,
HEX5,
output [9:0] LEDR
);
assign LEDR[9:0] = 10'd0; // all LEDs on the board should be off
/*
* KEY[0] is the clock
* SW[3:0] is the dataIn
* HEX2 displays dataIn
* SW[8:4] ... | 7.23615 |
module hex_decoder (
input [3:0] hex_digit,
output reg [6:0] segments
);
always @(*) begin
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segm... | 7.584821 |
module embedding #(
parameter RAW_INPUT_BIT = 1,
parameter RAW_INPUT_SZ = 1,
parameter INPUT_SZ = 2,
parameter HIDDEN_SZ = 64,
parameter OUTPUT_SZ = 1, //NUM_OUTPUT_SYMBOLS = 2,
parameter QN = 6,
parameter QM = 11,
parameter DSP48_PER_R... | 6.798838 |
module EMBOSS (
input clk,
input [7:0] shreshold,
input rst_n,
input i_HSYNC,
input i_VSYNC,
input i_BLANK,
input [7:0] i_Y0,
output reg H_SYNC,
output reg V_SYNC,
output reg BLANK,
output reg [15:0] display_data
);
wire signed [9:0] emboss_value;
reg [7:0] r_Y0;
alway... | 6.712343 |
module EMC08 (
CLOCK,
CLOCK_MEM,
RESET_B,
P0,
P1,
P2,
P3,
P4,
PHT,
EA_B,
SE_B,
TM,
PSEN_B
);
input CLOCK;
input CLOCK_MEM;
input RESET_B;
inout [7:0] P0;
inout [7:0] P1;
inout [7:0] P2;
inout [7:0] P3;
output [7:0] P4;
input PHT;
input EA_B;
inp... | 6.506649 |
module emc_top_ext_ram_tb;
// common reg s
reg top_clock_i;
reg top_clock_mem_i;
reg top_reset_i;
// ports
wire [7:0] top_p0_io;
wire [7:0] top_p1_io;
wire [7:0] top_p2_io;
wire [7:0] top_p3_io;
wire [7:0] top_p4_o;
// PAD control signals
wire [7:0] top_p0_y_i;
reg [7... | 6.738912 |
module emc_top_ext_ram_tb;
// common reg s
reg top_clock_i;
reg top_clock_mem_i;
reg top_reset_i;
// ports
wire [7:0] top_p0_io;
wire [7:0] top_p1_io;
wire [7:0] top_p2_io;
wire [7:0] top_p3_io;
wire [7:0] top_p4_o;
// PAD control signals
wire [7:0] top_p0_y_i;
reg [7... | 6.738912 |
module emc_top_ext_rom_tb;
// common reg s
reg top_clock_i;
reg top_clock_mem_i;
reg top_reset_i;
// ports
wire [7:0] top_p0_io;
wire [7:0] top_p1_io;
wire [7:0] top_p2_io;
wire [7:0] top_p3_io;
wire [7:0] top_p4_o;
// PAD control signals
wire [7:0] top_p0_y_i;
reg [7... | 6.738912 |
module emc_top_tb;
// common reg s
reg top_clock_i;
reg top_clock_mem_i;
reg top_reset_i;
// PAD control signals
reg [7:0] top_p0_y_i;
reg [7:0] top_p1_y_i;
reg [7:0] top_p2_y_i;
reg [7:0] top_p3_y_i;
wire [7:0] top_p0_en_o;
wire [7:0] top_p1_en_o;
wire [7:0] top_p2_e... | 7.242455 |
module emesh2packet #(
parameter AW = 32, // address width
parameter PW = 104
) // packet width
(
//Emesh signal bundle
input write_out,
input [ 1:0] datamode_out,
input [ 4:0] ctrlmode_out,
input [AW-1:0] dstaddr_out,
input [AW-1:0] data_out,
input [AW-1:0] src... | 7.605377 |
module emesh_decode (
//Packet Command
input [15:0] cmd_in,
//Write
output cmd_write,
output cmd_write_stop,
//Read
output cmd_read,
output cmd_atomic_add,
output cmd_atomic_and,
output cmd_atomic_or,
output cmd_atomic_xor,
output cmd_cas,
//Fields
output [3:0] cm... | 7.196226 |
module emesh_if ( /*AUTOARG*/
// Outputs
cmesh_ready_out,
cmesh_access_out,
cmesh_packet_out,
rmesh_ready_out,
rmesh_access_out,
rmesh_packet_out,
xmesh_ready_out,
xmesh_access_out,
xmesh_packet_out,
emesh_ready_out,
emesh_access_out,
emesh_packet_out,
// Inputs
... | 6.812796 |
module emesh_mux (/*AUTOARG*/
// Outputs
ready_out, access_out, packet_out,
// Inputs
access_in, packet_in, ready_in
);
//#####################################################################
//# PARAMETERS
//#####################################################################
parameter ... | 7.250807 |
module emesh_readback ( /*AUTOARG*/
// Outputs
ready_out,
access_out,
packet_out,
// Inputs
nreset,
clk,
access_in,
packet_in,
read_data,
ready_in
);
parameter AW = 32; // address width
parameter PW = 104; // packet width
//clk, reset
input nreset; // asynchro... | 7.191321 |
module emesh_wralign ( /*AUTOARG*/
// Outputs
data_out,
// Inputs
datamode,
data_in
);
input [1:0] datamode;
input [63:0] data_in;
output [63:0] data_out;
wire [3:0] data_size;
assign data_size[0] = (datamode[1:0] == 2'b00); //byte
assign data_size[1] = (datamode[1:0] == 2'b01); //... | 6.690338 |
module emg(emg_out, i_spk_cnt, clk, reset);
// parameter NN = 6; // (log2(neuronCount) - 1)
// output wire signed [17:0] emg_out;
// input wire [NN:0] i_spk_cnt;
// input wire clk, reset;
//
// reg signed [35:0] emg_hp, emg_lp;
// wire [35:0] stimulus, emg_stimulus;
// reg [35:0] spikes_long;
// wire signed [35:0] ... | 6.817504 |
module emif_altera_avalon_onchip_memory2_181_kt6usya (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output [31:0] rea... | 6.591447 |
module emif (
input wire global_reset_n, // global_reset_n.reset_n, Asynchronous reset causes the memory interface to be reset and recalibrated. The global reset signal applies to all memory interfaces placed within an I/O column.
input wire pll_ref_clk, // pll_ref_clk.clk, ... | 7.670099 |
module emif_ddr4_altera_avalon_onchip_memory2_160_upip3ra (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output [31:0] readdata;
... | 6.649436 |
module emif_ddr4_ddr4a_altera_avalon_onchip_memory2_170_yroldmy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output... | 6.623564 |
module emif_ddr4_ddr4b_altera_avalon_onchip_memory2_170_yroldmy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output... | 6.623564 |
module emissor (
CLK,
CLR,
CPU_event,
state,
BUS
);
input CLK, CLR;
// Cinco bits para os eventos da CPU
// 4 3 2 1 0
// sh wh wm rh rm
// sendo:
// - sh: 0 -> no shares; 1 -> other shared block (bit auxiliar)
// - wh: 1 -> write hit
// - wm: 1 -> write miss
// -... | 7.405077 |
module corescore_emitter_uart #(
parameter clk_freq_hz = 0,
parameter baud_rate = 57600
) (
input wire i_clk,
input wire [7:0] i_data,
input wire i_valid,
output reg o_ready,
output wire o_uart_tx
);
localparam START_VALUE = clk_freq_hz / baud_rate;
localp... | 6.975706 |
module to emulate pull down resistors by occasionally pulling outputs low.
// Built for use with alchitry CU and early gen alchitry IO boards which didn't
// have pull down resistors in hardware
`ifndef _ALCHITRY_EMULATE_PULL_DOWN_
`define _ALCHITRY_EMUALTE_PULL_DOWN_
`default_nettype none
module emulate_pull_down #... | 8.707052 |
module emu_output_port_lookup #(
//Master AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter SRC_PORT_POS = 16,
parameter DST_PORT_POS = 24,
// AXI Register... | 7.543014 |
module EM_flipflop (
input wire clk,
input wire [31:0] ALUOutE,
input wire [31:0] WriteDataE,
input wire [ 4:0] WriteRegE,
input wire RegWriteE,
input wire MemtoRegE,
input wire MemWriteE,
output reg [31:0] ALUOutM,
output reg [31:0] WriteDataM,
outpu... | 7.305032 |
module EM_MEM_Register (
input clock,
input wire hit,
input [31:0] branchTarget,
input zeroFlag,
input [31:0] ALUResult,
input [31:0] readData2,
input [4:0] writeReg,
input MemRead,
input MemWrite,
input Branch,
input RegWrite,
input MemToReg,
input jumpSignal,
ou... | 6.764868 |
module: EM_MEM_Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EM_MEM_Register_TEST;
// Inputs
reg clock;
reg hit;
reg [31:0] branchTarget;
reg zeroFlag;
reg [31:0] A... | 6.754489 |
module PSEL ( /* IN */
msub,
Y,
/* OUT */
P_1p,
P_2p,
P_1m,
P_2m
);
input msub; // -X*Y
input [2:0] Y;
output P_1p; // +X enable
output P_2p; // +2X enable
output P_1m; // -X enable
output P_2m; // -2X enable
wire P_1pi, P_2pi, P_1mi, P_2mi;
assign P_1pi = (!Y[2]) ... | 6.701537 |
module PPART ( /* IN */
PX_1p,
PX_2p,
PX_1m,
PX_2m,
/* IN */ PX1p,
PX2p,
PX1m,
PX2m,
/* OUT */ PX
);
input PX_1p, PX_2p, PX_1m, PX_2m;
input [17:0] PX1p;
input [17:0] PX2p;
input [17:0] PX1m;
input [17:0] PX2m;
output [17:0] PX;
assign #`da PX[17:0] = ({18{PX_1p}} ... | 7.230854 |
module EM_pipeline_register #(
parameter NUMBER_CONTROL_SIGNALS = 16
) (
control_sinals_IN,
control_sinals_OUT,
result_IN,
result_OUT,
address_IN,
address_OUT,
reg_dst_num_IN,
reg_dst_num_OUT,
reg_dst_value_IN,
reg_dst_value_OUT,
sp_Reg_IN,
sp_Reg_OUT,
CCR_Reg_IN,... | 6.768535 |
module PSEL ( /* IN */
msub,
Y,
P_1p,
P_2p,
P_1m,
P_2m
);
input msub;
input [2:0] Y;
output P_1p;
output P_2p;
output P_1m;
output P_2m;
wire P_1pi, P_2pi, P_1mi, P_2mi;
assign P_1pi = (!Y[2]) & (Y[1] ^ Y[0]);
assign P_2pi = (!Y[2]) & (Y[1] & Y[0]);
assign P_1mi = Y[2] &... | 6.701537 |
module PPART ( /* IN */
PX_1p,
PX_2p,
PX_1m,
PX_2m,
PX1p,
PX2p,
PX1m,
PX2m,
PX
);
input PX_1p, PX_2p, PX_1m, PX_2m;
input [17:0] PX1p;
input [17:0] PX2p;
input [17:0] PX1m;
input [17:0] PX2m;
output [17:0] PX;
assign #`da PX[17:0] = ({18{PX_1p}} & PX1p[17:0]) |
({18{... | 7.230854 |
module Enable #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (
// Section: operational I/Os
input wire clk,
input wire reset,
output reg finished,
// Section: memory I/Os
output reg [addrBits-1:0] address,
output reg ... | 7.751254 |
module decoder (
select,
adrx,
en
);
output [31:0] select;
input [4:0] adrx;
input en;
wire [4:0] adrx_bar;
// invert input stage
not (adrx_bar[4], adrx[4]);
not (adrx_bar[3], adrx[3]);
not (adrx_bar[2], adrx[2]);
not (adrx_bar[1], adrx[1]);
not (adrx_bar[0], adrx[0]);
// 7-input an... | 7.018254 |
module enabled_mux4 #(
parameter REGBITS = 4
) (
input clk,
reset,
input [REGBITS-1:0] a,
b,
c,
d,
input [1:0] control,
input enable,
output reg [REGBITS-1:0] e
);
mux4 #(32) dataupdate (
a,
b,
c,
d,
control,
e_o
);
always @(*)
if... | 7.975063 |
module enabled_reg #(
parameter WIDTH = 16
) (
input clk,
reset,
enable,
input [WIDTH-1:0] a,
output reg [WIDTH-1:0] b
);
always @(posedge clk)
if (reset) b <= 0;
else if (enable) b <= a;
endmodule
| 7.47006 |
module enable_border_module (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
enable_border
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
output enable_border;
/**************************************************/
parameter h_start = 11'd300;
parameter v_s... | 6.780939 |
module enable_clk_gen (
clk,
out_en
);
// ---------- INCLUDES ----------
`include "verilog_utils.vh"
// ---------- PARAMETERS ----------
parameter CLK_FREQ = 100000000;
parameter EN_FREQ = 1000;
// Advanced configuration (not normally needed)
parameter MAX_ERROR_PERC = 10;
// ---------- LO... | 7.080708 |
module enable_counter #(
parameter WIDTH = 10
) (
input clk,
input rst,
input enable,
output reg [WIDTH-1:0] contador,
output reg valid
);
always @(posedge clk) begin
if (rst) begin
contador <= 'd0;
valid <= 'd0;
end else begin
if (enable) contador <= contador + 'd1... | 7.885092 |
module enable_hold_square_module (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
hold_square,
enable_hold_square
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
input [15:0] hold_square;
output enable_hold_square;
/***************************************... | 6.659335 |
module enable_next_square_module (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
load_next_square,
enable_next_square
);
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
input load_next_square;
output enable_next_square;
/************************************... | 6.952324 |
module Enable_tb ();
// Clock
reg clk;
always #1 clk = clk !== 1'b1;
// Memory
parameter romFile = "zeroes.hex";
localparam addrBits = `ADDRESS_BITS;
localparam dataBits = `DATA_BITS;
reg [addrBits-1:0] address;
reg [dataBits-1:0] dataIn;
wire [dataBits-1:0] dataOut;
reg readW... | 7.031475 |
module enables the interrupt when it is strobed.
// Let the PUC or other hosts set how many interrupts.
//
//////////////////////////////////////////////////////////////////////////////////
module enb_interupt(
input clk,
input reset,
input enb_int_strb,
input [11:0] enb_add... | 7.20882 |
module for 8B10B Encoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Enc8B10B(
input BYTECLK,
input reset,
input bit_control,
input [7:0] in,
... | 7.05964 |
module enc8in (
i_one_hot,
o_bin,
o_active
);
input [7:0] i_one_hot;
output reg [2:0] o_bin;
output reg o_active;
always @* begin
o_bin[0] = i_one_hot[1] | i_one_hot[3] | i_one_hot[5] | i_one_hot[7];
o_bin[1] = i_one_hot[2] | i_one_hot[3] | i_one_hot[6] | i_one_hot[7];
o_bin[2] = i_one... | 7.476042 |
module testbench;
parameter DELAY = 20;
reg [7:0] one_hot;
wire [2:0] bin;
wire active;
enc8in enc_inst (
.i_one_hot(one_hot),
.o_bin(bin),
.o_active(active)
);
initial begin
one_hot = 8'b0;
#DELAY;
one_hot = 8'b1;
repeat (7) begin
#DELAY;
one_ho... | 7.015571 |
module LED_MUX (
clk,
rst,
LED0,
LED1,
LED2,
LED3,
LEDOUT,
LEDSEL
);
reg [1:0] index = 0;
input clk, rst;
input [7:0] LED0, LED1, LED2, LED3;
output reg [3:0] LEDSEL;
output reg [7:0] LEDOUT;
always @(posedge clk) begin
if (rst) index = 0;
else index = index + 1;
en... | 6.952824 |
module sine_wave_gen (
Clk,
a,
b
);
//declare input and output
input Clk;
output a;
output b;
//declare the sine ROM - 30 registers each 8 bit wide.
reg [7:0] sine[0:29];
//Internal signals
integer i;
integer j;
//Initialize the sine rom with samples.
initial begin
i = 0;
... | 6.660409 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.