code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0... | 6.716539 |
module test_base_01;
//-----------------Definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
//------------------parte principal
initial begin
$display("Exemplo0011 - Fernando Silva - 414506");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = 20;
$dis... | 6.932753 |
module circuito (
f,
a,
b,
c,
d
);
output f;
input a, b, c, d;
wire s0, s1, s2, s3, s4, s5;
not NOT1 (s0, d);
and AND1 (s1, a, b, s0);
not NOT2 (s2, a);
and AND2 (s3, s2, c);
not NOT3 (s4, b);
and AND3 (s5, s4, c);
or OR1 (f, s1, s3, s5);
endmodule
| 6.7052 |
module testcircuito;
reg a, b, c, d;
wire f;
circuito CIRC1 (
f,
a,
b,
c,
d
);
initial begin
$display("Exemplo 01 - Bruno Rafael Nicolletti - 380752");
$display("Test Circuito Logico para Funcao com Quine-McCluskey");
$display("\n a b c d = f");
$monitor(" %... | 6.943425 |
module circuito (
f,
a,
b,
c,
d
);
output f;
input a, b, c, d;
wire s0, s1, s2, s3, s4, s5, s6, s7, s8;
not NOT1 (s0, a);
not NOT2 (s1, b);
not NOT3 (s2, c);
not NOT4 (s3, d);
and AND1 (s4, s0, s1, s3);
and AND2 (s5, s0, s2, s3);
and AND3 (s6, s1, s2, s3);
and AND4 (s7, a, s1,... | 6.7052 |
module testcircuito;
reg a, b, c, d;
wire f;
circuito CIRC1 (
f,
a,
b,
c,
d
);
initial begin
$display("Exemplo 02 - Bruno Rafael Nicolletti - 380752");
$display("Test Circuito Logico para Funcao com Quine-McCluskey");
$display("\n a b c d = f");
$monitor(" %... | 6.943425 |
module circuito (
f,
a,
b,
c,
d,
e
);
output f;
input a, b, c, d, e;
wire s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
not NOT1 (s0, a);
not NOT2 (s1, b);
not NOT3 (s2, c);
not NOT4 (s3, d);
not NOT5 (s4, e);
and AND1 (s5, a, s1, s2, d, s4);
and AND2 (s6, a, b, d, e);
... | 6.7052 |
module testcircuito;
reg a, b, c, d, e;
wire f;
circuito CIRC1 (
f,
a,
b,
c,
d,
e
);
initial begin
$display("Exemplo 03 - Bruno Rafael Nicolletti - 380752");
$display("Test Circuito Logico para Funcao com Quine-McCluskey");
$display("\n a b c d e = f");
... | 6.943425 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Fernando dos Santos Silva - 414506 - Version 1.1");
$display("Test number system");
a = 5;
... | 6.932753 |
module f4 (
output [2:0] saida,
input [0:0] entr01,
input [0:0] entr02
);
input [2:0] saida_not;
//---NOT
not NOT1 (saida_not[0], entr01[0]);
//---NOT
not NOT2 (saida_not[1], entr02[0]);
//---AND
and AND1 (saida[0], saida_not[0], entr02[0]);
//---AND
and AND2 (saida[1], entr01[0], saida_... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [0:0] x;
reg [0:0] y;
wire [2:0] z;
f4 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - Fernando dos Santos Silva - 414506");
$display("Test LU's module \n");... | 6.629466 |
module Exercicio1;
reg clk, reset, x;
wire m1;
exercicio01_seq010_mealy M1 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 - Thaise Souto Martins - 395504");
$display("\nTime\tX Seq 010");
// initial values
clk = 1;
reset = 0;
x = 0;
// i... | 6.677777 |
module exercicio02_seq0110_moore (
y,
x,
clk,
reset
);
output y;
input x;
input clk;
input reset;
reg y;
parameter // state identifiers
start = 3'b000, id0 = 3'b110, id01 = 3'b001, id011 = 3'b010, id0110 = 3'b101; // signal found
reg [2:0] E1; // current state variables
reg [2:... | 6.55818 |
module Exercicio2;
reg clk, reset, x;
wire m1;
exercicio02_seq0110_moore M1 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 - Thaise Souto Martins - 395504");
$display("\nTime\tX Seq 0110");
// initial values
clk = 1;
reset = 0;
x = 0;
/... | 6.52006 |
module Exercicio3;
reg clk, reset, x;
wire m1;
exercicio03_seq1010_mealy M3 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 - Thaise Souto Martins - 395504");
$display("\nTime\tX Seq 1010");
// initial values
clk = 1;
reset = 0;
x = 0;
//... | 6.936273 |
module Exercicio04;
reg clk, reset, x;
wire m1;
exercicio04_seq000_111 M5 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 - Thaise Souto Martins - 395504");
$display("\nTime\tX Seq 000|111");
// initial values
clk = 1;
reset = 0;
x = 0;
/... | 6.585786 |
module seq1010_test;
reg clk, reset, x;
wire m1, m2;
seq1010_mealy mealy1 (
m1,
x,
clk,
reset
);
initial begin
$display("\n Marley Ribeiro");
$display(" Time x exer3");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 ... | 6.728479 |
module exerextra4 (
y,
x,
clk,
reset
);
output y;
input x;
input clk;
input reset;
reg y;
parameter start = 3'b000, id1 = 3'b001, id11 = 3'b011, id0 = 3'b110, id00 = 3'b100;
reg [2:0] E1;
reg [2:0] E2;
// next state logic
always @(x or E1) begin
y = `notfound;
case (E1)... | 7.09453 |
module nandgate (
output s,
input p,
input q
);
assign s = ~(p & q);
endmodule
| 7.298658 |
module test_base_01;
// ------------------------- definir dados
reg [5:0] a;
reg [5:0] b;
reg [5:0] c;
reg [5:0] d;
reg [5:0] e;
// ------------------------- parte principal
initial begin
$display("Exemplo0001 - Pedro Henrique Vilar Locatelli - 427453");
$display("Executar as operaes ");
#1a = 2;
#1b = 15;
#... | 6.932753 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 1'b0;
b = 1'... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] e;
// ------------------------- parte principal
initial begin
$display("Exemplo0002 - Pedro Henrique Vilar Locatelli - 427453");
$display("Executar as operaes ");
#1a = 6'b101010;
#1b = 5'b1101... | 6.932753 |
module xnorgate (
output s,
input p,
input q
);
assign s = ~(p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 1'b0;
b =... | 7.028584 |
module test_base_01;
// ------------------------- definir dados
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] d;
reg [15:0] e;
// ------------------------- parte principal
initial begin
$display("Exemplo0003 - Pedro Henrique Vilar Locatelli - 427453");
$display("Executar as operaes ");
#1a = 6'b100111; ... | 6.932753 |
module nandgate (
output s,
input p,
input q
);
assign s = ~(p) | ~(q);
endmodule
| 7.298658 |
module test_base_01;
// ------------------------- definir dados
reg [8:0] a;
reg [7:0] b;
reg [6:0] c;
reg [5:0] d;
reg [8:0] e;
// ------------------------- parte principal
initial begin
$display("Exemplo0004 - Pedro Henrique Vilar Locatelli - 427453");
$display("Executar as operaes ");
#1a = 8'b101010;
#1b ... | 6.932753 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 1'b0;
b = 1'... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exemplo0005 - Pedro Henrique Vilar Locatelli - 427453");
$display("Executar as operaes ");
#1a = 8'b101010 + ~8'b... | 6.932753 |
module xorgate (
output s,
input p,
input q
);
assign s = ~(p) & q | p & ~(q);
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 1'b0;
b = 1'... | 6.716539 |
module comple1 (
output [7:0] s,
input [7:0] r
);
assign s = ~r;
endmodule
| 7.237485 |
module xnorgate (
output s,
input p,
input q
);
assign s = p & q | ~(p) & ~(q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 1'b0;
b =... | 7.028584 |
module comple2 (
output [7:0] s,
input [7:0] r
);
assign s = ~r + 1'b1;
endmodule
| 7.389152 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 1'b0... | 6.553783 |
module andagate (
output s,
input p,
input r
);
assign s = p & r;
endmodule
| 7.312962 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 1'b0... | 6.553783 |
module oragate (
output s,
input p,
input r
);
assign s = p | r;
endmodule
| 6.958234 |
module testandtestgate;
// ------------------------- dados locais
reg [0:7] a; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
andtestgate AND1 (
s,
a
);
// ------------------------- preparacao
initial begin : start
a = 8'b00000000;
... | 7.453235 |
module testortestgate;
// ------------------------- dados locais
reg [0:7] a; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
ortestgate OR1 (
s,
a
);
// ------------------------- preparacao
initial begin : start
a = 8'b00000000;
en... | 7.428848 |
module meia_diferenca (
s0,
s1,
p,
q
);
output s0, s1;
input p, q;
wire temp1;
xor XOR1 (s0, p, q);
not NOT1 (temp1, p);
and AND1 (s1, q, temp1);
endmodule
| 6.723426 |
module diferenca (
s0,
s1,
p,
q,
s
);
output s0, s1;
input p, q, s;
wire temp1, temp2, temp3;
meia_diferenca D1 (
temp1,
temp2,
p,
q
);
meia_diferenca D2 (
s0,
temp3,
temp1,
s
);
xor XOR1 (s1, temp3, temp2);
endmodule
| 6.853547 |
module meia_diferenca (
s0,
s1,
p,
q
);
output s0, s1;
input p, q;
wire temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;
// -- Not
nor NOR1 (temp1, p, p);
// -- And
nor NOR2 (temp2, temp1, temp1);
nor NOR3 (temp3, q, q);
nor NOR4 (s1, temp3, temp2);
// -- Xor
nor NOR5 (te... | 6.723426 |
module meia_diferenca (
v,
d,
p,
q
);
output v, d;
input p, q;
wire temp1, temp2, temp3, temp4, temp5, temp6;
// -- Not
nand NAND1 (temp1, p, p);
// -- And
nand NAND2 (temp2, temp1, q);
nand NAND3 (temp3, temp1, q);
nand NAND4 (v, temp2, temp3);
// -- Xor
nand NAND5 (temp4, p, q... | 6.723426 |
module diferenca (
s0,
s1,
x,
y,
vem_um
);
output s0, s1;
input x, y, vem_um;
wire temp1, temp2, temp3, temp4, temp5, temp6;
meia_diferenca MD1 (
temp2,
temp1,
x,
y
);
meia_diferenca MD2 (
temp3,
s0,
temp1,
vem_um
);
nand NAND1 (temp4,... | 6.853547 |
module testeclock_variacao_up_down;
wire clk;
clock clk1 (clk);
reg p;
wire p1, t1;
pulse pulse1 (
p1,
clk
);
initial begin
p = 1'b0;
end
initial begin
$dumpfile("testeclock_variacao_up_down.vcd");
$dumpvars(1, clk, p1, p);
#120 $finish;
end
endmodule
| 7.089431 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q = d;
qnot = ~q;
end
endmodule
| 7.02102 |
module teste;
wire [3:0] saida;
reg d;
wire clock;
clock clk (clock);
leftRegister LF1 (
saida,
d,
clock
);
initial begin
$display("D CLOCK SAIDA");
d = 1;
$monitor("%1b %1b %4b", d, clock, saida);
#25 d = 0;
#120 $finish;
end
endmodule
| 7.490834 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (s, a, b);
// ------------------------- preparacao
initial begin:start
// atribuicao simultanea
// dos valores iniciais
a=0; b=0;
end
// -... | 6.695863 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q = d;
qnot = ~q;
end
endmodule
| 7.02102 |
module teste;
wire [4:0] saida;
reg d;
wire clock;
clock clk (clock);
rightrotateRegister r1 (
saida,
d,
clock
);
initial begin
d = 1;
$monitor("%1b %1b %5b", d, clock, saida);
#25 d = 0;
#120 $finish;
end
endmodule
| 7.490834 |
module dff (
output q,
input clr,
input clk,
input inp,
input b
);
reg q, qnot;
wire s;
and AND1 (s, inp, b);
always @(posedge clk) begin
if (clr) q <= 0;
else q <= s;
qnot <= ~q;
end
endmodule
| 7.02102 |
module portaNAND (
output x,
input m,
input n
);
// -- x = saida, m e n sao entradas.
assign x = ~(m & n);
//-- dependencias, x depende de m e n. O sinal " ~ " indica negacao.
endmodule
| 9.261431 |
module aux; //-- modulo que ira preparar a funcao para execucao.
reg y, z;
//-- registradores, vao ser meus valores de entrada.
wire x;
//-- conexao(fio), vai ser a saida.
portaNAND executor (
x,
y,
z
);
//-- instancia, ira utilizar o primeiro modulo que foi usado.
initial begin ... | 7.84206 |
module inicio2 (
output x,
input a,
input b,
input c
);
wire aux;
assign aux = a | b;
assign x = aux | c;
endmodule
| 9.13598 |
module inicio (
output x,
input a,
input b
);
assign x = a | b;
endmodule
| 8.400844 |
module final(output w, input j, input k);
assign w = j|k;
endmodule
| 7.06412 |
module variaveis;
reg r, s, t;
wire p, q;
inicio primeiro (
p,
r,
s
);
initial begin : start
r = 0;
s = 0;
end
final segundo(q, p, t);
initial begin : starttwo
t = 0;
end
initial begin
$display("MILLER - 449048");
$display("OR com 3 entradas, utilizando 2 po... | 7.166786 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Miller - 449048");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = 2... | 6.932753 |
module portaNANDmorgan (
output x,
input m,
input n
);
// -- x = saida, m e n sao entradas.
assign x = (~m | ~n);
//-- De Morgan: (a'+b')=(a.b)'
endmodule
| 7.92268 |
module aux; //-- modulo que ira preparar as variaveis para execucao.
reg y, z;
//-- variaveis de entrada.
wire x;
//-- variavel de saida.
portaNANDmorgan executor (
x,
y,
z
);
initial begin : start
y = 0;
z = 0;
end
initial begin
$display("Miller - 449048");
$d... | 7.84206 |
module portaNORtwo (
output x,
input m,
input n
);
// -- x = saida, m e n sao entradas.
assign x = (~m & ~n);
//-- De Morgan: (a'+b')=(a.b)'
endmodule
| 8.896855 |
module executor; //-- modulo que ira preparar as variaveis para execucao.
reg y, z;
//-- variaveis de entrada.
wire x;
//-- variavel de saida (fio).
portaNORtwo executor (
x,
y,
z
);
initial begin : start
y = 0;
z = 0;
end
initial begin
$display("Miller - 449048");... | 8.313457 |
module ANDtriplo (
output u,
input h,
input j,
input o
);
assign u = (h & j & o);
endmodule
| 7.973201 |
module novo;
reg a, b, c;
wire u;
ANDtriplo pendrive (
u,
a,
b,
c
);
initial begin : start
a = 0;
b = 0;
c = 0;
end
initial begin
$display("Miller - 449048");
$display("Porta AND com 3 entradas");
$display(" ");
$monitor(" %b & %b & %b = %b", a, b, c... | 7.191307 |
module inicio (
output x,
input a,
input b
);
assign x = a & b;
endmodule
| 8.400844 |
module final(output w, input j, input k);
assign w = j&k;
endmodule
| 7.06412 |
module variaveis;
reg r, s, t;
wire p, q;
inicio primeiro (
p,
r,
s
);
initial begin : start
r = 0;
s = 0;
end
final segundo(q, p, t);
initial begin : starttwo
t = 0;
end
initial begin
$display("MILLER - 449048");
$display("AND com 3 entradas, utilizando 2 p... | 7.166786 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
orgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [2:0] c;
reg [3:0] d;
reg [4:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0001 - Davidson Francis - 466499");
a = 3 + 14;
b = 3 * 8;
c = 33 / 5;
d =... | 6.932753 |
module notgate2 (
output s,
input p,
input q
);
assign s = (p | q);
endmodule
| 6.699218 |
module notgate3 (
output s,
input p,
input q,
input r
);
wire a;
notgate2 not21 (
a,
p,
q
);
notgate2 not22 (
s,
a,
r
);
endmodule
| 7.093285 |
module testnotgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
notgate3 NOT3 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// at... | 7.480879 |
module test_base_01;
// ------------------------- definir dados
reg [6:0] a;
reg [5:0] b;
reg [3:0] c;
reg [6:0] d;
reg [9:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0002 - Davidson Francis - 466499");
a = 6'b100110 + 5'b11011;
b = 5'b11101 + 'o25;... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [5:0] a;
reg [4:0] b;
reg [4:0] c;
reg [5:0] d;
reg [9:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0003 - Davidson Francis - 466499");
a = ~6'b101010 + 1;
b = ~'o25 + 1;
c = ~27... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
//reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0004 - Davidson Francis - 466499");
a = ~6'b101111 + 1;
//b = ~'321 + 1; nao en... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0005 - Davidson Francis - 466499");
a = 6'b101011 + ~(4'b1001) + 1;
b = 5'b10011 +... | 6.932753 |
module and3Gate (
output s,
input a,
input b,
input c
);
wire z;
assign z = a & b;
assign s = z & c;
endmodule
| 8.298983 |
module exercicio;
reg a, b, c;
wire s;
and3Gate and1 ( s, a, b, c );
// ------ Preparaao
initial begin:start
a=0;
b=0;
c=0;
end
// ------------------------- parte principal
initial begin:main
$display("Exercicioo0008 - Mateus Cunha da Silva - 463624");
$display("Tabela ");
$display("\n a & b = s\n");
$... | 7.052118 |
module and3Gate (
output s,
input a,
input b,
input c
);
wire z;
and and1 (z, a, b);
and and2 (s, c, z);
endmodule
| 8.298983 |
module exercicio;
reg a, b, c;
wire s;
and3Gate and1 ( s, a, b, c );
// ------ Preparaao
initial begin:start
a=0;
b=0;
c=0;
end
// ------------------------- parte principal
initial begin:main
$display("Exercicioo0009 - Mateus Cunha da Silva - 463624");
$display("Tabela ");
$display("\n a & b = s\n");
$... | 7.052118 |
module binario01;
// -- definir tamanho dos registradores
reg [0:4] a;
reg [0:4] b;
reg [0:2] c;
reg [0:3] d;
reg [0:4] e;
// -- parte principal
initial begin : main
$display("Exercicio 001 - Débora Deslandes de Almeida Batista");
$display("Matricula : 451549");
$display("Teste number ")... | 6.80342 |
module or3Gate (
output s,
input a,
input b,
input c
);
wire z;
or or1 (z, a, b);
or or2 (s, c, z);
endmodule
| 8.152343 |
module exercicio;
reg a, b, c;
wire s;
or3Gate or1 ( s, a, b, c );
// ------ Preparaao
initial begin:start
a=0;
b=0;
c=0;
end
// ------------------------- parte principal
initial begin:main
$display("Exercicioo0010 - Mateus Cunha da Silva - 463624");
$display("Tabela ");
$display("\n a | b | c = s\n");
... | 7.052118 |
module test_op;
//----------------definir dados
reg [4:0] a;
reg [4:0] b;
reg [3:0] c;
reg [3:0] d;
reg [3:0] e;
reg aux1, aux2, aux3, aux4;
//---------------- parte principal
initial begin
aux1 = 3;
aux2 = 14;
a = aux1 + aux2;
aux1 = 3;
aux2 = 8;
b = aux1 * aux2;
aux1 = ... | 6.675576 |
module complement;
//---------------------definir dados
reg [5:0] a;
reg [4:0] b;
reg [4:0] c;
reg [5:0] d;
reg [5:0] e;
reg [4:0] e1;
reg [5:0] e2;
reg [5:0] aux;
initial begin
a = 6'b101010;
b = 5'o25;
c = 5'd27;
d = 6'h2C;
e1 = 5'd25;
e2 = 6'd35;
aux = ~e2 +... | 6.901411 |
module complement;
//-----------------definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
initial begin
a = 6'b101111;
b = 7'b0011011;
c = 6'd25;
d = 5'hD;
e = 8'o24;
$display("Exercicio0014 - complemento de 2 - Silvino Henrique Santos de Souza - 412773... | 6.901411 |
module complement;
//-----------------definir dados
reg [7:0] a, b, c, d, e;
reg [7:0] a0, a1, b0, b1, c0, c1, d0, d1, e0, e1;
//--------------parte principal
initial begin
a0 = 8'b00101011;
a1 = 8'b00001001;
a1 = ~a1 + 1'b1;
a = a0 + a1;
b0 = 8'b00010011;
b1 = 8'o15;
b1 = ~b1 +... | 6.901411 |
module test_base_01;
// ------------------------- definir dados
reg [10:0] a;
reg [10:0] b;
reg [10:0] c;
reg [10:0] d;
reg [10:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio0016 - Douglas Cruz de Matos - 433134");
$display("Exercicio 1 system");
//--testando valores positivo... | 6.932753 |
module ex_base_07;
// ------------------------- definir dados
reg [0:7] a = 8'b00001011; //entrada de 1 byte ou 8 bits
// ------------------------- parte principal
initial begin
$display("Exerccio 0017 - Pedro Henrique A. M. de Carvalho - 427452");
$display("Ex number system");
a = ~a + 1; // co... | 7.403764 |
module binario02;
// -- definir bits dos registradores
reg [0:6] a;
reg [0:5] b;
reg [0:3] c;
reg [0:6] d;
reg [0:9] e;
// -- parte principal
initial begin : main
$display("Exercicio 002 - Débora Deslandes de Almeida Batista - 451549");
a = 'b100110 + 'b11011;
b = 'b11101 + 'o25;
c = ... | 6.564965 |
module test_fullAdder;
// ------------------------- definir dados
reg [2:0] x;
reg [2:0] y;
reg carry;
wire [2:0] soma;
// ------------------------- instncia
fullAdder3bits fa1 (
soma,
x,
y,
0
);
// ------------------------- parte principal
initial begin
$display("Exe... | 7.258892 |
module fullSubtrator (
output [2:0] s,
input [1:0] a,
input [1:0] b,
input carryIn
);
wire w[1:0];
wire carryOut[1:0];
xor xor1 (w[0], b[0], carryIn);
xor xor2 (w[1], b[1], carryIn);
fullAdder fa1 (
s[0],
carryOut[0],
a[0],
w[0],
carryIn
);
fullAdder fa2 (
... | 7.006681 |
module funcao (
output s,
input [2:0] x,
input [2:0] y
);
wire [2:0] w;
xnor xnor1 (w[0], x[0], y[0]);
xnor xnor2 (w[1], x[1], y[1]);
xnor xnor3 (w[2], x[2], y[2]);
and and1 (s, w[0], w[1], w[2]);
endmodule
| 6.786886 |
module funcao (
output s,
input [2:0] x,
input [2:0] y
);
wire [2:0] w;
xnor xnor1 (w[0], x[0], y[0]);
xnor xnor2 (w[1], x[1], y[1]);
xnor xnor3 (w[2], x[2], y[2]);
nand nand1 (s, w[0], w[1], w[2]);
endmodule
| 6.786886 |
module F4 (
output [7:0] s,
input [3:0] a,
input [3:0] b
);
or or0 (s[0], a[0], b[0]);
or or1 (s[1], a[1], b[1]);
or or2 (s[2], a[2], b[2]);
or or3 (s[3], a[3], b[3]);
and and0 (s[4], a[0], b[0]);
and and1 (s[5], a[1], b[1]);
and and2 (s[6], a[2], b[2]);
and and3 (s[7], a[3], b[3]);
end... | 7.002384 |
module F4 (
output s,
input a,
input b,
input chave
);
wire s1, s2, s3, s4, c1, c2;
not not0 (c1, chave);
buf buf0 (c2, chave);
or or0 (s1, a, b);
or or1 (s, s3, s4);
and and0 (s2, a, b);
and and1 (s3, s1, c1);
and and2 (s4, s2, c2);
endmodule
| 7.002384 |
module F4 (
output s,
output ss,
input a,
input b,
input chave
);
wire s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, c0, c1;
and and0 (s0, a, b);
or or0 (s1, a, b);
nand nand0 (s2, a, b);
nor nor0 (s3, a, b);
not not0 (c1, chave);
buf buf0 (c0, chave);
and and1 (s4, s0, c1);
and ... | 7.002384 |
module F4 (
output s,
input x,
input y,
input chave0,
input chave1,
input chave2
);
wire s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, c0, c1, c2, c3, c4, c5;
not notx (s0, x);
not noty (s14, y);
or or0 (s1, x, y);
nor nor0 (s2, x, y);
and and0 (s3, x, y);
... | 7.002384 |
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