code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module f33m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`W3:0] v1, v2, v3;
input l1, l2, l3;
output [`W3:0] out;
genvar i;
generate
for (i = 0; i <= `W3; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
endmodule
... | 6.701979 |
module f32m_sub (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_sub
s1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
s2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.641308 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
`define MOST 2*`M+1:2*`M
`define M 97 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define W2 (4*`M-1) // width for a GF(3^{2*M}) element
`define W3 (6*`M-1) ... | 7.39398 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module func1 (
S,
R,
q,
out
);
input [`WIDTH+2:0] S, R;
input [1:0] q;
output [`WIDTH+2:0] out;
wire [`WIDTH+2:0] t;
func4 f (
R,
q,
t
); // t == q*R
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_sub s1 (
S[i+1:i],
... | 7.258845 |
module func2 (
A,
out
);
input [`WIDTH+2:0] A;
output [`WIDTH+2:0] out;
assign out = {A[`WIDTH:0], 2'd0};
endmodule
| 6.95158 |
module func4 (
A,
aa,
C
);
input [`WIDTH+2:0] A;
input [1:0] aa;
output [`WIDTH+2:0] C;
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_mult m (
A[i+1:i],
aa,
C[i+1:i]
);
end
endgenerate
endmodule
| 7.077584 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module func4 (
A,
aa,
C
);
input [`WIDTH+2:0] A;
input [1:0] aa;
output [`WIDTH+2:0] C;
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_mult m (
A[i+1:i],
aa,
C[i+1:i]
);
end
endgenerate
endmodule
| 7.077584 |
module func2 (
A,
out
);
input [`WIDTH+2:0] A;
output [`WIDTH+2:0] out;
assign out = {A[`WIDTH:0], 2'd0};
endmodule
| 6.95158 |
module func1 (
S,
R,
q,
out
);
input [`WIDTH+2:0] S, R;
input [1:0] q;
output [`WIDTH+2:0] out;
wire [`WIDTH+2:0] t;
func4 f (
R,
q,
t
); // t == q*R
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_sub s1 (
S[i+1:i],
... | 7.258845 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f3_ram ( /*autoport*/
//output
f3_rdata,
//input
clk,
f3_wdata,
f3_wr_en,
f3_waddr,
f3_raddr
);
input clk;
//write side
input [95:0] f3_wdata;
input f3_wr_en;
input [7:0] f3_waddr;
//read side
input [7:0] f3_raddr;
output [95:0] f3_rdata;
blk_mem_gen_f3_ram f3... | 7.014306 |
module fourc (
sum,
ca,
ca_out,
a,
b,
c,
d,
ca_in
);
input a, b, c, d, ca_in;
output sum, ca, ca_out;
wire w1;
fa fa_0 (
w1,
ca_out,
a,
b,
c
);
fa fa_1 (
sum,
ca,
w1,
d,
ca_in
);
endmodule
| 7.347031 |
module F4TS16_V (
input input1,
input input2,
input input3,
input input4,
input inputen,
output [7:0] temp1,
output [7:0] temp2,
output [15:0] output1
);
T3TE8_V T3TE8_u (
input1,
input2,
input3,
input4,
temp1
);
T3TE8_V T3TE8_u2 (
input1,
... | 6.665453 |
module f4_ram ( /*autoport*/
//output
f4_rdata,
//input
clk,
f4_wdata,
f4_wr_en,
f4_waddr,
f4_raddr
);
input clk;
//write side
input [255:0] f4_wdata;
input f4_wr_en;
input [6:0] f4_waddr;
//read side
input [6:0] f4_raddr;
output [255:0] f4_rdata;
blk_mem_gen_f4_ra... | 6.711039 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/f51m_comb/f51m_comb.opt (
1_pad, 2_pad, 3_pad, 4_pad, 5_pad, 6_pad, 7_pad, 8_pad,
44_pad, 45_pad, 46_pad, 47_pad, 48_pad, 49_pad, 50_pad, 51_pad );
input 1_pad, 2_pad, 3_pad, 4_pad, 5_pad, 6_pad, 7_pad, 8_pad;
... | 6.939825 |
module fivec (
sum,
ca,
ca_out1,
ca_out2,
a,
b,
c,
d,
e,
ca_in1,
ca_in2
);
input a, b, c, d, e, ca_in1, ca_in2;
output sum, ca, ca_out1, ca_out2;
wire w1, w2;
fa fa_0 (
w1,
ca_out1,
a,
b,
c
);
fa fa_1 (
w2,
ca_out2,
... | 7.142308 |
module F64 (
inA,
Z
);
// Assigning ports as in/out
input [63:0] inA;
output Z;
wire [63:0] A;
alt_invert #(64) m (
inA,
A
);
wire Zn;
func64 m2 (
A,
Zn
);
assign Z = ~Zn;
endmodule
| 8.035227 |
module F8 (
inA,
Z
);
// Assigning ports as in/out
input [7:0] inA;
output Z;
wire [7:0] A;
alt_invert #(8) m (
inA,
A
);
wire Zn;
func8 m2 (
A,
Zn
);
assign Z = ~Zn;
endmodule
| 8.425234 |
module fa (
input A,
input B,
inout S1,
inout Cout1,
inout Cout2,
input Ci,
output S,
output Cout
);
halfadder h1 (
A,
B,
S1,
Cout1
);
halfadder h2 (
Ci,
S1,
S,
Cout2
);
assign Cout = Cout1 | Cout2;
endmodule
| 7.001699 |
module fa (
input a,
input b,
input c,
output co,
output sum
);
assign {co, sum} = a + b + c;
endmodule
| 7.001699 |
module fa1 (
output s,
output co,
input ci,
input a,
input b
);
assign {co, s} = a + b + ci;
endmodule
| 7.13902 |
module fa16 (
input [15:0] a,
input [15:0] b,
input cin,
output gout,
output pout,
output [15:0] s,
output [15:0] cout
);
wire [3:0] p;
wire [3:0] g;
wire [3:0] c;
fa4 u_fa40 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.gout(g[0]),
.pout(p[0]),
.s(s[3:0])... | 6.724251 |
module testbench;
// I/O of the full_adder_1bit module
logic A, B, Cin;
logic Sum, Cout;
logic clock;
logic [1:0] GOLDEN_SUM;
logic correct;
// Declaration for testing integers
integer i, j, k;
// Don't forget to wire in your signals to the module instantiation here!
full_adder_1bit ... | 7.015571 |
module CLA (
a,
b,
c,
s,
co
);
input [1:0] a, b;
input [0:0] c;
output [2:0] s;
output [0:0] co;
wire [0:0] cx0;
Carry c1 (
.a (a[0:0]),
.b (b[0:0]),
.c (c[0:0]),
.s (s[0:0]),
.co(cx0[0:0])
);
Carry c2 (
.a (a[1:1]),
.b (b[1:1]),
.c (cx... | 7.133874 |
module Carry (
a,
b,
c,
s,
co
);
input [0:0] a;
input [0:0] b;
input [0:0] c;
output [0:0] s;
output [0:0] co;
wire [0:0] out1, out2, out3, out4;
assign out1 = a & b;
assign out2 = a ^ b;
assign out3 = out2 & c;
assign co = out3 | out1;
assign out4 = a ^ b;
assign s = out4 ^ ... | 7.09206 |
module FullAdder;
reg [1:0] a;
reg [1:0] b;
reg [0:0] c;
reg [1:0] k;
wire [1:0] enca;
wire [2:0] s;
wire [0:0] co;
Oracle ora (
.a(a),
.k(k),
.enca(enca)
);
CLA cla (
.a (enca),
.b (b),
.c (c),
.s (s),
.co(co)
);
initial begin
k = 'b10;
... | 6.770439 |
module fa4 (
input [3:0] a,
input [3:0] b,
input cin,
output gout,
output pout,
output [3:0] s,
output [3:0] cout
);
wire [3:0] p;
wire [3:0] g;
wire [3:0] c;
assign cout[3] = c[3];
fa u_fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.g(g[0]),
.p(p[0]),
.s... | 6.65011 |
module fa4_f (
I1,
I2,
C,
X
); // full adder structure for the final circuit
input [3:0] I1, I2;
input C;
output [4:0] X;
wire [3:0] Z1;
wire Z2; // calling structures of 4-bit full adder and concatenation buffer
fa4 M1 (
.I1(I1),
.I2(I2),
.C(C),
.S(Z1),
.Cout... | 7.852038 |
module CLA (
a,
b,
c,
s,
co
);
input [7:0] a, b;
input [0:0] c;
output [8:0] s;
output [0:0] co;
wire [0:0] cx0, cx1, cx2, cx3, cx4, cx5, cx6;
Carry c1 (
.a (a[0:0]),
.b (b[0:0]),
.c (c[0:0]),
.s (s[0:0]),
.co(cx0[0:0])
);
Carry c2 (
.a (a[1:1]),
... | 7.133874 |
module Carry (
a,
b,
c,
s,
co
);
input [0:0] a;
input [0:0] b;
input [0:0] c;
output [0:0] s;
output [0:0] co;
wire [0:0] out1, out2, out3, out4;
assign out1 = a & b;
assign out2 = a ^ b;
assign out3 = out2 & c;
assign co = out3 | out1;
assign out4 = a ^ b;
assign s = out4 ^ ... | 7.09206 |
module FullAdder;
reg [7:0] a;
reg [7:0] b;
reg [0:0] c;
reg [7:0] k;
wire [7:0] enca;
wire [8:0] s;
wire [0:0] co;
Oracle ora (
.a(a),
.k(k),
.enca(enca)
);
CLA cla (
.a (enca),
.b (b),
.c (c),
.s (s),
.co(co)
);
initial begin
k = 'b101010... | 6.770439 |
module FA8_tf;
reg [7:0] A, B; //input data reg
reg Ci; //carry in
wire [7:0] S; //sum
wire Co; //carry out
//variable for test
integer i;
//instantiate the design under test
FA8 FA8 (
.A (A),
.B (B),
.Ci(Ci),
.S (S),
.Co(Co)
)... | 6.826386 |
module FAA (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.656773 |
module FAB (
input clk,
input rst_s1,
input stop, //可扩展
input num_in, //一个顺序编号，用于确定在同时进行的两条指令的顺序
input [`PC_BUS] pc, //pc
input [`PC_BUS] npc, //next pc
input [`DECODEOUT_BUS] decode_out, //decode 产生的控制信号具体未定义
input [`DATA_BUS] rfrdata1,
input [`DATA_BUS] rfrdata2,
outp... | 8.183908 |
module FAB_PLREG (
input clk,
input rst,
input stop,
input num_in,
output reg num_out,
input RFWe,
output reg rfwe,
input [`REG_ADDR_BUS] rd,
output reg [`REG_ADDR_BUS] rfwaddr,
input [`DATA_BUS] rfwdata1,
output reg [`DATA_BUS] rfwdata
);
always @(posedge clk) begin
... | 7.472002 |
module Fabonacci_Processor_tb();
localparam PERIOD = 100;
localparam N = 15;
reg [15:0]portIn;
wire [15:0]portOut;
reg clk, reset, int;
wire ack;
reg [15:0] cycles_counter;
Processor processor(clk, reset, portIn, portOut, int, ack);
initial
begin
portIn = 16'h00;
/* Initialize the processor */
clk... | 6.795158 |
module CPU_IO_ConfigMem (
FrameData,
FrameStrobe,
ConfigBits
);
output [19:0] ConfigBits;
input [31:0] FrameData;
input [19:0] FrameStrobe;
LHQD1 Inst_frame0_bit0 (
.D(FrameData[0]),
.E(FrameStrobe[0]),
.Q(ConfigBits[4])
);
LHQD1 Inst_frame0_bit1 (
.D(FrameData[1]),
... | 7.484413 |
module W_IO (
E1BEG,
E2BEG,
E2BEGb,
E6BEG,
W1END,
W2MID,
W2END,
W6END,
A_I_top,
A_T_top,
A_O_top,
UserCLK,
B_I_top,
B_T_top,
B_O_top,
FrameData,
FrameStrobe
);
wire A_I;
output A_I_top;
wire A_O;
input A_O_top;
wire A_Q;
wire A_T;
output ... | 7.848084 |
module W_IO_ConfigMem (
FrameData,
FrameStrobe,
ConfigBits
);
output [11:0] ConfigBits;
input [31:0] FrameData;
input [19:0] FrameStrobe;
LHQD1 Inst_frame0_bit0 (
.D(FrameData[0]),
.E(FrameStrobe[0]),
.Q(ConfigBits[10])
);
LHQD1 Inst_frame0_bit1 (
.D(FrameData[1]),
... | 7.275654 |
module fab_op_fifo (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [11 : 0] din;
input wr_en;
input rd_en;
output [11 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_... | 6.678776 |
module fac #(
parameter CGAINA = 0,
parameter CGAINB = 0,
parameter CGAING = 0
) (
input clk,
input rst_n,
input fs_enb,
input [35:0] csump,
input [35:0] inpba,
input [35:0] inpbb,
input [35:0] outaa,
input [35:0] outab,
output [35:0] xout
);
wire [35:0] gsum;
wire [... | 7.823015 |
module faceDrawer (
clk,
resetn,
enable,
location,
colour_in,
finished,
x_out,
y_out,
colour_out,
write_out
);
input clk, resetn, enable;
input [3:0] location;
input [2:0] colour_in;
output reg finished;
output [7:0] x_out;
output [6:0] y_out;
output [2:0] colour_ou... | 6.953506 |
module FACell (
output Cnext,
Sthis,
input xn,
am,
Cthis
);
wire t1, t2, t3;
xor (t1, am, xn);
and (t2, t1, Cthis);
and (t3, am, xn);
or (Cnext, t2, t3);
xor (Sthis, t1, Cthis);
endmodule
| 7.106661 |
module FACE_DETECTION_DP #(
parameter WIDTH_ADDR = 4'd10,
WIDTH_INTE_ADDR = 5'd16,
WIDTH_POSI = 4'd8,
WIDTH_INTE = 5'd20
) (
input clk,
rst_n,
////// CU
// imager interface
input write_next_frame_dp,
output new_image_ready_dp,
// window selector
input select_window_st... | 6.837447 |
module FACE_DETECTION_ENGINE #(
parameter WIDTH_INTE = 5'd20,
WIDTH_INTE_ADDR = 5'd16,
WIDTH_ADDR = 4'd10,
WIDTH_POSI = 4'd8
) (
input clk,
rst_n,
// imager interface
input new_image_ready,
output write_next_frame,
// Block RAM of integrated image
input [ WIDTH_INTE-... | 6.837447 |
module face_reader #(
parameter WIDTH = 256,
parameter DEPTH = 256,
parameter FILTER_SIZE = 5,
parameter COLOR_DEPTH = 8
) (
image_in_R,
image_in_G,
image_in_B,
enable,
enable_process,
clk,
image_output,
centroid_x,
centroid_y,
done,
finish
);
input [COLOR_D... | 6.744797 |
module dlyRst #(
parameter W_CNTRST = 16
) (
input clk,
input rstn_i,
output reg rstn
);
reg rstn_b2, rstn_b1;
`ifdef SIMULATING
reg [3:0] reset_cnt;
wire reset_cnt_end = (4'hF == reset_cnt);
`else
reg [W_CNTRST-1:0] reset_cnt;
wire reset_cnt_end = ({W_CNTRST{1'b1}} == r... | 8.112767 |
module fact (
input wire clk,
input wire rst,
input wire go,
input wire [3:0] in,
output wire Done,
output wire Error,
output wire [1:0] CS,
output wire [31:0] result
);
wire cnt_lt_2, in_gt_12;
wire [5:0] ctrl_signals;
fact_controlunit CU (
.clk (clk),
.rst (rst),... | 7.53294 |
module factor (
input clk,
input rst_n,
input i_in_valid,
input [11:0] i_n,
output [ 3:0] o_p2,
output [ 2:0] o_p3,
output [ 2:0] o_p5,
output o_out_valid,
output [50:0] number
);
wire [50:0] number0, number1, number2, number3, number4;
wire out_v... | 6.94 |
module factor_of_2 (
input clk,
input rst_n,
input [11:0] i_n,
input i_in_valid_pos,
output [3:0] o_p2,
output o_out_valid,
output [50:0] number
);
wire [50:0] numbers[0:43];
//part1---->set MUXs and DFFs and get o_out_valid
wire [11:0] Q, D;
wire [12:0] D_temp;
wir... | 6.743104 |
module add1bit #(
parameter BW = 2
) (
input [BW-1:0] a,
input b,
output [BW-1:0] result,
output [50:0] number
);
wire [50:0] numbers[0:BW-1];
wire [BW:0] temp;
assign temp[0] = b;
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
HA1 ha0 (
.S(result[i]),
... | 7.155037 |
module adders #(
parameter BW = 2
) (
input [BW-1:0] a,
input [BW-1:0] b,
output [BW-1:0] result,
output [ 50:0] number
);
wire [BW:0] CI_temp;
wire [50:0] numbers [0:BW-1];
assign CI_temp[0] = 1'b0;
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
FA1 fa0 (
... | 7.311842 |
module Detect_Posedge (
input clk,
input rst_n,
input i_in_valid,
output control,
output [50:0] number
);
wire i_valid_pre, pre_bar;
wire [50:0] num1, num2, num3;
assign number = num1 + num2 + num3;
FD2 f0 (
.Q(i_valid_pre),
.D(i_in_valid),
.CLK(clk),
.RESET(rst_n),... | 6.592147 |
module REGP #(
parameter BW = 2
) (
input clk,
input rst_n,
output [BW-1:0] Q,
input [BW-1:0] D,
output [50:0] number
);
wire [50:0] numbers[0:BW-1];
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
FD2 f0 (
Q[i],
D[i],
clk,
rst_n,... | 8.289611 |
module factorialSum (
input clk,
rst,
start,
input [5:0] num,
output reg [1:0] statusLed,
output wire [6:0] disp_unit,
output wire [6:0] disp_tens,
output wire [6:0] disp_hundreth
);
// States of FSM
parameter idle = 0, compute = 1, done = 2;
reg [1:0] current_... | 7.200619 |
module Factorial_Accelerator (
input [1:0] A,
input [3:0] WD,
input WE,
input clk,
rst,
output [31:0] RD
);
wire [3:0] n;
wire [31:0] nf, Result;
wire go_en, n_en;
wire [1:0] RdSel;
wire Go, Done, Err, ResDone, ResErr;
wire GoPulse;
wire GoPulseCmb;
Factorial_Address_Decoder ... | 6.899887 |
module Mux (
input wire [31:0] in1,
in0, //32 bit inputs
input sel, //1 bit sel input
output reg [31:0] Z //32 bit output
);
always @(*) begin
if (sel == 'b0) Z = in0; //sel set to 0, output in0
if (sel == 'b1) Z = in1; //sel set to 1, output in1
end
endmodule
| 8.496048 |
module GT_CMP (
input wire [31:0] A,
B, //32 bit inputs
output reg GT //1 bit output
);
always @(*) begin
GT = A > B; //A > B, result into GT
end
endmodule
| 7.073713 |
module Load_Reg (
input wire [31:0] D,
input wire Load_reg,
input wire CLK,
input wire rst,
output reg [31:0] Q
);
always @(posedge CLK, posedge rst) begin
if (rst) Q <= 0;
else if (Load_reg) Q <= D;
else Q <= Q;
end
endmodule
| 8.605528 |
module MUL (
input wire [31:0] X,
Y, //32 bit input operands
output reg [31:0] Z //32 bit output product
);
always @(*) begin
Z <= X * Y; // multiplies X with Y, puts product in Z
end
endmodule
| 7.233134 |
module Decrementer (
input wire [31:0] D,
input wire Load_count,
input wire EN,
input wire CLK,
output reg [31:0] Q
);
reg [31:0] count;
always @(posedge CLK) begin
if (EN & Load_count) count <= D;
else if (EN)
if (count > 0) count <= count - 1;
else count <= 0;
else coun... | 7.414714 |
module Factorial_CU (
input go,
clk,
input GT_Fact,
GT_Input,
output reg Sel,
Load_Reg,
Load_Cnt,
OE,
En,
output Done,
Err
);
//Next and Current State Registers
reg [2:0] CS = 0, NS;
reg Err_Internal = 0, Done_Internal = 0;
//assign Err = Err_Internal;
assign Err... | 6.74879 |
module Factorial_DP #(
parameter Data_Width = 32
) (
input [3:0] n,
input Clk,
En,
Sel,
Load_Reg,
Load_Cnt,
OE,
output [Data_Width - 1:0] nf,
output GT_Input,
GT_Fact
);
wire [ 3:0] CNT_Out;
wire [Data_Width - 1:0] MUX_Out;
wire [Data_Width - 1:0] REG_Out;
... | 7.696361 |
module connects the an External Bus to Avalon Switch Fabric *
* It acts as both a master for the avalon swtich fabric *
* and a slave to the master peripheral *
* *
*******... | 9.339336 |
module connects the an External Bus to Avalon Switch Fabric *
* It acts as both a master for the avalon swtich fabric *
* and a slave to the master peripheral *
* *
*******... | 9.339336 |
module clk_div (
input clk_in,
output reg clk_div
);
reg [32:0] counter;
always @(posedge clk_in) begin
counter <= counter + 1;
if (counter >= 20000) begin
counter <= 0;
clk_div <= ~clk_div;
end
end
endmodule
| 7.520262 |
module factor (
input clk,
input rst_n,
input i_in_valid,
input [11:0] i_n,
output [ 3:0] o_p2,
output [ 2:0] o_p3,
output [ 2:0] o_p5,
output o_out_valid,
output [50:0] number
);
wire [50:0] number0, number1, number2, number3, number4;
wire out_v... | 6.94 |
module factor_of_2 (
input clk,
input rst_n,
input [11:0] i_n,
input i_in_valid_pos,
output [3:0] o_p2,
output o_out_valid,
output [50:0] number
);
wire [50:0] numbers[0:43];
//part1---->set MUXs and DFFs and get o_out_valid
wire [11:0] Q, D;
wire [12:0] D_temp;
wir... | 6.743104 |
module add1bit #(
parameter BW = 2
) (
input [BW-1:0] a,
input b,
output [BW-1:0] result,
output [50:0] number
);
wire [50:0] numbers[0:BW-1];
wire [BW:0] temp;
assign temp[0] = b;
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
HA1 ha0 (
.S(result[i]),
... | 7.155037 |
module adders #(
parameter BW = 2
) (
input [BW-1:0] a,
input [BW-1:0] b,
output [BW-1:0] result,
output [ 50:0] number
);
wire [BW:0] CI_temp;
wire [50:0] numbers [0:BW-1];
assign CI_temp[0] = 1'b0;
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
FA1 fa0 (
... | 7.311842 |
module Detect_Posedge (
input clk,
input rst_n,
input i_in_valid,
output control,
output [50:0] number
);
wire i_valid_pre, pre_bar;
wire [50:0] num1, num2, num3;
assign number = num1 + num2 + num3;
FD2 f0 (
.Q(i_valid_pre),
.D(i_in_valid),
.CLK(clk),
.RESET(rst_n),... | 6.592147 |
module REGP #(
parameter BW = 2
) (
input clk,
input rst_n,
output [BW-1:0] Q,
input [BW-1:0] D,
output [50:0] number
);
wire [50:0] numbers[0:BW-1];
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
FD2 f0 (
Q[i],
D[i],
clk,
rst_n,... | 8.289611 |
module factura (
clk,
counterp,
dmin,
umin,
dseg,
useg
);
input clk;
input [20:0] counterp;
output reg [3:0] dmin;
output reg [3:0] umin;
output reg [3:0] dseg;
output reg [3:0] useg;
always @(posedge clk) begin
if (counterp >= 'd00 && counterp < 'd600) begin
dmin = '... | 6.694492 |
module fact_ad (
input wire [1:0] A,
input wire WE,
output reg WE1,
WE2,
output wire [1:0] RdSel
);
always @(*) begin
case (A)
2'b00: begin
WE1 <= WE;
WE2 <= 1'b0;
end
2'b01: begin
WE1 <= 1'b0;
WE2 <= WE;
end
2'b10: begin
W... | 6.680139 |
module fact_controlunit (
input wire clk,
input wire rst,
input wire go,
output reg Done,
output reg Error,
output reg [1:0] CS,
/* 5 KHz clock */
// status signals (OUTPUT)
input wire cnt_lt_2,
input wire in_gt_12,
// control signals (INPUT)
output reg [5:0] control_sign... | 7.786595 |
module fact_datapath (
input wire clk,
input wire rst,
input wire [3:0] in,
input wire [5:0] control_signals,
output wire cnt_out,
output wire in_gt_12,
output wire [31:0] result
);
//control signals
wire cnt_ld, cnt_ud, cnt_ce;
wire mux_s0, mux_s1;
wire en_D;
assign en_D = contro... | 7.403483 |
module fact_reg #(
parameter w = 32
) (
input wire Clk,
Rst,
input wire [w-1:0] D,
input wire Load_Reg,
output reg [w-1:0] Q
);
always @(posedge Clk, posedge Rst) begin
if (Rst) Q <= 0;
else if (Load_Reg) Q <= D;
else Q <= Q;
end
endmodule
| 8.552847 |
module fact_res_err_reg (
input Clk,
Rst,
GoPulseCmb,
Err,
output reg ResErr
);
always @(posedge Clk, posedge Rst) begin
if (Rst) ResErr <= 1'b0;
else ResErr <= (~GoPulseCmb) & (Err | ResErr);
end
endmodule
| 6.50219 |
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a ^ b) & cin);
endmodule
| 7.203305 |
module FADDER (
s,
c,
x,
y,
z
);
input x, y, z;
wire d0, d1, d2, d3, d4, d5, d6, d7;
output s, c;
DECODER dec (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
x,
y,
z
);
assign s = d1 | d2 | d4 | d7, c = d3 | d5 | d6 | d7;
endmodule
| 6.577998 |
module FA_dataflow (
Cout,
Sum,
In1,
In2,
Cin
);
input In1, In2, Cin;
output Cout;
output Sum;
assign {Cout, Sum} = In1 + In2 + Cin;
endmodule
| 7.807455 |
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