code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DECODER (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
x,
y,
z
);
input x, y, z;
output d0, d1, d2, d3, d4, d5, d6, d7;
wire x0, y0, z0;
not n1 (x0, x);
not n2 (y0, y);
not n3 (z0, z);
and a0 (d0, x0, y0, z0);
and a1 (d1, x0, y0, z);
and a2 (d2, x0, y, z0);
and ... | 6.800244 |
module FADDER (
s,
c,
x,
y,
z
);
input x, y, z;
wire d0, d1, d2, d3, d4, d5, d6, d7;
output s, c;
DECODER dec (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
x,
y,
z
);
assign s = d1 | d2 | d4 | d7, c = d3 | d5 | d6 | d7;
endmodule
| 6.577998 |
module FADDER8BIT (
s,
c,
x,
y,
z
);
input [7:0] x, y;
input z;
output [7:0] s;
output c;
wire c1, c2, c3, c4, c5, c6, c7;
FADDER f0 (
s[0],
c1,
x[0],
y[0],
z
);
FADDER f1 (
s[1],
c2,
x[1],
y[1],
c1
);
FADDER f2 (
... | 7.085577 |
module fadder_df (
sum,
cout,
cin,
in1,
in2
);
input in1, in2, cin;
output cout, sum;
assign {cout, sum} = cin + in1 + in2;
endmodule
| 6.72647 |
module faddr (
a,
b,
ci,
s,
co
);
input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = a & b | a & ci | b & ci;
endmodule
| 7.01017 |
module testbench_Fadd ();
reg a, b, cin;
wire cout, sum;
integer i = 0;
`define test_fadd(A, B, CIN, COUT, SUM)\
a=A;\
b=B;\
cin=CIN;\
i=i+1;\
#5;\
if(COUT==cout&&SUM==sum)\
$display ("case %d passed!",i);\
else begin\
$display("case %d failed!",i);\
$finish;\
end;\
... | 6.847763 |
module top (
input clk_16mhz,
output led_usr
);
reg [7:0] duty_cycle = 0;
reg count_up = 1;
wire divided_pulse;
// Fade up / down to "heartbeat" LED
always @(posedge clk_16mhz) begin
if (divided_pulse) begin
if (duty_cycle == 1) begin
count_up <= 1;
end else if (duty_cycle =... | 7.233807 |
module pulse (
input CLK,
output reg PULSE
);
reg [9:0] ctr;
always @(posedge CLK) begin
if (ctr < 1000) begin
ctr <= ctr + 1;
PULSE <= ctr > 800;
end else PULSE <= 0;
end
endmodule
| 6.570181 |
module fade_tb ();
reg clk_16mhz;
wire led_usr;
// Clock
initial begin
clk_16mhz = 0;
forever #(31.25) clk_16mhz = ~clk_16mhz; // 16 MHz
end
top inst_top (
.clk_16mhz(clk_16mhz),
.led_usr (led_usr)
);
// Dump wave
initial begin
$dumpfile("fade_tb.lxt");
$dumpvars(... | 6.791701 |
module top (
input clk_in,
output [2:0] rgb // LED outputs. [0]: Blue, [1]: Red, [2]: Green.
);
wire clk = clk_in; // Directly use the 12 MHz oscillator, no fancy PLL config
// ----------------------------------------------------------
// Advanced three channel fading blinky
// -------------------... | 7.233807 |
module top (
input clk_in,
output [2:0] rgb // LED outputs. [0]: Blue, [1]: Red, [2]: Green.
);
wire clk = clk_in; // Directly use the 12 MHz oscillator, no fancy PLL config
// ----------------------------------------------------------
// Fading blinky
// ------------------------------------------... | 7.233807 |
module mulgen_FA (
A,
B,
C,
out,
cout
);
input A, B, C;
output out, cout;
assign {cout, out} = A + B + C;
endmodule
| 6.979023 |
module mulgen_HA (
A,
B,
out,
cout
);
input A, B;
output out, cout;
assign {cout, out} = A + B;
endmodule
| 7.85871 |
module nnXor (
R,
C,
and1,
sig,
val
);
input R;
input C;
input and1;
input sig;
output val;
assign val = ((R & C & and1) ^ sig);
endmodule
| 6.703623 |
module RegDumpProcessor (
PHI0,
n_RES,
RnW,
addr_bus,
data_bus,
regdump_data,
regdump_addr
);
input PHI0; // Core PHI0
input n_RES; // Core #RES
output RnW; // Core R/W
output [15:0] addr_bus; // Core address bus
inout [7:0] data_bus; // Core data bus
input [31:0] regdump_d... | 7.099971 |
module Fake8502 (
input _reset,
input clock,
input r_w_6502,
output r_w_8502,
input [15:0] address_6502,
output [15:0] address_8502,
inout [7:0] data_6502,
inout [7:0] data_8502,
input aec,
inout [6:0] pio
);
wire ce_pio;
wire ce_0000;
wire ce_0001;
reg [6:0] data_pio;
... | 6.685796 |
module fakecpu (
input wire clk_in,
input wire rst_in,
input wire rdy_in,
input wire [ 7:0] mem_din,
output wire [ 7:0] mem_dout,
output wire [31:0] mem_a,
output wire mem_wr,
output wire [31:0] dbgreg_dout
);
reg [31:0] q_pc, d_pc; // fake pc
reg [31:0] q_reg, d_reg; //... | 6.621629 |
module fakedata (
input clk,
input rst,
output reg [31:0] data = 0,
output reg strobe = 0,
output reg last = 0
);
reg [31:0] testdata[0:63];
reg teststrobe[0:63];
reg testlast[0:63];
initial begin
//I really hope this synthesizes correctly!!!!
$readmemh("testdata.mem", testdata);
... | 6.708734 |
module FakeDM (
input [15:0] Address,
input [15:0] WriteData,
input MemRead,
input MemWrite,
input rst,
input clk,
output reg [15:0] ReadData,
output reg AddressSrc //0: Ram1 Address, 1: Ram2 Address
);
reg [15:0] fakeMemPool[0:31];
reg [15:0] content = 16'b0;
integer pos = 0;
... | 6.966126 |
module fake_envelope_generator (
clk,
rst_b,
note_on,
note_off,
a,
b,
c,
d,
x,
y,
z,
out_value,
busy,
done
);
input wire clk, rst_b;
input wire note_on, note_off;
input wire [17:0] a, b, c, d;
input wire [31:0] x, y, z;
output wire [17:0] out_value;
ou... | 6.656064 |
module fakeram45_256x95
(
rd_out,
addr_in,
we_in,
wd_in,
w_mask_in,
clk,
ce_in
);
parameter BITS = 95;
parameter WORD_DEPTH = 256;
parameter ADDR_WIDTH = 8;
parameter corrupt_mem_on_X_p = 1;
output reg [BITS-1:0] rd_out;
input [ADDR_WIDTH-1:0] addr_in;
input ... | 7.188702 |
module fakeram45_512x64
(
rd_out,
addr_in,
we_in,
wd_in,
w_mask_in,
clk,
ce_in
);
parameter BITS = 64;
parameter WORD_DEPTH = 512;
parameter ADDR_WIDTH = 9;
parameter corrupt_mem_on_X_p = 1;
output reg [BITS-1:0] rd_out;
input [ADDR_WIDTH-1:0] addr_in;
input ... | 7.569701 |
module fakeram45_64x15
(
rd_out,
addr_in,
we_in,
wd_in,
w_mask_in,
clk,
ce_in
);
parameter BITS = 15;
parameter WORD_DEPTH = 64;
parameter ADDR_WIDTH = 6;
parameter corrupt_mem_on_X_p = 1;
output reg [BITS-1:0] rd_out;
input [ADDR_WIDTH-1:0] addr_in;
input ... | 7.430071 |
module fakeram45_64x7
(
rd_out,
addr_in,
we_in,
wd_in,
w_mask_in,
clk,
ce_in
);
parameter BITS = 7;
parameter WORD_DEPTH = 64;
parameter ADDR_WIDTH = 6;
parameter corrupt_mem_on_X_p = 1;
output reg [BITS-1:0] rd_out;
input [ADDR_WIDTH-1:0] addr_in;
input ... | 7.430071 |
module fakeram45_64x96
(
rd_out,
addr_in,
we_in,
wd_in,
w_mask_in,
clk,
ce_in
);
parameter BITS = 96;
parameter WORD_DEPTH = 64;
parameter ADDR_WIDTH = 6;
parameter corrupt_mem_on_X_p = 1;
output reg [BITS-1:0] rd_out;
input [ADDR_WIDTH-1:0] addr_in;
input ... | 7.430071 |
module fake_dpram #(
parameter aw = 9,
parameter dw = 8
) (
input clk,
// Port 1
input [aw-1:0] addr1,
input [dw-1:0] din1,
output [dw-1:0] dout1, // 1-cycle latency
input wen1,
input ren1,
// Port 2
input [aw-1:0] addr2,
input [dw-1:0] din2,
output [dw-1:0] dout2, ... | 8.274281 |
module fake_dpram_tb;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("fake_dpram.vcd");
$dumpvars(5, fake_dpram_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 120; cc = cc + 1) begin
clk = 0;
#5;
clk =... | 6.749218 |
module fifo (
output reg [7:0] rdata,
output wire emptyB,
input read,
input [7:0] wdata,
input write,
input reset,
input clk
);
reg [8:0] rdaddr;
reg [8:0] wraddr;
assign emptyB = (rdaddr != wraddr);
// initial begin
// $monitor ($time,,,"write=%b wraddr=%x wdata=%s, rda... | 6.640482 |
module fake_hilbert_tb;
parameter MSB = 0;
wire [MSB:0] re, im;
reg clk = 0, rst = 0, en = 0, stb = 0;
reg [MSB:0] d;
wire valid;
always #5 clk <= ~clk;
initial begin : HILB_TB
$dumpfile("hilb_tb.vcd");
$dumpvars;
#23 rst <= 1;
#20 rst <= 0;
#20 en <= 1;
// Test pha... | 6.863279 |
module fake_netfpga_sram (
input clk,
input reset,
// Write
input [`FLOW_RAM_ADDR_WIDTH-1:0] wr_0_addr,
input wr_0_req,
input [`FLOW_RAM_WORD_WIDTH-1:0] wr_0_data,
output reg ... | 6.705403 |
module fake_nonburstboundary #(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A + $clog2(WIDTH_D / 8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
) (
input clk,
input resetn,
// Slave port... | 8.239546 |
module onepulse_fsm (
I,
O,
clk,
reset
);
input I;
output O;
input clk;
input reset;
wire [2:0] state, next_state;
Nbit_reg #(2, 0) state_reg (
.in (next_state),
.out(state),
.clk(clk),
.we (1'b1),
.gwe(1'b1),
.rst(reset)
);
assign next_state = (sta... | 6.616384 |
module circuit (
input clk,
rst,
input [31:0] dado,
input [4:0] endereco,
input [4:0] contador,
output [31:0] dado_escrita,
output [ 4:0] endereco_escrita,
posicao_atual
);
Reorder_Buffer rb (
clk,
rst,
dado,
endereco,
contador,
dado_escrita,
... | 6.801902 |
module Reorder_Buffer (
input clk,
rst,
input [31:0] dado,
input [4:0] endereco,
input [4:0] contador,
output [31:0] dado_escrita,
output [ 4:0] endereco_escrita,
posicao_atual
);
reg [36:0] PRF[0:4];
reg [4:0] posicao_atual;
always @(posedge clk) begin
if (!rst) begin
... | 6.675385 |
module replayfifo (
output reg [7:0] rdata,
output wire emptyB,
input replay, // reset the read pointer
input erase, // erase the buffer
input read,
input [7:0] wdata,
input write,
input reset,
input ... | 7.446385 |
module FAKE_ROM (
input wire romEnable_i,
input wire [31:0] romAddr_i,
output reg [31:0] romData_o
);
reg [31:0] instructions[0:1023];
always @(*) begin
if (romEnable_i == 1'b0) begin
romData_o <= 32'b0;
end else begin
romData_o <= instructions[romAddr_i[11:2]];
end
end
endm... | 6.879182 |
module for adding fake jitter, and offsets to the input
* signal.
*
* NOTE:
*
* TODO:
*
*/
module fake_signal
#(parameter WIDTH = 24,
parameter MSB = WIDTH-1,
parameter RATIO = 12,
parameter RMAX = RATIO-1,
parameter RZERO = 0,
parameter SHAKE = 1,
parameter NOISY = 1,
parame... | 8.221118 |
module fake_telescope #( // Data-bus and bit-width settings:
parameter WIDTH = 24,
parameter MSB = WIDTH - 1,
// Fake-data generation-modes:
parameter MULTI = 1, // runtime mode setting (0/1)?
parameter RNG = 1, // use random (MFSR) data for testing?
parameter CONST = 0, // use consta... | 7.046861 |
module fallingDetector (
fdSensorValue,
fdFactoryValue,
fallDetected
);
input [7:0] fdSensorValue;
input [7:0] fdFactoryValue;
output fallDetected;
wire lt, gt, eq;
comparator8 cmp (
fdSensorValue,
fdFactoryValue,
1'b0,
1'b1,
1'b0,
lt,
eq,
gt
);
... | 8.280501 |
module falling_edge (
input clk_sys,
input signal,
output falling
);
assign falling = old & ~signal ? 1'b1 : 1'b0;
reg old;
always @(posedge clk_sys) old <= signal;
endmodule
| 7.095571 |
module falling_piece_update_tb;
reg clk, reset;
reg [4:0] falling_piece_i = 5'd5, falling_piece_j = 5'd5;
reg [2:0] falling_piece_type = 3'd4;
reg [1:0] falling_piece_angle = 3'd0;
reg [2:0] op_type = 3'b001;
wire [4:0] pos_i, pos_j;
wire check_done, valid;
wire [2:0] new_piece_type;
wire update_done... | 7.041726 |
module fallthrough_small_async_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, // Data out
output full,
output ... | 7.500042 |
module fallthrough_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [ WIDTH-1:0] d... | 7.500042 |
module fallthrough_small_fifo_tester ();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer ... | 7.500042 |
module fallthrough_small_fifo_old #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter NEARLY_FULL = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, //... | 7.500042 |
module fallthrough_small_fifo_twothresh #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1,
parameter PROG_FULL_THRESHOLD_EARLY = 2 ** MAX_DEPTH_BITS - 1
) (
input [ WIDTH-1:0] din, // Data in
input w... | 7.500042 |
module fallthrough_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, ... | 7.500042 |
module fallthrough_small_fifo_tester ();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer ... | 7.500042 |
module FALL_TEST (
input clk,
input reset,
input signed [15:0] AX_DATA,
input signed [15:0] AY_DATA,
input signed [15:0] AZ_DATA,
//input signed [15:0] GZ_DATA,
output reg [7:0] CT_S,
output reg CT_SS
);
//分频器
reg [19:0] count;
always @(posedge clk, negedge reset)
if (!reset)... | 7.101875 |
module FALU (
input [63:0] op1,
input [63:0] op2,
input [2:0] opcode,
input wid,
output [63:0] out,
input clk,
input rst
);
wire sign1, sign2;
wire [9:0] exp1;
wire [9:0] exp2;
wire exp_sgn1, exp_sgn2;
wire [ 9:0] exp_diff;
wire [52:0] val1;
wire [52:0] val2;
wire [15:0] ops... | 6.61784 |
module Fan(clk,
sensor,
rstn,
CRS_o,
);
input clk, rstn;
input signed [7:0] sensor;
output [3:0] CRS_o;
reg [1:0] state;
reg [3:0] CRS;
assign CRS_o = CRS;
always @(posedge clk or negedge rstn) begin
if (!rstn)begin
... | 8.525311 |
module FancySlave (
resetn,
SCLK,
MOSI,
MISOA,
MISOB,
SS,
Hex0,
Hex1,
Hex2,
Hex3,
Hex4,
Hex5,
Switches,
Keys,
Lights,
Green
);
/*
I/Os
*/
// General I/Os //
input resetn;
input [17:0] Switches;
input [1:0] Keys;
output [6:0] Hex0, Hex1, He... | 7.989086 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
parameter idle=4'd0, s1=4'd1, s11=4'd2, s110=4'd3, b0=4'd4, b1=4'd5, b2=4'd6, b3=4'd7, counts=4'd8, waiti... | 7.203305 |
module fangbo_rom #(
parameter DATA_WIDTH = 12,
parameter ADDR_WIDTH = 12
) (
input [(ADDR_WIDTH-1):0] addr,
input clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the ROM variable
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
// Initialize the ROM with $readmemb. Put the memory contents
... | 7.885366 |
module Fangdou (
input CLK,
input bottom,
output myCLK
);
reg temp3, temp2, temp1;
always @(posedge CLK) begin
temp1 <= bottom;
temp2 <= temp1;
temp3 <= temp2;
end
assign myCLK = temp3 && temp2 && temp1;
endmodule
| 6.596327 |
module box (
(* invertible_pin="INV_A" *)
input wire A,
input wire B,
output wire Y
);
parameter [0:0] INV_A = 1'b0;
endmodule
| 7.681437 |
module top(
input wire [1:0] di,
output wire [5:0] do
);
wire [1:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
box b00 (.A(d[0]), .B( ), .Y(do[0]));
box b01 (.A(d[0]), .B( ), .Y(do[1]));
box b02 (.A( ), .B(d[0]), .Y(do[2]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
box b10 (.A(d[1]... | 6.776298 |
module Pipecomponent (
output Z,
input ZCOMP,
input A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z,
A,
enable
);
assign ACOMP = Z;
endmodule
| 7.182889 |
module Fanout_4_t;
reg in = 1'b0;
wire [3:0] out;
// test instance instantiation
Fanout_4 FO4 (
.in (in),
.out(out)
);
// uncommment and add "+access+r" to your nverilog command to dump fsdb waveform on NTHUCAD
// initial begin
// $fsdbDumpfile("FO4.fsdb");
// $fsdbDumpvars;
... | 6.763216 |
module: FanSpeed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FanSpeed;
// Inputs
reg arst;
reg clk;
reg [7:0] speed;
// Outputs
wire pwm_data;
// Instantiate the Uni... | 8.365707 |
module fantasma_rebotando (
input wire clk, // 25 MHz (a no ser que uses otro ModeLine (ver videosyncs.v)
output wire [7:0] r,
output wire [7:0] g,
output wire [7:0] b,
output wire hsync,
output wire vsync
);
wire [10:0] hc, vc; // posicion actual X,Y de la pantalla
wire display_enable... | 6.72845 |
module fan_out_2 (
in1,
out1,
out2
);
input [1:0] in1;
output [0:0] out1, out2;
assign out1 = !in1;
assign out2 = !in1;
endmodule
| 7.022711 |
module FAN_PWM (
clk, // 50MHz OSC_50_BANK2
PWM_input, // 16 speed levels
clk_div_out, // 8 bit frequency divider
FAN
); // Fan control pin
//=======================================================
// PORT declarations
//=======================================================
input clk; /... | 8.22761 |
module fap (
Cout,
Sum,
p,
A,
B,
Cin
);
input A, B, Cin;
output p, Sum, Cout;
rha ha1 (
g1,
p,
temp1,
A,
B
);
ha ha2 (
g2,
Sum,
temp1,
Cin
);
or o1 (Cout, g1, g2);
endmodule
| 7.036238 |
module fapch_counter (
input wire fclk,
input wire rdat_n,
output reg vg_rclk,
output reg vg_rawr
);
reg [4:0] rdat_sync;
reg rdat_edge1, rdat_edge2;
wire rdat;
wire rwidth_ena;
reg [3:0] rwidth_cnt;
wire rclk_strobe;
reg [5:0] rclk_cnt;
// RCLK/RAWR restore
// currently simplest ... | 7.196308 |
module fare_total (
input wire [15:0] distance_fare_bcd,
input wire [15:0] wait_fare_bcd,
output wire [15:0] fare_total_bcd,
output wire max
);
wire [3:0] a_1;
wire [3:0] a_2;
wire [3:0] a_3;
wire [3:0] a_4;
wire [3:0] b_1;
wire [3:0] b_2;
wire [3:0] b_3;
wire [3:0] b_4;
wire [3:0] a... | 6.669569 |
module fare_total_tb ();
reg [15:0] distance_fare_bcd;
reg [15:0] wait_fare_bcd;
wire [15:0] fare_total_bcd;
wire max;
parameter CYCLE = 5'd20;
initial begin
distance_fare_bcd = 16'b0000_0000_0000_0000;
wait_fare_bcd = 16'b0000_0000_0000_0000;
#(CYCLE * 20);
distance_fare_bcd = 16'b0001... | 7.867706 |
module FarPath #(
parameter size_in_mantissa = 24, //1.M
parameter size_out_mantissa = 24,
parameter size_exponent = 8,
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter size_counter = 5, //log2(size_in_mantissa) + 1 = 5)
parameter double_size_in_mantissa = size_in_m... | 8.08677 |
module farrow #(
parameter IL = 3
) // Input buffer length -1
(
input clk, // System clock
input reset, // Asynchronous reset
input signed [7:0] x_in, // System input
output [3:0] count_o, // Counter FSM
output ... | 7.368788 |
module fasm_dparam ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
clk_i,
rst_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xclk_i,
xrst_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ-ONLY
output [DW-1:... | 9.938538 |
module fasm_dpsram_rbw ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xrst_i,
xclk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word... | 8.822115 |
module fasm_dpsram_wbr ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xrst_i,
xclk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word... | 8.852691 |
module fasm_fifo ( /*AUTOARG*/
// Outputs
dat_o,
rok_o,
wok_o,
// Inputs
dat_i,
rde_i,
wre_i,
clr_i,
rst_i,
ena_i,
clk_i
);
parameter AW = 4; // fifo depth
parameter DW = 32; // fifo width
output [DW-1:0] dat_o;
output rok_o, // empty signal
wok_o; // full... | 7.251147 |
module fasm_sparam ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
clk_i,
rst_i
);
parameter AW = 5; // 32
parameter DW = 2; // x2
// PORT A - READ/WRITE
output [DW-1:0] dat_o;
input [DW-1:0] dat_i;
input [AW-1:0] adr_i;
input wre_i;
input st... | 9.2602 |
module fasm_spsram_rbw ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word width bits
// wishbone port a
output [DW-1:0] dat_o; // DO
input [DW-1:0] d... | 8.089298 |
module fasm_spsram_wbr ( /*AUTOARG*/
// Outputs
dat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word width bits
// wishbone port a
output [DW-1:0] dat_o; // DO
input [DW-1:0] d... | 7.860538 |
module fasm_tparam ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xrst_i,
xclk_i
);
parameter AW = 4;
parameter DW = 6;
// wishbone port a
output [DW-1:0] dat_o; // DO
... | 8.577452 |
module fasm_tpsram_rbw ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xrst_i,
xclk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word... | 8.736846 |
module fasm_tpsram_wbr ( /*AUTOARG*/
// Outputs
dat_o,
xdat_o,
// Inputs
dat_i,
adr_i,
wre_i,
stb_i,
rst_i,
clk_i,
xdat_i,
xadr_i,
xwre_i,
xstb_i,
xrst_i,
xclk_i
);
parameter AW = 8; ///< address space (2^AW) words
parameter DW = 32; ///< data word... | 8.327093 |
module fast2slow (
output o_sgl, //output for slow clk region
output reg o_read, //output for fast clk region
input i_sgl, //enable signal input
input f_clk,
input frst_n,
input s_clk,
input srst_n
);
reg i_sgl_reg1;
reg i_sgl_reg2;
reg i_sgl_reg3;
reg o_read_reg1;
r... | 7.631231 |
module Fast6551 (
input _reset,
input ce,
input clock,
input r_w,
output _acia_ce,
input [1:0] address,
input [7:0] data_in,
output [7:0] data_out,
input [7:0] acia_data_in,
output [7:0] acia_data_out,
input acia_clock_in,
output acia_clock_out
);
wire [1:0] counter;
... | 7.696238 |
module fsm (
input clock,
input _reset,
input [7:0] data,
output reg lock_flag
);
reg [1:0] state;
always @(negedge clock, negedge _reset) begin
if (!_reset) begin
state <= 0;
lock_flag <= 0;
end else begin
case (state)
0: if (data == 8'h55) state <= 1;
1:... | 6.845858 |
module FAST9_Top (
clock,
nReset,
outAddr,
outPixel
);
input clock;
input nReset;
output [14:0] outAddr;
output [7:0] outPixel;
wire isCorner; // 코너 확인
wire [31:0] compare; // DARK, BRIGHT, SIMILAR 값
wire [14:0] refAddr; // 기준점 주소
wire [7:0] refPixel; // 기준점 데이터
wire [127:0] adjPi... | 7.710086 |
module fastata (
input CLK,
input RESET,
input TS,
input RW,
input [31:0] A,
input IDEWAIT,
output [1:0] IDECS,
output IOR,
output IOW,
output TA,
output ACCESS
);
/* Timing Diagram
S0 S1 S2 S3 S4... | 7.175422 |
module fastbits #(
parameter WIDTH = 16,
parameter MSB = WIDTH - 1
) (
input [MSB:0] a_i,
input [MSB:0] b_i,
input [1:0] m_i,
output [MSB:0] b_no,
output z_o
);
wire [WIDTH:0] c;
assign c[0] = 1'b1;
assign z_o = c[WIDTH];
genvar ii;
generate
for (ii = 0; ii < WIDTH; ii = ... | 6.967307 |
module single_bit (
input a_i,
input b_i,
input c_i,
input [1:0] m_i,
output b_no,
output c_o
);
assign b_no = m_i[1] ? (m_i[0] ? ~(a_i ^ b_i) : ~(a_i | b_i)) : // XNOR : NOR
(m_i[0] ? (a_i & b_i) : ~(a_i & b_i)); // AND : NAND
// assign c_o = b_no ? c_i : 1'b0 ;
MUXCY MUXCY (
... | 6.742787 |
module fastbranch_bypass (
outa,
outb,
rega,
regb,
data_readRegA,
data_readRegB,
dx_ir,
xm_ir,
dx_rd,
xm_rd,
mw_rd,
dx_o,
xm_o,
mw_o,
q_dmem0,
ctrl_writeEnable
);
input [31:0] dx_ir, xm_ir, data_readRegA, data_readRegB, dx_o, xm_o, mw_o, q_dmem0;
input... | 8.694668 |
module fastchip (
input clk,
input cyc,
input clk_sys,
input reset,
input sel,
output sel_ack, // 1 when fast chip is used instead of legacy chip
output ready,
input [23:0] addr,
input [15:0] din,
output [15:0] dout,
input lds,
input uds,
input ... | 6.757042 |
module fastcounter_stage_ #(
parameter NBITS = 3
) (
input i_clk,
input i_rst,
input i_dir, // 1 for increment, 0 for decrement
input i_en,
input i_load,
input [NBITS-1:0] i_load_q,
output [NBITS-1:0] o_q,
output o_zero, // 1 when counter is 0 (registered)
output o_ones // 1 w... | 7.537365 |
module fastcounter #(
parameter NBITS = 10,
parameter NBITS_STAGE = 9 // default value good for iCE40
) (
input i_clk,
input i_rst,
//
input [1:0] i_mode,
input i_dir,
input i_en,
input [NBITS-1:0] i_load_q,
input i_load,
//
output o_end,
output o_nend,
output o_... | 6.695856 |
module: fastdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fastdiv_tb;
// Inputs
reg [7:0] xin;
reg [7:0] yin;
reg clk;
reg enbl;
// Outputs
wire [15:0] xyout;
// Ins... | 7.29332 |
module fastfir_dynamictaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wire i_clk, i_r... | 7.597985 |
module fastfir_fixedtaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wire i_clk, i_res... | 7.087396 |
module FASTICA_PROCESSOR (
input go,
input clk,
output wire signed [25:0] Y1,
output wire signed [25:0] Y2,
output wire signed [25:0] Y3,
output wire signed [25:0] Y4
);
wire whitening_busy, fastica_busy;
wire go_whitening, go_ram1, go_fastica;
wire clk_whitening, clk_mem1, clk_fastica;
... | 6.609673 |
module fast_log2 #(
parameter DELAY = 1,
DSP_FP_SIZE = 1
) (
input CLK,
RESET,
valid,
input [DSP_FP_SIZE-1:0] x
, output rdy,
output [DSP_FP_SIZE-1:0] result
);
`include "function.v"
wire [DSP_FP_SIZE-1:0] value, exponent, exponent_d, f1, f2, f3, f4;
wire f1_rdy, f2_rdy, f3_rdy, f4... | 6.756417 |
module FastAdder2 (
input wire cin,
input wire [1:0] a,
input wire [1:0] b,
output wire [1:0] out,
output wire cout
);
wire [1:0] g = a & b;
wire [1:0] p = a ^ b;
assign out = a ^ b ^ {(g[0]) | (p[0] & cin), (cin)};
assign cout = (g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin);
endmodule
| 8.329719 |
module FastAdder4 (
input wire cin,
input wire [3:0] a,
input wire [3:0] b,
output wire [3:0] out,
output wire cout
);
wire [3:0] g = a & b;
wire [3:0] p = a ^ b;
assign out = a ^ b ^ {
(g[2]) | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin),
(g[1]) | (p[1] &... | 7.92285 |
module FastAdder8 (
input wire cin,
input wire [7:0] a,
input wire [7:0] b,
output wire [7:0] out,
output wire cout
);
wire [7:0] g = a & b;
wire [7:0] p = a ^ b;
assign out = a ^ b ^ {
(g[6]) | (p[6] & g[5]) | (p[6] & p[5] & g[4]) | (p[6] & p[5] & p[4] & g[3]) | (p[6] & p[5] & p[4] & ... | 8.253312 |
module FastMultiplier (
input [31:0] a,
input [31:0] b,
input sign,
output [63:0] product
);
wire [33:0] pp0;
wire [33:0] pp1;
wire [33:0] pp2;
wire [33:0] pp3;
wire [33:0] pp4;
wire [33:0] pp5;
wire [33:0] pp6;
wire [33:0] pp7;
wire [33:0] pp8;
wire [33:0] pp9;
wire [33:0] pp10;... | 6.623876 |
module fastram (
input RESET,
input CLK,
input ACCESS,
input [3:0] A,
input [1:0] SIZ,
input AS20,
input RW20,
input DS20,
// cache and burst control
output CBACK,
output CIIN,
input CBREQ,
input STERM,
// ram chip control
output [3:0] RAMCS,
output... | 6.946445 |
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