code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fastspk_sanger (
clkOut,
sysClk
);
input sysClk;
output clkOut;
wire clkOut, sysClk;
wire inv1, inv2, inv3, inv4, inv5, inv6, inv7, inv8, trig;
reg sp1, sp2;
//synthesis attribute keep of inv1 is "true";
//synthesis attribute keep of inv2 is "true";
//synthesis attribute keep of inv3 is ... | 6.962815 |
module pulseToSpike (
spike_out,
trigger_in
);
input trigger_in;
output spike_out;
//
//spike generation
//
wire inv1, inv2;
reg sp1, sp2;
//synthesis attribute keep of inv1 is "true";
//synthesis attribute keep of inv2 is "true";
//synthesis attribute keep of sp1 is "true";
//synthesis a... | 7.065492 |
module fastspk (
spike_out,
reset
) /* synthesis syn_noprune=1 */;
input reset;
output spike_out;
reg t2;
reg t1;
always @(negedge spike_out or posedge reset) begin
if (reset) begin
if (~spike_out) begin
t1 <= ~t2;
end
end else begin
if (~spike_out) t1 <= ~t2;
e... | 6.721196 |
module AXIS_WB_AXIS_WishboneCSR ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_ctl_dat_i, // @[:@6.4]
output [31:0] io_ctl_dat_o, // @[:@6.4]
input io_ctl_cyc_i, // @[:@6.4]
input io_ctl_stb_i, // ... | 6.911172 |
module AXIS_WB_AXIS_TransferSplitter ( // @[:@539.2]
output io_xferIn_done, // @[:@542.4]
input [31:0] io_xferIn_length, // @[:@542.4]
input io_xferIn_valid, // @[:@542.4]
input io_xferOut_done, // @[:@542.4]
output [31:0] io_xferOut_length, // @[:@542.4]
ou... | 6.911172 |
module AXIS_WB_AXIS_ClearCSR ( // @[:@697.2]
input clock, // @[:@698.4]
input reset, // @[:@699.4]
input [31:0] io_csr_dataOut, // @[:@700.4]
input io_csr_dataWrite, // @[:@700.4]
output [31:0] io_csr_dataIn, // @[:@700.4]
output [31:0] i... | 6.911172 |
module AXIS_WB_AXIS_StatusCSR ( // @[:@714.2]
input clock, // @[:@715.4]
output [31:0] io_csr_dataIn, // @[:@717.4]
input [31:0] io_value // @[:@717.4]
);
reg [31:0] reg$; // @[StatusCSR.scala 26:20:@719.4]
reg [31:0] _RAND_0;
assign io_csr_dataIn = reg$; // @[StatusCSR.sc... | 6.911172 |
module AXIS_WB_AXIS_SimpleCSR ( // @[:@723.2]
input clock, // @[:@724.4]
input reset, // @[:@725.4]
input [31:0] io_csr_dataOut, // @[:@726.4]
input io_csr_dataWrite, // @[:@726.4]
output [31:0] io_csr_dataIn, // @[:@726.4]
output [31:0] ... | 6.911172 |
module AXIS_WB_AXIS_SetCSR ( // @[:@735.2]
input clock, // @[:@736.4]
input reset, // @[:@737.4]
input [31:0] io_csr_dataOut, // @[:@738.4]
input io_csr_dataWrite, // @[:@738.4]
output [31:0] io_csr_dataIn, // @[:@738.4]
output [31:0] io_... | 6.911172 |
module AXIS_WB_WB_WishboneCSR ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_ctl_dat_i, // @[:@6.4]
output [31:0] io_ctl_dat_o, // @[:@6.4]
input io_ctl_cyc_i, // @[:@6.4]
input io_ctl_stb_i, // @[... | 7.38061 |
module AXIS_WB_WB_ClearCSR ( // @[:@699.2]
input clock, // @[:@700.4]
input reset, // @[:@701.4]
input [31:0] io_csr_dataOut, // @[:@702.4]
input io_csr_dataWrite, // @[:@702.4]
output [31:0] io_csr_dataIn, // @[:@702.4]
output [31:0] io_... | 6.685573 |
module AXIS_WB_WB_SimpleCSR ( // @[:@725.2]
input clock, // @[:@726.4]
input reset, // @[:@727.4]
input [31:0] io_csr_dataOut, // @[:@728.4]
input io_csr_dataWrite, // @[:@728.4]
output [31:0] io_csr_dataIn, // @[:@728.4]
output [31:0] io... | 6.618859 |
module AXIS_WB_WB_SetCSR ( // @[:@737.2]
input clock, // @[:@738.4]
input reset, // @[:@739.4]
input [31:0] io_csr_dataOut, // @[:@740.4]
input io_csr_dataWrite, // @[:@740.4]
output [31:0] io_csr_dataIn, // @[:@740.4]
output [31:0] io_va... | 6.978655 |
module WB_WB_AXIS_WishboneCSR ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_ctl_dat_i, // @[:@6.4]
output [31:0] io_ctl_dat_o, // @[:@6.4]
input io_ctl_cyc_i, // @[:@6.4]
input io_ctl_stb_i, // @[... | 7.458124 |
module WB_WB_AXIS_TransferSplitter ( // @[:@556.2]
output io_xferIn_done, // @[:@559.4]
input [31:0] io_xferIn_address, // @[:@559.4]
input [31:0] io_xferIn_length, // @[:@559.4]
input io_xferIn_valid, // @[:@559.4]
input io_xferOut_done, // @[:@559.4]
... | 6.733942 |
module WB_WB_AXIS_ClearCSR ( // @[:@714.2]
input clock, // @[:@715.4]
input reset, // @[:@716.4]
input [31:0] io_csr_dataOut, // @[:@717.4]
input io_csr_dataWrite, // @[:@717.4]
output [31:0] io_csr_dataIn, // @[:@717.4]
output [31:0] io_... | 6.708612 |
module WB_WB_AXIS_StatusCSR ( // @[:@731.2]
input clock, // @[:@732.4]
output [31:0] io_csr_dataIn, // @[:@734.4]
input [31:0] io_value // @[:@734.4]
);
reg [31:0] reg$; // @[StatusCSR.scala 26:20:@736.4]
reg [31:0] _RAND_0;
assign io_csr_dataIn = reg$; // @[StatusCSR.scal... | 6.670404 |
module WB_WB_AXIS_SimpleCSR ( // @[:@740.2]
input clock, // @[:@741.4]
input reset, // @[:@742.4]
input [31:0] io_csr_dataOut, // @[:@743.4]
input io_csr_dataWrite, // @[:@743.4]
output [31:0] io_csr_dataIn, // @[:@743.4]
output [31:0] io... | 6.754351 |
module WB_WB_AXIS_SetCSR ( // @[:@752.2]
input clock, // @[:@753.4]
input reset, // @[:@754.4]
input [31:0] io_csr_dataOut, // @[:@755.4]
input io_csr_dataWrite, // @[:@755.4]
output [31:0] io_csr_dataIn, // @[:@755.4]
output [31:0] io_va... | 7.167661 |
module Fast_median_filter (
input wire [7:0] din,
input wire data_valuable,
input sclk,
input s_rst_n,
input vsync,
output wire [7:0] median,
output wire dout_flag
);
wire [7:0] Data00, Data01, Data02, Data10, Data11, Data12, Data20, Data21, Data... | 6.734808 |
module AntiLog2 (
input [9:0] DIN,
input clk,
output reg [23:0] DOUT
);
// Comprises 2 main blocks: barrel shifter & LUT
reg [ 3:0] barrelshfcnt;
reg [22:0] LUTout;
wire [38:0] tmp1 = ({1'b1, LUTout} << barrelshfcnt);
always @(posedge clk) begin
barrelshfcnt <= DIN[9:6];
DOUT <= tm... | 6.943877 |
module dual_ported_bram (
clka,
clkb,
ena,
enb,
wea,
web,
addra,
addrb,
dia,
dib,
doa,
dob
);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 9;
parameter DEPTH = 1 << ADDR_WIDTH;
input clka, clkb, ena, enb, wea, web;
input [ADDR_WIDTH-1:0] addra, addrb;
i... | 6.564995 |
module BRAM (
CLK,
RST_N,
RD_ADDRA,
RD_ADDRB,
REA,
REB,
WR_ADDRA,
WR_ADDRB,
WEA,
WEB,
DIA,
DIB,
DOA,
DOB,
INIT
);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 9;
parameter DEPTH = 1 << ADDR_WIDTH;
input CLK, RST_N;
input REA, REB;
input WEA,... | 6.8698 |
module fast_counter (
aclr,
clock,
cnt_en,
q
);
input aclr;
input clock;
input cnt_en;
output [2:0] q;
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
lpm_counter LPM_COUNTER_component (
.aclr(aclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aloa... | 6.827576 |
module is a basic register used for individual GPIO_IN# and GPIO_OUT# in the diagram, each holding 32 bits
module gpio_reg
#(parameter integer WIDTH = 32)
(
input rstn,
input clk,
input en,
input [WIDTH-1:0] datain,
output reg [WIDTH-1:0] dataout
);
always @(posedge clk)
if(!rstn) begin... | 8.35416 |
module sets the enables for each individual gpio register for out and enables the counter
module w_addr_decoder
#(
parameter integer WIDTH = 32
)
(
input sel,
input w_en,
input [WIDTH-1:0] addr,
output reg wren0,
output reg wren1,
output reg wren2,
output reg wren3,
output reg wren4... | 7.140662 |
module sets the enables for each individual gpio register for in
module r_addr_decoder
#(
parameter integer WIDTH = 32
)
(
input sel,
input rw_en,
input [WIDTH-1:0] addr,
output reg rden0,
output reg rden1,
output reg rden2,
output reg rden3
);
always @(*)
begin
rden0 <... | 7.140662 |
module wcount_addr_decoder #(
parameter integer WIDTH = 32
) (
input [2:0] outSel,
output reg rdwren0,
output reg rdwren1,
output reg rdwren2,
output reg rdwren3
);
always @(*) begin
rdwren0 <= (outSel == 1) ? 1'b1 : 1'b0;
rdwren1 <= (outSel == 2) ? 1'b1 : 1'b0;
rdwren2 <= (outSel... | 7.09671 |
module takes 4 gpio registers and groups them so the counter can easily select which one is in use
// This module needs to be able to change the number of gpio registers from 4 to whatever the desired number is through a variable
module gpio_out_mux
#(
parameter integer N = 4,
parameter integer WIDTH = 32
)
(
... | 7.094315 |
module gpio_en #(
parameter integer WIDTH = 32
) (
input rstn,
input clk,
input wren5,
input [WIDTH-1:0] endata,
output reg [WIDTH-1:0] pinout
);
always @(posedge clk)
if (!rstn) begin
pinout <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end else begin
pinout <= wren5 ? endata ... | 7.43972 |
module takes 4 gpio registers and groups them so the counter can easily select which one is in use
// This module needs to be able to change the number of gpio registers from 4 to whatever the desired number is through a variable
module gpio_in_mux
#(
parameter integer N = 4,
parameter integer WIDTH = 32
)
(
... | 7.094315 |
module Log2flowthru
/*
A fast base-2 logarithm function, 24 bits (21 used) in, 8 bits out.
Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
(more info at the web site - see "Extras")
Executes every cycle, with a latency of 1 - slower throughput than pipelined
version, but faster result.
This version h... | 8.153191 |
module Log2highacc
/*
A fast base-2 logarithm function, 24 bits (22 used) in, 12 bits out.
Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
(more info at the web site - see "Extras")
Executes every cycle, with a latency of 3.
Compared to previous versions, this one has a larger, higher resolution
look... | 8.057399 |
module Log2pipelined
/*
A fast base-2 logarithm function, 24 bits (21 used) in, 8 bits out.
Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
(more info at the web site - see "Extras")
Executes every cycle, with a latency of 3.
This version has a smallish lookup table, hence, a slightly uneven output.
... | 7.701299 |
module
//*************************************************************
// Revision List
//*************************************************************
// rn1:
// date: 2020/06/21
// modifier:
// description:
/////////////////////////////////////////////////////////////////
modu... | 8.366981 |
module jtframe_pll0 (
input inclk0,
output reg c0, // 96
output reg c1, // 48
output c2, // 48 (shifted by -2.5ns)
output reg c3, // 24
output reg c4, // 6
output reg locked
);
initial begin
locked = 0;
#30 locked = 1;
end
reg nc;
`ifdef BAS... | 7.044764 |
module jtframe_pll1 (
input inclk0,
output reg c0 // 25
);
initial begin
c0 = 1'b0;
forever c0 = #20 ~c0;
end
endmodule
| 6.688123 |
module jtframe_pll6293 (
input inclk0,
output reg c0, // 50.3
output c1, // 50.3
output c2, // 50.3 (shifted by -2.5ns)
output reg c3, // 25.17
output reg c4, // 6.29
output reg locked
);
initial begin
locked = 0;
#30 locked = 1;
end
assi... | 6.67367 |
module jtframe_pll6144 (
input inclk0,
output reg c0, // 49.152
output c1, // 49.152
output c2, // 49.152 (shifted by -2.5ns)
output reg c3, // 24.576
output reg c4, // 6.144
output reg locked
);
initial begin
locked = 0;
#30 locked = 1;
end... | 7.023474 |
module fast_square_bb (
input clock,
input reset,
input freq_step,
input record,
output data_out_strobe,
input wire signed [15:0] i_in,
input wire signed [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
reg [15:0] i_sr_out;
reg [15:0] q_sr_out;
//IIR FILTER
... | 7.081684 |
module fast_square_bb_comb (
input clock,
input ext_reset,
input reset,
input freq_step,
input record,
output data_out_strobe,
input wire signed [15:0] i_in,
input wire signed [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output reg [2:0] mod_counter
);
... | 7.081684 |
module fast_square_controller (
input clock,
input reset,
input pll_locked,
output reg rx_record,
output reg rx_reset,
output reg rx_next,
output reg freq_step_out,
output [3:0] debug
);
parameter NUM_FREQ_STEPS = 32;
parameter RECORD_TICKS = 15000;
reg [3:0] state, next_state;
... | 7.002539 |
module FAST_t_opr_16_7_0_1080_1920_s_core_buf_val_0_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 9;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1927;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
inp... | 6.889751 |
module FAST_t_opr_16_7_0_1080_1920_s_core_buf_val_0_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd9;
parameter AddressRange = 32'd1927;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 6.889751 |
module FAST_t_opr_16_7_0_1080_1920_s_k_buf_val_0_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1920;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce... | 6.889751 |
module FAST_t_opr_16_7_0_1080_1920_s_k_buf_val_0 (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1920;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 6.889751 |
module fas_pipline2 (
input clk,
input rst,
//s1, significand32
input [32:0] x1,
input [32:0] y1,
input [ 8:0] base_ei,
input enable,
//s1, significand32
output [32:0] x2,
output [ 8:0] base_eo,
output valid
);
//////////////////////////////////////////////... | 6.65684 |
module fas_pipline3 (
input clk,
input rst,
//s1, significand32
input [32:0] x2,
input [ 8:0] base_ei,
input enable,
//s1, significand32
output [32:0] x3,
output [ 8:0] base_eo,
output valid
);
////////////////////////////////////////////////////////////
wire... | 6.821161 |
module CHIP (
val,
dat,
clk,
rst,
done,
freq
);
input clk, rst;
input val;
input [15:0] dat;
output done;
output [3:0] freq;
wire clk_i, rst_i, val_i;
wire [15:0] dat_i;
wire done_i;
wire [3:0] freq_i;
FAS fas (
.data_valid(val_i),
.data(dat_i),
.clk(clk... | 6.56214 |
module fat16in (
in16,
a8,
b4,
c2,
d1,
e1
);
input [15:0] in16;
output [7:0] a8;
output [3:0] b4;
output [1:0] c2;
output d1;
output e1;
wire [3:0] w;
nand_nor ENC16in_1 (
.in (in16[15:12]),
.aout(a8[7:6]),
.bout(b4[3]),
.cout(w[3])
);
nand_nor E... | 7.024995 |
module fat64in (
i64,
a32,
b16,
c8,
d4,
e2,
f1
);
input [63:0] i64;
output [31:0] a32;
output [15:0] b16;
output [7:0] c8;
output [3:0] d4;
output [1:0] e2;
output f1;
wire [1:0] w;
fat16in ENC64in_1 (
.in16(i64[63:48]),
.a8 (a32[31:24]),
.b4 (b16[15:12... | 6.721274 |
module: fa
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fatest;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire cout;
// Instantiate the Unit Under Test (UUT... | 6.898322 |
module fattree_nca_random_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current ro... | 6.580586 |
module fattree_nca_destp_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current rou... | 6.677905 |
module fattree_nca_straight_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current ... | 6.539023 |
module fattree_destport_up_select #(
parameter K = 3,
parameter SW_LOC = 0
) (
destport_in,
destport_o
);
input [K : 0] destport_in;
output [K : 0] destport_o;
localparam [K-1 : 0] SW_LOC_ONHOT = 1 << SW_LOC;
wire going_up = destport_in[K];
assign destport_o = (going_up) ? {1'b1, SW_LOC_ON... | 7.679564 |
module fattree_conventional_routing #(
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
cur... | 6.802268 |
module fattree_look_ahead_routing #(
parameter ROUTE_NAME = "NCA_RND_UP",
parameter P = 4,
parameter L = 2,
parameter K = 2
) (
reset,
clk,
destport_encoded, // current router destination port
dest_addr_encoded,
neighbors_rx,
neighbors_ry,
lkdestport_encoded // look ahead... | 6.543511 |
module fattree_deterministic_look_ahead_routing #(
parameter P = 4,
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
destport_encoded, // current router ... | 7.327345 |
module fattree_destport_decoder #(
parameter K = 2
) (
destport_decoded_o,
destport_encoded_i
);
input [K:0] destport_encoded_i;
output [2*K-1 : 0] destport_decoded_o;
assign destport_decoded_o = (destport_encoded_i[K])? /*go up*/ {destport_encoded_i[K-1:0],{K{1'b0}}}:
/*go down*/{{K{1'b... | 7.679564 |
module fattree_ssa_check_destport #(
parameter DSTPw = 5,
parameter SS_PORT = 0
) (
destport_encoded, //exsited packet dest port
destport_in_encoded, // incomming packet dest port
ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
ss_port_nonhdr_flit // asserted if ... | 6.95895 |
module fattree_destp_generator #(
parameter K = 2,
parameter P = 2 * K,
parameter SW_LOC = 0,
parameter DSTPw = 4
) (
dest_port_in_encoded,
dest_port_out
);
localparam P_1 = P - 1;
input [DSTPw-1:0] dest_port_in_encoded;
output [P_1-1 : 0] dest_port_out;
wire [2*K-1 : 0] destport_deco... | 7.679564 |
module fattree_nca_random_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current ro... | 6.580586 |
module fattree_nca_destp_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current rou... | 6.677905 |
module fattree_nca_straight_up_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
current_level, //connected to current ... | 6.539023 |
module fattree_destport_up_select #(
parameter K = 3,
parameter SW_LOC = 0
) (
destport_in,
destport_o
);
input [K : 0] destport_in;
output [K : 0] destport_o;
localparam [K-1 : 0] SW_LOC_ONHOT = 1 << SW_LOC;
wire going_up = destport_in[K];
assign destport_o = (going_up) ? {1'b1, SW_LOC_ON... | 7.679564 |
module fattree_conventional_routing #(
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
current_addr_encoded, // connected to current router x address
cur... | 6.802268 |
module fattree_look_ahead_routing #(
parameter ROUTE_NAME = "NCA_RND_UP",
parameter P = 4,
parameter L = 2,
parameter K = 2
) (
reset,
clk,
destport_encoded, // current router destination port
dest_addr_encoded,
neighbors_rx,
neighbors_ry,
lkdestport_encoded // look ahead... | 6.543511 |
module fattree_deterministic_look_ahead_routing #(
parameter P = 4,
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
reset,
clk,
destport_encoded, // current router ... | 7.327345 |
module fattree_destport_decoder #(
parameter K = 2
) (
destport_decoded_o,
destport_encoded_i
);
input [K:0] destport_encoded_i;
output [2*K-1 : 0] destport_decoded_o;
assign destport_decoded_o = (destport_encoded_i[K])? /*go up*/ {destport_encoded_i[K-1:0],{K{1'b0}}}:
/*go down*/{{K{1'b... | 7.679564 |
module fattree_addr_encoder #(
parameter K = 2,
parameter L = 2
) (
id,
code
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
function integer... | 6.73616 |
module fattree_addr_decoder #(
parameter K = 2,
parameter L = 2
) (
id,
code
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
function integer... | 6.73616 |
module fattree_ssa_check_destport #(
parameter DSTPw = 5,
parameter SS_PORT = 0
) (
destport_encoded, //exsited packet dest port
destport_in_encoded, // incomming packet dest port
ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
ss_port_nonhdr_flit // asserted if ... | 6.95895 |
module fattree_destp_generator #(
parameter K = 2,
parameter P = 2 * K,
parameter SW_LOC = 0,
parameter DSTPw = 4,
parameter SELF_LOOP_EN = "NO"
) (
dest_port_in_encoded,
dest_port_out
);
localparam P_1 = (SELF_LOOP_EN == "NO") ? P - 1 : P;
input [DSTPw-1:0] dest_port_in_encoded;
outp... | 7.679564 |
module fat_4to1 (
d4,
eout3
);
input [3:0] d4;
output eout3;
wire w1;
wire w2;
nor (w1, d4[3], d4[2]);
nor (w2, d4[1], d4[0]);
nand (eout3, w1, w2);
endmodule
| 7.024104 |
module fat_8to1 (
c8,
eout2
);
input [7:0] c8;
output eout2;
wire w1, w2;
nand_nor_2 fat_8to1_1 (
.in (c8[7:4]),
.out(w1)
);
nand_nor_2 fat_8to1_2 (
.in (c8[3:0]),
.out(w2)
);
nand (eout2, w1, w2);
endmodule
| 7.399315 |
module fat_tree (
in,
eout
);
input [63:0] in;
output [5:0] eout;
wire [31:0] a32;
wire [15:0] b16;
wire [ 7:0] c8;
wire [ 3:0] d4;
wire [ 1:0] e2;
fat64in fat_64in (
.i64(in[63:0]),
.a32(a32[31:0]),
.b16(b16[15:0]),
.c8 (c8[7:0]),
.d4 (d4[3:0]),
.e2 (e2[1:0... | 6.720367 |
module fau2hadf (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
haudf HA1 (
w1,
w2,
a,
b
);
haudf HA2 (
sum,
w3,
w1,
c_in
);
or O (c_out, w2, w3);
endmodule
| 8.157038 |
module signalHolder ( // @[:@88.2]
input clock, // @[:@89.4]
input io_rst, // @[:@91.4]
output io_o, // @[:@91.4]
input io_i // @[:@91.4]
);
reg [6:0] value; // @[Counter.scala 17:33:@93.4]
reg [31:0] _RAND_0;
reg _T_9; // @[FaultDetector.scala 104:23:@94.4]
reg [31:0] _RAND_1;
wire _T_... | 6.553027 |
module faultfsm2 (
input wire clock,
input wire reset,
input wire rec_lt96,
input wire rec_ge96,
input wire rec_ge128,
input wire tec_lt96,
input wire tec_ge96,
input wire tec_ge128,
input wire tec_ge256,
input wire erb_eq128,
output reg resetcount,
output reg ... | 7.193381 |
module fault_encoder (
input wire clk,
input wire rstn,
input wire core_fault,
input wire ibus_fault,
input wire dbus_fault,
input wire pbus_fault,
input wire rom_i_fault,
input wire rom_d_fault,
input wire tcm_i_fault,
input wire tcm_d_fault,
input wire sram_i_fault,
in... | 7.320175 |
module fault_mem (
clk,
write_read,
address,
wdata,
rdata
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter CAPACITY = 65535; // 511 255
input clk;
input write_read;
input [ADDR_WIDTH-1:0] address;
input [DATA_WIDTH-1:0] wdata;
output [DATA_WIDTH-1:0] rdata;
re... | 6.967052 |
module FAusingHA (
input a,
input b,
input cin,
output sum,
output carry
);
wire s1, s2, s3;
half_adder_data h0 (
.a(a),
.b(b),
.sum(s1),
.carry(s2)
);
half_adder_data h1 (
.a(s1),
.b(cin),
.sum(sum),
.carry(s3)
);
assign carry = s2 | s3... | 7.495748 |
module faxil_register #(
// {{{
parameter AW = 4,
parameter DW = 32,
parameter [AW-1:0] ADDR = 0,
parameter [DW-1:0] MASK = -1,
parameter [DW-1:0] FIXED_BIT_MASK = 0,
localparam AXILLSB = $clog2(DW / 8),
parameter [0:0] OPT_ASYNC_RESET = 1'b0,
parameter [0:0] OPT_INITIAL = 1'b0
/... | 7.814357 |
module faxi_addr #(
// {{{
parameter AW = 32
// }}}
) (
// {{{
input wire [AW-1:0] i_last_addr,
input wire [2:0] i_size, // 1b, 2b, 4b, 8b, etc
input wire [1:0] i_burst, // fixed, incr, wrap, reserved
input wire [7:0] i_len,
output reg [7:0] o_incr,
output reg [AW-1:0] o_next_a... | 7.778453 |
module FA_24 (
a,
b,
cin,
s,
cout
);
parameter DATA_WIDTH = 24;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
input cin;
output [DATA_WIDTH -1 : 0] s;
output cout;
wire [1:0] tmp;
FA_8 FA_24_0 (
.a(a[7:0]),
.b(b[7:0]),
.cin(cin),
.s(s[7:0]),
... | 7.473333 |
module FA_25 (
a,
b,
cin,
s,
cout
);
parameter DATA_WIDTH = 25;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
input cin;
output [DATA_WIDTH -1 : 0] s;
output cout;
wire [2:0] tmp;
FA_8 FA_25_0 (
.a(a[7:0]),
.b(b[7:0]),
.cin(cin),
.s(s[7:0]),
... | 7.67124 |
module FA_4 (
a,
b,
cin,
s,
cout
);
parameter DATA_WIDTH = 4;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
input cin;
output [DATA_WIDTH -1 : 0] s;
output cout;
wire [DATA_WIDTH - 1:0] tmp;
FA FA_0 (
.x(a[0]),
.y(b[0]),
.cin(cin),
.s(s[0]),
... | 8.702845 |
module FA_48 (
a,
b,
cin,
s,
cout
);
parameter DATA_WIDTH = 48;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
input cin;
output [DATA_WIDTH -1 : 0] s;
output cout;
wire tmp;
FA_24 FA_24_0 (
.a(a[23:0]),
.b(b[23:0]),
.cin(cin),
.s(s[23:0]),
... | 7.793826 |
module FA_8 (
a,
b,
cin,
s,
cout
);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1:0] a;
input [DATA_WIDTH - 1:0] b;
input cin;
output [DATA_WIDTH -1 : 0] s;
output cout;
wire tmp;
FA_4 FA_0 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.s(s[3:0]),
.cout(tmp)... | 8.803062 |
module fa_1bit (
s,
c_out,
a,
b,
c_in
);
output c_out, s;
input a, b, c_in;
assign s = a ^ b ^ c_in;
assign c_out = (a & b) | (a & c_in) | (b & c_in);
endmodule
| 7.26038 |
module FA_8_tb ();
parameter DATA_WIDTH = 8;
reg [DATA_WIDTH-1:0] t_a;
reg [DATA_WIDTH-1:0] t_b;
reg t_cin;
wire cout;
wire [DATA_WIDTH-1:0] t_s;
FA_8 FA_8_0 (
.a(t_a),
.b(t_b),
.cin(t_cin),
.s(t_s),
.cout(cout)
);
initial begin
#0 t_a = 8'b0000000;
t_b = 8'... | 7.178631 |
module fa_b (
s,
co,
a,
b,
c
);
input a, b, c;
output s, co;
assign s = a ^ b ^ c;
assign co = (a & b) | (b & c) | (c & a);
endmodule
| 7.788289 |
module fold_xor3None (
input I0,
input I1,
input I2,
output O
);
assign O = (I0 ^ I1) ^ I2;
endmodule
| 7.818269 |
module Or3xNone (
input I0,
input I1,
input I2,
output O
);
assign O = |({I2, I1, I0});
endmodule
| 8.260437 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire and_inst0_out;
wire and_inst1_out;
wire and_inst2_out;
Or3xNone Or3xNone_inst0 (
.I0(and_inst0_out),
.I1(and_inst1_out),
.I2(and_inst2_out),
.O (COUT)
);
assign and_inst0_out = I0 &... | 7.610141 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module corebit_xor (
input in0,
input in1,
output out
);
assign out = in0 ^ in1;
endmodule
| 7.624638 |
module fold_xor3None (
input I0,
input I1,
input I2,
output O
);
wire xor_inst0_out;
wire xor_inst1_out;
corebit_xor xor_inst0 (
.in0(I0),
.in1(I1),
.out(xor_inst0_out)
);
corebit_xor xor_inst1 (
.in0(xor_inst0_out),
.in1(I2),
.out(xor_inst1_out)
);
a... | 7.818269 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
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