code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Or3xNone (
input I0,
input I1,
input I2,
output O
);
wire orr_inst0_out;
wire [2:0] orr_inst0_in;
assign orr_inst0_in = {I2, I1, I0};
coreir_orr #(
.width(3)
) orr_inst0 (
.in (orr_inst0_in),
.out(orr_inst0_out)
);
assign O = orr_inst0_out;
endmodule
| 8.260437 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire Or3xNone_inst0_O;
wire and_inst0_out;
wire and_inst1_out;
wire and_inst2_out;
wire fold_xor3None_inst0_O;
Or3xNone Or3xNone_inst0 (
.I0(and_inst0_out),
.I1(and_inst1_out),
.I2(and_inst2_o... | 7.610141 |
module fa_df (
input a,
b,
cin,
output sum,
carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module FA_final (
A,
B,
Cin,
S,
Cout
);
input A;
input B;
input Cin;
output S;
output reg Cout;
wire c1;
wire s1;
wire c2;
always @(*) begin : FA_prc_cout
reg or_ln8;
reg read_FA_c1_ln8;
reg read_FA_c2_ln8;
begin
read_FA_c1_ln8 = c1;
read_FA_c2_ln8 = c... | 6.898731 |
module and1 (
c,
a,
b
);
output c;
input a, b;
assign c = a & b;
endmodule
| 6.707901 |
module xor1 (
c,
a,
b
);
output c;
input a, b;
assign c = a ^ b;
endmodule
| 7.967626 |
module fa_gates (
s,
cout,
a,
b,
cin
);
output s, cout;
input a, b, cin;
xor1 u1 (
o1,
a,
b
);
xor1 u2 (
s,
o1,
cin
);
and1 u3 (
o2,
cin,
o1
);
and1 u4 (
o3,
a,
b
);
or u5 (cout, o2, o3);
endmodule
| 6.73766 |
module half_adder (
A,
B,
Sum,
Carry
);
input A, B;
output Sum, Carry;
assign Sum = A ^ B; //XOR Operation
assign Carry = A & B; //AND Operation
endmodule
| 6.966406 |
module fa_ha (
a,
b,
cin,
s,
co
);
input a, b, cin;
output s, co;
wire ha1_sum, ha2_sum, ha1_carry, ha2_carry, Sum, Carry;
//Instantiate Half Adder
half_adder ha1 (
.A(a),
.B(b),
.Sum(ha1_sum),
.Carry(ha1_carry)
);
half_adder ha2 (
.A(ha1_sum),
.... | 7.0661 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module FA_liu (
input A,
input B,
input a,
input b,
output S,
output E
);
xnor g1 (k, A, B);
nand g2 (l, a, b);
nand g3 (S, k, l);
nor g4 (E, k, l);
endmodule
| 7.369965 |
module _90_fa (
A,
B,
C,
X,
Y
);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1:0] A, B, C;
(* force_downto *)
output [WIDTH-1:0] X, Y;
(* force_downto *)
wire [WIDTH-1:0] t1, t2, t3;
wire _TECHMAP_FAIL_ = WIDTH > 1;
`FA_CELL FA (
.COUT(X),
.CIN(C),
.A... | 7.517837 |
module fa_Nb #(
parameter WIDTH = 4
) (
input CARRY_IN,
input [WIDTH-1:0] IN0,
input [WIDTH-1:0] IN1,
output [WIDTH-1:0] SUM,
output CARRY_OUT
);
reg [WIDTH-1:0] temp_sum;
reg temp_carry;
integer i = 0;
always @(*) begin
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) be... | 7.288712 |
module fa_nbits #(
parameter SIZE = 8,
APPROX_BITS = 0
) (
input signed [SIZE-1:0] a,
b,
approx_en,
input signed cin,
output logic signed [SIZE:0] sum,
output logic signed cout
);
//Sign Extension to account for overflow
logic signed [SIZE:0] a_ext, b_ext;
assign a_ext = {{a[SIZE-... | 6.609421 |
module fa_nbits_sub #(
parameter SIZE = 8,
APPROX_BITS = 0
) (
input signed [SIZE-1:0] a,
b,
approx_en,
input signed cin,
output logic signed [SIZE-1:0] sum,
output logic signed cout
);
logic cin_internal[SIZE:0];
assign cin_internal[0] = cin;
genvar i;
generate
for (i ... | 6.985641 |
module FA_post_build (
A,
B,
Cin,
S,
Cout
);
input A;
input B;
input Cin;
output S;
output reg Cout;
wire c1;
wire s1;
wire c2;
always @(*) begin : FA_prc_cout
reg or_ln8;
reg read_FA_c1_ln8;
reg read_FA_c2_ln8;
begin
read_FA_c1_ln8 = c1;
read_FA_c2_ln... | 6.505672 |
module FA_rtl (
A,
B,
Cin,
S,
Cout
);
input A;
input B;
input Cin;
output S;
output Cout;
wire c1;
wire s1;
wire c2;
HA_rtl ha1_ptr (
.A(A),
.B(B),
.Sum(s1),
.Carry(c1)
);
HA_rtl ha2_ptr (
.A(s1),
.B(Cin),
.Sum(S),
.Carry(c2)
)... | 7.142349 |
module FullAdder (
input I0,
input I1,
input I2,
output O,
output COUT
);
wire LUT3_inst0_O;
wire LUT3_inst1_O;
LUT3 #(
.INIT(8'h96)
) LUT3_inst0 (
.I0(I0),
.I1(I1),
.I2(I2),
.O (LUT3_inst0_O)
);
LUT3 #(
.INIT(8'hE8)
) LUT3_inst1 (
.I0(I0),
... | 7.610141 |
module FullAdder (
input I0,
input I1,
input I2,
output O,
output COUT
);
wire LUT3_inst0_O;
wire LUT3_inst1_O;
LUT3 #(
.INIT(8'h96)
) LUT3_inst0 (
.I0(I0),
.I1(I1),
.I2(I2),
.O (LUT3_inst0_O)
);
LUT3 #(
.INIT(8'hE8)
) LUT3_inst1 (
.I0(I0),
... | 7.610141 |
module fA_sram_3 #(
parameter WIDTH_A = 12
) (
input [WIDTH_A-1:0] addr,
output [15:0] coef
);
wire [15:0] Coef[0:39];
assign Coef[0] = 'h0013;
assign Coef[1] = 'h0011;
assign Coef[2] = 'h0014;
assign Coef[3] = 'h000c;
assign Coef[4] = 'h0017;
assign Coef[5] = 'h0014;
assign Coef[6] = '... | 6.760821 |
module FA_using_HA (
A,
B,
Cin,
Sum,
Carry
);
input A, B, Cin;
output Sum, Carry;
wire w1, w2, w3;
Half_Adder h1 (
w1,
w2,
A,
B
);
Half_Adder h2 (
Sum,
w3,
w1,
Cin
);
or (Carry, w2, w3);
endmodule
| 7.481402 |
module: fulladder_u_halfadder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fatb();
reg a, b , cin;
wire sum, cout;
fa uut(sum,cout,a,b,cin);
initial
begin
$monitor ($time... | 6.551784 |
module fa (
output wire sum,
output wire c_out,
input wire a,
input wire b,
input wire c_in
);
wire sum1, carry1, carry2;
ha_v1 ha1 (
sum1,
carry1,
a,
b
);
ha_v1 ha2 (
sum,
carry2,
c_in,
sum1
);
or or1 (c_out, carry1, carry2);
endmodu... | 7.730301 |
module fa_v1_tb;
//declaracion de se�ales
reg
test_a,
test_b,
test_cin; //las se�ales de entrada al semisumador. Se han declarado reg porque queremos inicializarlas (las variables tipo reg solo se usan para almacenar valores)
wire test_sum, test_carry; //se�ales de salida, se declaran como wire... | 7.09063 |
module fa_v2 (
a,
b,
ci,
s
);
input a, b, ci; //input a,b,carry in
output s; //output sum
wire w0; //use 1 wire
_xor2 U0_xor2 (
.a(a),
.b(b),
.y(w0)
); //XOR gate
_xor2 U1_xor2 (
.a(w0),
.b(ci),
.y(s)
); //XOR gate
endmodule
| 6.868122 |
module fba (
A,
B,
Cin,
sum,
carry
);
input [3:0] A, B;
output [3:0] sum;
input Cin;
output carry;
wire w0, w1, w2;
FullAdder FA_0 (
A[0],
B[0],
Cin,
sum[0],
w0
);
FullAdder FA_1 (
A[1],
B[1],
w0,
sum[1],
w1
);
FullAdder... | 7.163771 |
module: FPAddSub_PreAlignModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module FBAddSub_PreAlignModule_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
// Outputs
wire Sa;
wire Sb;... | 6.797701 |
module FBCV_ALU_Decoder (
input [11:0] FBC_Th_Value, //That comes from the IR' 12 bits ontop of MUX2 in the simple MU0 design and after having been passed through the FORCE for FBC instruction - We ensure that we will always know the the th nu of the fib number we are looking for
//input [15:0] FBCV_RAm_DataO... | 7.441714 |
module FBCV_FORCE (
input [15:0] IR_Prime_16,
output [15:0] FBC_V
);
assign FBC_V[11:0] = IR_Prime_16[11:0];
assign FBC_V[15:12] = 0;
endmodule
| 6.605588 |
module FBDisplay (
input start,
input clock,
input resetn,
output reg finished,
input finished_dp,
input [`RESULT_WIDTH-1:0] result_dp,
output reg start_dp,
output reg [`INSTRUCTION_WIDTH-1:0] instruction_dp
);
reg [`FBDISP_OP_WIDTH-1:0] cur_state;
// TODO declare any register
... | 7.413839 |
module FBHelper (
input clk,
input valid,
input [31:0] pixel,
input sync
);
always @(posedge clk) begin
if (valid) put_pixel(pixel);
if (sync) vmem_sync();
end
endmodule
| 6.832359 |
module Fblock_salt (
input [31:0] R,
input [59:0] K,
output [31:0] F_RK,
input CLK
);
wire [47:0] RE;
wire [47:0] RE_x;
Eblock Eblock_instance (
R,
RE
);
xor_48_salt xor_48_instance (
RE,
K,
RE_x,
CLK
);
SP_block SP_block_instance (
RE_x,
... | 7.112322 |
module FBST #(
parameter pHRES = 1280,
parameter pVRES = 720,
parameter pHTOTAL = 1354,
parameter pVTOTAL = 910,
parameter pHSS = 1300,
parameter pHSE = 1340,
parameter pVSS = 778,
parameter pVSE = 782
) (
input iCLK,
output [7:0] oRED,
output [7:0] oGRN,
... | 6.698779 |
module: fbs
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fbs_tb;
// Inputs
reg clk;
reg backup;
reg restore;
reg [255:0] dataIn;
// Outputs
wire [255:0] dataOut;
wire re... | 6.684006 |
module FB_addr_col_gen #(
parameter WIDTH = 13
)
// input signals
(
clk,
rst,
enable,
steep,
x_coord,
y_coord,
// output signals
FB_addr,
color_out
);
input clk, rst, enable, steep;
input [WIDTH-1:0] x_coord, y_coord;
output reg color_out;
output reg [18:0] FB_addr;
al... | 7.182568 |
module FB_blue_mem #(
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 20
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we_2,
clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] b_ram[614399:0];
alway... | 6.553666 |
module FB_green_mem #(
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 20
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we_2,
clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] g_ram[614399:0];
alwa... | 7.860813 |
module fb_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
inpu... | 7.183263 |
module fb_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 ... | 6.923508 |
module fb_ram_dual (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// ... | 6.505785 |
module FB_red_mem #(
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 20
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr,
write_addr,
input we_2,
clk,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] r_ram[614399:0];
always... | 6.762221 |
module fb_topstatem (
clk_top,
rst,
SystemEnd,
SystemStart,
PHYInitEnd,
NumbFrameReturned,
DistFrameReturned,
DelayFrameReturned,
DelayDistFrameReturned,
ConfigEnd,
DataFrameGo,
StateIdle,
StateNumb,
StateDist,
StateDelay,
StateDelayDist,
StateData,
... | 6.898237 |
module FC (
clk,
rst,
cmd,
done,
M_RW,
M_A,
M_D,
F_IO,
F_CLE,
F_ALE,
F_REN,
F_WEN,
F_RB
);
input clk;
input rst;
input [32:0] cmd;
output done;
output M_RW;
output [6:0] M_A;
inout [7:0] M_D;
inout [7:0] F_IO;
output F_CLE;
output F_ALE;
output ... | 6.751893 |
module fc2_ctrl ( /*autoport*/
//output
f6_raddr,
w6_raddr,
f7_wr_en,
fc2_done,
fc2_clr,
//input
clk,
rst_n,
fc2_start
);
input clk;
input rst_n;
//Input Weight and Feature Read Addr
output [6:0] f6_raddr;
output [6:0] w6_raddr;
//Output Feature Write Enable
outpu... | 7.209725 |
module fc3_ctrl ( /*autoport*/
//output
f7_raddr,
w7_raddr,
f8_wr_en,
fc3_done,
fc3_clr,
//input
clk,
rst_n,
fc3_start
);
input clk;
input rst_n;
//Input Weight and Feature Read Addr
output [6:0] f7_raddr;
output [6:0] w7_raddr;
//Output Feature Write Enable
outp... | 7.459061 |
module fc3_exec ( /*autoport*/
//output
class0,
class1,
class2,
class3,
class4,
class5,
class6,
class7,
class8,
class9,
//input
clk,
rst_n,
f8_wr_en,
mac_5
);
input clk;
input rst_n;
input f8_wr_en;
input [229:0] mac_5; //mac result. mac5_1 ~ m... | 7.180268 |
module fcache (
input clk,
input write,
input [15:0] addr,
input [255:0] wData,
output [255:0] rData
);
reg [255:0] regfile[0:1023];
assign rData = regfile[addr];
always @(posedge clk) begin
if (write) regfile[addr] <= wData;
end
endmodule
| 6.972458 |
module fcalc (
input [1:0] sel,
input [31:0] b,
input [31:0] c,
input [31:0] d,
output reg [31:0] f
);
always @(*) begin
case (sel)
// 0 <= i <= 15
2'b00: f <= (b & c) | (~b & d);
// 16 <= i <= 31
2'b01: f <= (d & b) | (~d & c);
// 32 <= i <= 47
2'b10: f <=... | 6.844028 |
module fcctl ( /*AUTOARG*/
// Outputs
afc,
ro,
// Inputs
credit,
ri,
rst
);
parameter VCN = 2; // number of VCs per direction
parameter PD = 3; // depth of an input VC buffer
input [VCN-1:0] credit; // credit input from the next router
output [VCN-1:0] afc; // ack for the credi... | 7.183538 |
module fce2 (
input wire clock,
input wire reset,
input wire inconerec, // MACFSM zu REC
input wire incegtrec, // MACFSM zu REC
input wire incegttra, // MACFSM zu TEC
input wire decrec, // MACFSM zu REC
input wire dectra, ... | 7.475673 |
module fcell (
input [63:0] IN,
input [31:0] KEY,
output [63:0] OUT
);
wire [31:0] a = IN[63:32];
wire [31:0] b = IN[31:0];
wire [31:0] f_out;
f f (
.X(a),
.K(KEY),
.Y(f_out)
);
assign OUT = {b ^ f_out, a};
endmodule
| 7.230309 |
module ha (
Cout,
Sum,
A,
B
);
input A, B;
output Cout, Sum;
/*
assign Cout = A & B;
assign Sum = A ^ B;
*/
SEH_ADDH_1 ha_inst (
.A (A),
.B (B),
.S (Sum),
.CO(Cout)
);
endmodule
| 8.17767 |
module fa (
Cout,
Sum,
A,
B,
C
);
input A, B, C;
output Cout, Sum;
//assign Cout = ((A&B) | (B&C) |(A&C));
/*
assign Cout = ~(~(A&B) & ~(B&C) & ~(A&C));
assign Sum = A^B^C;
*/
SEH_ADDF_D_1 fa_inst (
.A (A),
.B (B),
.CI(C),
.S (Sum),
.CO(Cout)
);
endmodul... | 7.316157 |
module rfa (
g,
p,
Sum,
A,
B,
Cin
);
input A, B, Cin;
output g, p, Sum;
assign g = A & B;
assign p = A ^ B;
assign Sum = p ^ Cin;
endmodule
| 6.90999 |
module cla8 (
Sum,
G,
P,
A,
B,
Cin
);
input [7:0] A, B;
input Cin;
output [7:0] Sum;
output G, P;
wire [7:0] gtemp1;
wire [7:0] ptemp1;
wire [7:0] ctemp1;
wire ctemp2;
wire [1:0] gouta, pouta;
rfa r01 (
gtemp1[0],
ptemp1[0],
Sum[0],
A[0],
B[0],... | 6.866219 |
module fcla8 (
Sum,
G,
P,
A,
B,
Cin
);
input [7:0] A, B;
input Cin;
output [7:0] Sum;
output G, P;
wire [7:0] gtemp1;
wire [7:0] ptemp1;
wire [7:0] ctemp1;
wire ctemp2;
wire [1:0] gouta, pouta;
mpfa r01 (
.g_b(gtemp1[0]),
.p (ptemp1[0]),
.Sum(Sum[0]),
... | 6.631469 |
module fcn5b (
input clk,
input [4:0] data_in,
output [4:0] L
);
// A is the lowest order bit
wire A, B, C, D, E;
assign {E, D, C, B, A} = data_in;
// Bit encoding for 5B/6B Classifications
// It counts the number of 1s and 0s in ABCD
// L40 means Four 1s and No 0s
wire L40, L31, L22, L13, L... | 6.763366 |
module fcn5b6b (
input clk,
input reset,
input [4:0] data_in,
input [4:0] L,
input K,
input COMPLS6,
output [5:0] data_out
);
wire A, B, C, D, E;
assign {E, D, C, B, A} = data_in;
wire L40, L31, L22, L13, L04;
assign {L40, L31, L22, L13, L04} = L;
reg a, b, c, d, e, i;
/* Transfo... | 6.627351 |
module feq (
input wire [31:0] x,
input wire [31:0] y,
output wire z
);
assign z = x == y ? 1'b1 : 1'b0;
endmodule
| 6.534988 |
module fCounter (
validS0,
validS1,
motorspeed,
faEnable,
fCount
);
input faEnable, validS0, validS1;
input signed [7:0] motorspeed;
output reg [15:0] fCount;
//Need to make to make boundary controls for this go from 1- 655. Debug counting logic.
initial begin
fCount = 16'b0000000110... | 7.513218 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v;
inout data;
wire ping_from_master, reset_from_master, par_error, rx_data_valid,
tx_done, pl_tx_en, pl_tx_type, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECT... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v;
inout data;
wire ping_from_master, reset_from_master, par_error, rx_data_valid,
tx_done, pl_tx_en, pl_tx_type, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECT... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v;
inout data;
wire ping_from_master, reset_from_master, par_error, rx_data_valid,
tx_done, pl_tx_en, pl_tx_type, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECT... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v;
inout data;
wire ping_from_master, reset_from_master, afc_iden, par_error,
rx_data_valid, tx_done, pl_tx_en, pl_tx_type, pl_tx_afc,
SYNOPSYS_UNCONNECTED_... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
out_en,
data_out,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v, data;
output out_en, data_out;
wire ping_from_master, reset_from_master, afc_iden, par_error,
rx_data_valid, tx_done, pl_tx_en, pl_tx_ty... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
out_en,
data_out,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v, data;
output out_en, data_out;
wire ping_from_master, reset_from_master, afc_iden, par_error,
rx_data_valid, tx_done, pl_tx_en, pl_tx_ty... | 8.605588 |
module fcp_core (
clk,
rstn,
is_support_12v,
out_volt,
data
);
output [1:0] out_volt;
input clk, rstn, is_support_12v;
inout data;
wire ping_from_master, reset_from_master, par_error, rx_data_valid,
tx_done, pl_tx_en, pl_tx_type, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECT... | 8.605588 |
module fcp_core (
clk,
rstn,
// I
is_support_12v,
// O
out_volt,
// IO
data
//out_en,
//data_out,
//data
);
//================================
// IO ports
//================================
input clk;
input rstn;
input is_support_12v;
output [1:0] out_volt; //... | 8.605588 |
module for data[31:0] , crc[7:0]=1+x^3+x^4+x^5+x^8;
//-----------------------------------------------------------------------------
module fcp_crc(
input [31:0] data_in,
input crc_en,
output [7:0] crc_out,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
... | 7.342293 |
module FCGPIOTestBitstream (
gpio_in,
gpio_out,
led_0,
led_1
);
(* IOSTANDARD="LVCMOS33" *) (* LOC="P8" *) input wire gpio_in;
(* IOSTANDARD="LVCMOS33" *) (* LOC="P6" *) output wire gpio_out;
(* IOSTANDARD="LVCMOS33" *) (* LOC="P38" *) output wire led_0;
(* IOSTANDARD="LVCMOS33" *) (* LOC="P37" ... | 6.810734 |
module fcu ( // Flag Computation Unit
input wire [15:0] alu_out,
input wire carry,
input wire ovf,
input wire zero,
input wire [2:0] op,
output reg flag
);
// sign extraction
wire sgn;
assign sgn = alu_out[15];
`include "ops.vh"
// op function
// ----------------------
/... | 7.640257 |
module fcw_ram (
input clk,
input rst,
input rd_en,
input wr_en,
input [1:0] addr,
input [23:0] d_in,
output reg [23:0] d_out
);
reg [23:0] ram[3:0];
always @(posedge clk) begin
if (rst) begin
ram[0] <= 24'd0; // replace the RAM reset values with the values you computed
... | 6.93304 |
module fcw_register (
input clk,
input rst,
input we,
input [23:0] fcw_in,
output reg [23:0] fcw_out
);
always @(posedge clk) begin
if (rst) fcw_out <= 24'b0;
else if (we) fcw_out <= fcw_in;
end
endmodule
| 7.685726 |
module fc_84 #(
parameter BIT_WIDTH = 32,
OUT_WIDTH = 64
) (
input signed [BIT_WIDTH*84-1:0] in,
input signed [BIT_WIDTH*84-1:0] in_weights,
input signed [BIT_WIDTH-1:0] bias,
output signed [OUT_WIDTH-1:0] out // size should increase to hold the sum of products
);
// convert flattened input ... | 7.115816 |
module fc_w_bram_top (
input clk,
input fc_w_bram_ena,
input [9 : 0] fc_w_bram_addra,
output [959 : 0] fc_w_bram_douta,
input fc_w_bram_enb,
input [9:0] fc_w_bram_addrb,
output [959 : 0] fc_w_bram_doutb
);
FC_W_BRAM u_fc_w_bram (
.clka (clk), // input wire clka
.e... | 6.623359 |
module FD3 (
input nCK,
input D,
input PR,
output reg Q = 1'b0,
output nQ
);
always @(negedge nCK or negedge PR) begin // Posedge ?
if (!PR) Q <= 1'b1; // tmax = 5.2ns
else Q <= D; // tmax = 5.4ns
end
assign nQ = ~Q;
endmodule
| 6.558862 |
module fd4q (
output q,
input d,
input cp,
input sd,
input sys_clk
);
reg fd_data = 1'b1;
assign q = fd_data;
// always @(posedge cp or negedge sd)
always @(posedge sys_clk) begin
if (cp | (~sd)) begin
if (~sd) begin
fd_data <= 1'b1;
end else begin
fd_d... | 6.732971 |
module fdbk_core (
input clk, // timespec 8.0 ns
input sync, // one in eight
input iq, // high on first
input signed [17:0] in_xy,
output signed [17:0] out_xy,
output [11:0] cmp_event, // see mp_proc.v
(* external *)
input [1:0] coarse_scale, // external
`AUTOMATIC_self
);
//... | 7.018707 |
module FDBuffer (
clk,
pc,
instr,
interruptSignal,
pcOut,
instrOut,
interruptSignalOut
);
// Inputs to the buffer
input [15:0] instr;
input [31:0] pc;
input clk, interruptSignal;
// Outputs from the buffer
output reg [15:0] instrOut;
output reg [31:0] pcOut;
output reg int... | 7.281821 |
module fdc1772_dpram #(
parameter DATAWIDTH = 8,
ADDRWIDTH = 9
) (
input clock,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
output reg [DATAWIDTH-1:0] q_a,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:... | 6.583183 |
module fdecode (
input wire [DATAW-1:0] a,
output wire sign,
output wire [EXPW-1:0] exponent,
output wire [MANW:0] fullman,
output wire zeroexp,
output wire hidden,
output wire infexp,
output wire zeroman,
output wire maxman,
output wire nan,
output wire infinity,
output ... | 7.413871 |
module FDE_Rex_Runner (
clk, //120kHz
rstn,
start_i,
db_o,
dori_o,
cs_o,
en_o,
rw_o,
rst_o,
state
);
input clk, rstn;
input start_i;
output [7:0] db_o;
output dori_o;
output [3:0] cs_o;
output en_o;
output rw_o;
output rst_o;
output [2:0] state;
wire [10:... | 9.514631 |
module FDE_Rex_Runner (
clk, //120kHz
rstn,
jmp_key,
db_o,
dori_o,
cs_o,
en_o,
rw_o,
rst_o,
state
);
input clk, rstn;
input jmp_key;
output [7:0] db_o;
output dori_o;
output [3:0] cs_o;
output en_o;
output rw_o;
output rst_o;
output [2:0] state;
wire star... | 9.514631 |
module FDG (
input CK,
input D,
input nCL,
output reg Q,
output nQ
);
// Same function as FDO ?
always @(posedge CK or negedge nCL) begin
if (!nCL) Q <= 1'b0; // tmax = 5.3ns
else Q <= D; // tmax = 4.2ns
end
assign nQ = ~Q;
endmodule
| 6.598968 |
module FDIV3 (
input CLK,
output K_OR,
K1,
K2
);
reg [2:0] C1, C2;
reg M1, M2;
always @(posedge CLK) begin
if (C1 == 4) C1 <= 0;
else C1 <= C1 + 1;
if (C1 == 1) M1 <= ~M1;
else if (C1 == 3) M1 = ~M1;
end
always @(negedge CLK) begin
if (C2 == 4) C2 <= 0;
else C2 <= C2 +... | 6.500317 |
module FDM (
input CK,
input D,
output reg Q,
output nQ
);
always @(posedge CK) Q <= #2 D;
assign nQ = ~Q;
endmodule
| 6.852183 |
module FDN (
input CK,
input D,
input nS,
output reg Q,
output nQ
);
always @(posedge CK or negedge nS) begin
if (!nS) Q <= 1'b1; // tmax = 2.9ns
else Q <= D; // tmax = 6.1ns
end
assign nQ = ~Q;
endmodule
| 6.653656 |
module FDreg (
input clk,
input reset,
input ExcClr,
input EN,
input [31:0] InstrIn,
input [31:0] PCAdd8In,
input [31:0] curPCIn,
input BDIn,
input ExcGetIn,
input [4:0] ExcCodeIn,
output [31:0] InstrOut,
output [31:0] PCAdd8Out,
output [31:0] curPCOut,
output BDO... | 6.946752 |
module FDS16bit (
input CK,
input [15:0] D,
output [15:0] Q
);
FDSCell CellA (
CK,
D[3:0],
Q[3:0]
);
FDSCell CellB (
CK,
D[7:4],
Q[7:4]
);
FDSCell CellC (
CK,
D[11:8],
Q[11:8]
);
FDSCell CellD (
CK,
D[15:12],
Q[15:12]
)... | 6.868339 |
module fdt (
// WB
input wire wb_rst_i,
input wire wb_clk_i,
input wire [31:0] wb_dat_i,
input wire [13:2] wb_adr_i,
input wire [ 3:0] wb_sel_i,
input wire wb_we_i,
input wire wb_cyc_i,
input wire wb_stb_i,
output reg [31:0] wb_dat_o,
... | 7.779996 |
module FD_AddrCal (
refAddr,
adjNumber,
sramAddr,
sramRead
);
input [14:0] refAddr; // 기준점
input [4:0] adjNumber; // 인접한 16개의 점
output [14:0] sramAddr; // SRAM의 Input 주소
output sramRead; // SRAM 읽기 신호
assign sramRead = (adjNumber == 5'd0) ? 1'b0 : 1'b1;
assign sramAddr = (adjNumber == ... | 7.192927 |
module FD_flipflop (
input wire clk,
input wire [31:0] RD,
input wire [31:0] PCPlus4F,
input wire CLR,
input wire EN,
output reg [31:0] InstrD,
output reg [31:0] PCPlus4D
);
//----------------------------------------
always @(posedge clk) begin
if (EN) ... | 7.125333 |
module fd_latch (
pc_out,
ir_out,
pc_in,
ir_in,
clock,
clear,
enable
);
// enable = ~ dostall
input clock, clear, enable;
input [31:0] pc_in, ir_in;
output [31:0] pc_out, ir_out;
// module register(out, in, clk, input_enable, clr);
register PC (
pc_out,
pc_in,
... | 7.004255 |
module FD_Testbench;
reg clock;
reg nReset;
wire isCorner; // 코너 확인
wire [14:0] refAddr; // 기준점 주소
wire [7:0] refPixel; // 기준점 데이터
wire [127:0] adjPixel; // 인접한 16개의 점 데이터
wire [7:0] thres; // 임계값
always begin
#10 clock = ~clock;
if (clock && isCorner) // 코너로 확인된 특징점인 경우에 출력
$displ... | 7.516199 |
module feadd (
input wire clock,
start,
input wire [254:0] a_in,
b_in,
output reg done = 0,
output wire [254:0] out
);
parameter W = 17; // hardware multiplier input word size
parameter N = 15; // number of words used to represent one field element
parameter C = 19; // pseudo-Mersenne c... | 7.597981 |
module feature (
input pixelclk,
input rst_n,
input post01_img_Bit,
input i_hs,
input i_vs,
input i_de,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output reg [22:0] s0,
output ... | 6.870331 |
module feature_1 (
input pixelclk,
input rst_n,
input i_hs,
input i_vs,
input i_de,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output [15:0] a2,
output [ 7:0] f1
// output [7:0]... | 6.53746 |
module feature_map_buffer_ctrl (
input clock,
input reset,
input data_rdy,
input [`X_COORD_BITWIDTH:0] xcoord,
input [`Y_COORD_BITWIDTH:0] ycoord,
output reg [`FM_ADDR_BITWIDTH:0] addr,
output reg buffer_full
);
//assign addr = xcoord + (ycoord * `FM_ADDR_WIDTH'd`FM_WIDTH);
always @(... | 7.045541 |
module feature_write_addr_gen_Add2i1u32_1 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u32_4 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
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