code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module feature_write_addr_gen_Add2i1u32_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u32_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u32_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u32_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1) + (32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add2i1u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) + (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux1U_32U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_32Ux32U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Add_3Ux1U_3U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_DECODE_2U_29_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_DECODE_2U_29_4_0 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_DECODE_2U_29_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_DECODE_2U_29_4_2 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_DECODE_2U_32_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi1u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000001 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi2u8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000010 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi3u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000011 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi4u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000100 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi5u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000101 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi6u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (8'B00000110 == in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Eqi7u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (&in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux1U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux2U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_3Ux3U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_8Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_8Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_8Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Equal_8Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u32u32u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
ass... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u32u32u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
ass... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u32u32u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
a... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u32u32u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
a... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u32u32u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
a... | 7.136373 |
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