repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a_lp.v | 2,256 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR1,
VAR3,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR9 ;
VAR10 VAR2 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/flow_classification.v | 4,864 | module MODULE1
( output [63:0] VAR39,
output [23:0] VAR4,
output VAR45,
output reg VAR31,
input VAR20,
output VAR42,
output [63:0] VAR33,
output [23:0] VAR38,
output VAR30,
output reg VAR49,
input VAR24,
output VAR16,
input [63:0] VAR25,
input [7:0] VAR37,
input VAR5,
output VAR50,
input VAR35,
input VAR43,
input VAR53... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/4f6a1e871ce3ebaf/gcd_block_design_gcd_0_1_stub.v | 2,706 | module MODULE1(VAR16,
VAR19, VAR10, VAR2, VAR5,
VAR14, VAR15, VAR12, VAR13,
VAR18, VAR11, VAR3,
VAR8, VAR1, VAR6, VAR4,
VAR17, VAR7, VAR9, interrupt)
;
input [5:0]VAR16;
input VAR19;
output VAR10;
input [31:0]VAR2;
input [3:0]VAR5;
input VAR14;
output VAR15;
output [1:0]VAR12;
output VAR13;
input VAR18;
input [5:0]VAR1... | mit |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/BRAM1.v | 2,704 | module MODULE1(VAR4,
VAR1,
VAR8,
VAR11,
VAR5,
VAR10
);
parameter VAR7 = 0;
parameter VAR14 = 1;
parameter VAR13 = 1;
parameter VAR12 = 1;
input VAR4;
input VAR1;
input VAR8;
input [VAR14-1:0] VAR11;
input [VAR13-1:0] VAR5;
output [VAR13-1:0] VAR10;
reg [VAR13-1:0] VAR3[0:VAR12-1];
reg [VAR14-1:0] VAR6;
reg [VAR13-1:0] ... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/sdram/sdram_ctrl.v | 28,165 | module MODULE1(
input wire VAR64,
input wire VAR4,
input wire VAR26,
input wire VAR39,
input wire VAR55,
input wire [ 4-1:0] VAR13,
output wire VAR81,
output reg [ 13-1:0] VAR54,
output reg [ 4-1:0] VAR177,
output reg [ 2-1:0] VAR118,
output reg VAR94,
output reg VAR82,
output reg VAR80,
output reg [ 2-1:0] VAR62,
inou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.symbol.v | 1,343 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR6
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetReg.v | 1,724 | module MODULE1 (
input VAR2,
output reg VAR1,
input en,
input clk,
input rst);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR1 <= 1'b0;
end else if (en) begin
VAR1 <= VAR2;
end
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.pp.symbol.v | 1,409 | module MODULE1 (
input VAR7 ,
output VAR3 ,
input VAR2 ,
input VAR1 ,
input VAR4 ,
input VAR8 ,
input VAR6,
input VAR9,
input VAR5
);
endmodule | apache-2.0 |
freecores/zet86 | impl/virtex4-ml403ep/dbg/send_addr.v | 1,747 | module MODULE1 (
output reg [ 4:0] VAR16,
output reg VAR1,
output VAR12,
input VAR3,
input VAR18,
input [19:0] VAR14,
input VAR10,
input VAR9,
input VAR20,
output VAR21
);
reg [4:0] VAR16;
reg VAR1;
wire VAR17;
wire VAR11;
wire VAR5;
wire [7:0] VAR8;
wire [7:0] b0, b1, VAR7, VAR2, VAR19;
VAR13 VAR4 (
.VAR12 (VAR12),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.behavioral.pp.v | 1,940 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR3,
VAR12 ,
VAR11
);
output VAR13 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR12 ;
input VAR11 ;
wire VAR7 ;
wire VAR9;
buf VAR6 (VAR7 , VAR8 );
VAR4 VAR10 (VAR9, VAR7, VAR3, VAR5);
buf VAR1 (VAR13 , VAR9 );
endmodule | apache-2.0 |
nyaxt/dmix | resample_pipeline_t.v | 2,078 | module MODULE1;
parameter VAR17 = 100000;
reg [15:0] VAR10 [VAR17-1:0];
reg [16:0] VAR1;
wire [15:0] VAR8 = VAR10[VAR1];
wire [23:0] VAR13 = {VAR8, 8'b0}; reg [23:0] VAR6;
parameter VAR9 = 10;
reg clk;
reg rst;
reg [(VAR11-1):0] VAR18;
reg [(24*VAR11-1):0] VAR7;
reg [(VAR11-1):0] VAR5;
wire [23:0] VAR12;
VAR3 #(.VAR11(... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/fifo_4x32.v | 1,881 | module MODULE1(
input [31:0] din, input VAR7,
input VAR5,
output [31:0] dout, output VAR6,
output VAR3,
input reset,
input clk
);
parameter VAR4 = 2;
parameter VAR2 = 2 ** VAR4;
reg [31:0] VAR8 [VAR2 - 1 : 0];
reg [VAR4 - 1 : 0] VAR9;
reg [VAR4 - 1 : 0] VAR1;
reg [VAR4 - 1 + 1 : 0] VAR10;
always @(posedge clk)
begin
if... | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_ams.v | 6,055 | module MODULE1 (
input VAR19 , input VAR12 , output reg [ 24-1: 0] VAR7 , output reg [ 24-1: 0] VAR17 , output reg [ 24-1: 0] VAR15 , output reg [ 24-1: 0] VAR6 , input [ 14-1: 0] VAR25 , input [ 14-1: 0] VAR5 ,
input [ 32-1: 0] VAR23 , input [ 32-1: 0] VAR16 , input [ 4-1: 0] VAR22 , input VAR13 , input VAR2 , output ... | mit |
AntonovAlexander/activecore | designs/rtl/fifo/fifo.v | 2,133 | module MODULE1
parameter VAR7=8,
VAR8=4
)
(
input wire clk, reset,
input wire rd, wr,
input wire [VAR7-1:0] VAR10,
output wire VAR13, VAR18,
output wire [VAR7-1:0] VAR6
);
reg [VAR7-1:0] VAR9 [2**VAR8-1:0]; reg [VAR8-1:0] VAR1, VAR16, VAR12;
reg [VAR8-1:0] VAR2, VAR3, VAR14;
reg VAR17, VAR15, VAR4, VAR11;
wire VAR5;
al... | apache-2.0 |
fanatid/gost28147-89 | rtl/gost89_pipelined_ecb.v | 8,019 | module MODULE2(
input clk,
input [511:0] VAR39,
input [255:0] VAR25,
input [63:0] in,
output [63:0] out
);
reg [31:0] VAR5[31:0], VAR36[31:0];
wire [31:0] VAR28[31:0], VAR32[31:0];
always @(posedge clk) begin
VAR5[0] <= in[63:32]; VAR36[0] <= in[31:0];
VAR5[1] <= VAR28[0]; VAR36[1] <= VAR32[0];
VAR5[2] <= VAR28[1]; VAR... | bsd-3-clause |
mahdienan/Spongent | verilog/pLayer.v | 1,412 | module MODULE1(VAR7, VAR10, clk, rst, VAR11, en);
input clk;
input rst;
input [263:0] VAR7;
input en;
output reg [263:0] VAR10;
output reg VAR11;
wire [7:0] VAR2;
reg [7:0] VAR13 [0:32];
reg [263:0] VAR1;
reg [7:0] VAR6, VAR8;
reg [31:0] VAR4, VAR3;
wire [8:0] VAR5 [8:0][32:0];
reg [31:0] VAR12;
integer VAR9; | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.behavioral.v | 1,098 | module MODULE1( VAR3, VAR4 );
input VAR3;
output VAR4;
VAR1 VAR5(.VAR3(VAR3),.VAR4(VAR4));
VAR1 VAR2(.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.symbol.v | 1,393 | module MODULE1 (
input VAR9,
input VAR4,
input VAR3,
input VAR2,
input VAR8,
output VAR10
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.functional.pp.v | 2,063 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR5 ,
VAR3,
VAR15,
VAR13,
VAR10 ,
VAR2
);
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR3;
input VAR15;
input VAR13;
input VAR10 ;
input VAR2 ;
wire VAR4 ;
wire VAR11 ;
wire VAR7;
nand VAR1 (VAR4 , VAR5, VAR12 );
nand VAR16 (VAR11 , VAR3, VAR4 );
VAR9 VAR14 (VAR7, VAR11, VAR15, VAR1... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/J1_soc-master/hdl/j1soc.v | 2,266 | module MODULE1#(
parameter VAR14 = "../VAR8/VAR2/VAR21.VAR19" )(
VAR18, VAR1,
VAR22, VAR23, VAR12, VAR4
);
input VAR18, VAR1,VAR22;
output VAR23, VAR12, VAR4;
wire VAR5; wire VAR16; wire [15:0] VAR7; reg [15:0] VAR15; wire [15:0] VAR9;
reg [1:4]VAR3;
wire [15:0] VAR17;
VAR21 #(VAR14) VAR20(VAR18, VAR1, VAR15, VAR5, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap.functional.pp.v | 1,172 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.pp.symbol.v | 1,350 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR4,
output VAR2 ,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
ludisu13/Estructuras2 | tarea45/pc_decider.v | 1,618 | module MODULE2(
input wire VAR15,
input wire VAR4,
output wire [9:0]VAR13,
input wire VAR9,
input wire VAR11,
input wire [9:0] VAR2
);
wire [9:0] VAR6;
wire [9:0] VAR14;
wire [9:0]VAR10;
wire [9:0] VAR16;
wire [9:0]VAR1;
reg [9:0] VAR12;
assign VAR1 = VAR12;
assign VAR10 = (VAR4) ? 10'b0 : VAR12;
assign VAR13 = (VAR9|V... | gpl-3.0 |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/syn/Altera/i2cSlaveTopAltera.v | 3,592 | module MODULE1 (
clk,
VAR3,
VAR12,
VAR19
);
input clk;
inout VAR3;
input VAR12;
output VAR19;
reg [1:0] VAR2;
wire rst;
wire VAR6;
wire [7:0] VAR9;
assign VAR19 = VAR9[0];
VAR13 VAR10(
.clk(clk),
.rst(rst),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR11(),
.VAR16(),
.VAR18(),
.VAR17(8'h12),
.VAR14(8'h34),
.VAR1(8'h56)... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.blackbox.v | 1,360 | module MODULE1 (
VAR8 ,
VAR4,
VAR1,
VAR2,
VAR5,
VAR3
);
output VAR8 ;
input VAR4;
input VAR1;
input VAR2;
input VAR5;
input VAR3;
supply1 VAR6;
supply0 VAR7;
endmodule | apache-2.0 |
secworks/blake2 | src/rtl/blake2_core.v | 20,927 | module MODULE1(
input wire clk,
input wire VAR6,
input wire VAR32,
input wire VAR59,
input wire VAR10,
input wire [7 : 0] VAR101,
input wire [7 : 0] VAR29,
input wire [1023 : 0] VAR67,
output wire ready,
output wire [511 : 0] VAR81,
output wire VAR96
);
localparam VAR23 = 4'hc;
localparam VAR75 = 128;
localparam VAR38 ... | bsd-2-clause |
codustry/cuckoo | cuckooExten/top_module.v | 1,071 | module MODULE1(
output [6:0] VAR4,
output VAR3,
VAR10,
input clk,
input VAR9
);
wire VAR14,VAR11,VAR18,VAR17,VAR8;
wire [3:0] VAR1,VAR2,VAR12;
assign VAR8 = ((VAR12==4'b0110)&&(!VAR9))? 0 :1;
assign VAR1 =(VAR14)? VAR2: VAR12;
assign VAR3 = (VAR14)? 1: 0;
assign VAR10 = (VAR14)? 0: 1;
VAR16 VAR16(VAR14,clk);
VAR6 VAR6(... | mit |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_LEDs.v | 2,232 | module MODULE1 (
address,
VAR6,
clk,
VAR2,
VAR5,
VAR8,
VAR9,
VAR3
)
;
output [ 7: 0] VAR9;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR2;
input VAR5;
input [ 31: 0] VAR8;
wire VAR4;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR9;
wire [ 7: 0] VAR1;
wire [ 31: 0] VAR3;
assign VAR4 = 1;
assign VAR1 ... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_ctrl.v | 31,685 | module MODULE1
(
clk, rst,
VAR148, VAR78, VAR147, VAR57, VAR122,
VAR18,
VAR101, VAR74, VAR81, VAR85, VAR119, VAR111, VAR42,
VAR90, VAR62, VAR7, VAR70,
VAR137, VAR16, VAR61, VAR45, VAR52, VAR144, VAR25,
VAR140, VAR97, VAR33, VAR17,
VAR22, VAR91, VAR26, VAR88, VAR3, VAR5,
VAR128, VAR138,
VAR13, VAR64, VAR120, VAR43, VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.pp.blackbox.v | 1,393 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR7,
VAR2,
VAR1 ,
VAR9
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.behavioral.pp.v | 1,891 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR5,
VAR11 ,
VAR4 ,
VAR8 ,
VAR7
);
output VAR12 ;
input VAR1 ;
input VAR5;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
wire VAR13 ;
wire VAR10;
not VAR2 (VAR13 , VAR5 );
and VAR3 (VAR10, VAR1, VAR13 );
VAR9 VAR6 (VAR12 , VAR10, VAR11, VAR4);
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/clk_193MHz/clk_193MHz_stub.v | 1,171 | module MODULE1(VAR1, MODULE1, VAR2)
;
input VAR1;
output MODULE1;
output VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a_1.v | 2,212 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR9 ,
VAR3,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR9 ;
input VAR3;
input VAR1;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR4 ,
VAR2,
VAR8,
VAR5,
VAR9
);... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/zynq_design_1_axi_bram_ctrl_0_bram_0_stub.v | 1,779 | module MODULE1(VAR4, VAR6, VAR14, VAR8, VAR10, VAR11, VAR12, VAR13, VAR5, VAR2,
VAR1, VAR7, VAR3, VAR9)
;
input VAR4;
input VAR6;
input VAR14;
input [3:0]VAR8;
input [31:0]VAR10;
input [31:0]VAR11;
output [31:0]VAR12;
input VAR13;
input VAR5;
input VAR2;
input [3:0]VAR1;
input [31:0]VAR7;
input [31:0]VAR3;
output [31:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.pp.blackbox.v | 1,458 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR2,
VAR10,
VAR5 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.behavioral.v | 1,938 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR13,
VAR12
);
output VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR13;
input VAR12;
wire VAR3 VAR5 ;
wire VAR6 ;
wire VAR2;
and VAR14 (VAR5 , VAR10, VAR4 );
nor VAR15 (VAR6 , VAR5, VAR1, VAR3 );
VAR7 VAR9 (VAR2, VAR6, VAR13, VAR12);
buf VAR11... | apache-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/message_fifo.v | 3,491 | module MODULE1(
input clk,
input rst,
input [7:0] VAR42,
input VAR27,
input VAR41,
output VAR9,
input VAR11,
output [7:0] VAR20,
output VAR7,
input VAR31,
output [7:0] VAR21
);
parameter VAR36=9;
parameter VAR17 = 0;
parameter VAR24 = (1 << VAR36);
wire VAR28;
reg VAR23;
reg VAR10;
reg VAR14;
reg VAR13;
reg VAR33;
reg ... | apache-2.0 |
mshr-h/fibonacci_verilog | rtl/fib.v | 1,528 | module MODULE1
parameter VAR11 = 7,
parameter VAR10 = 90
)
(
input wire VAR3,
input wire clk,
input wire req,
input wire [VAR11-1:0] VAR5,
output reg ack,
output reg [VAR10-1:0] VAR1
);
localparam
VAR14 = 2'b00,
VAR7 = 2'b01,
VAR9 = 2'b10,
VAR4 = 2'b11;
reg [1:0] state;
reg [VAR11-1:0] VAR2;
reg [VAR10-1:0] VAR6;
reg [... | mit |
ainterr/mips_processor | debounce.v | 1,717 | module MODULE1 (
input wire VAR6,
input wire VAR1,
input wire VAR8,
output reg VAR2);
parameter VAR5 = 25000000;
parameter VAR3 = 26;
reg [VAR3-1:0] VAR12;
reg [VAR3-1:0] VAR9;
reg VAR13;
reg VAR10;
reg VAR7;
reg VAR14;
wire VAR4;
wire VAR15;
wire VAR11;
assign VAR4 = VAR1;
assign VAR15 = (VAR12 == VAR5);
always @(pose... | mit |
megari/sd2snes | verilog/sd2snes_gsu/address.v | 5,524 | module MODULE1(
input VAR18,
input [7:0] VAR22, input [2:0] VAR16, input [23:0] VAR19, input [7:0] VAR4, input VAR25, output [23:0] VAR10, output VAR12, output VAR15, output VAR9, output VAR2, output VAR13, output VAR26, input [23:0] VAR1,
input [23:0] VAR27,
output VAR23,
output VAR8,
output VAR17,
output VAR5,
output... | gpl-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_topstatem.v | 3,061 | module MODULE1(VAR4, rst, VAR23, VAR14, VAR7, VAR17, VAR22, VAR18,
VAR24, VAR21, VAR20, VAR6, VAR15, VAR8, VAR1, VAR13, VAR3, VAR16);
input VAR4; input rst;
input VAR23;
input VAR14;
input VAR7;
input VAR17;
input VAR22;
input VAR18;
input VAR24;
input VAR21;
input VAR20;
output VAR6;
output VAR15;
output VAR8;
output ... | gpl-3.0 |
johan92/yafpgatetris | megafunctions/pll.v | 17,189 | module MODULE1 (
input wire VAR1, input wire rst, output wire VAR5, output wire VAR3 );
VAR2 VAR6 (
.VAR1 (VAR1), .rst (rst), .VAR5 (VAR5), .VAR3 (VAR3), .VAR4 () );
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.functional.v | 1,994 | module MODULE1 (
VAR2 ,
VAR13 ,
VAR15 ,
VAR5 ,
VAR8 ,
VAR10
);
output VAR2 ;
input VAR13 ;
input VAR15 ;
input VAR5 ;
input VAR8 ;
input VAR10;
wire VAR1 ;
wire VAR11 ;
wire VAR6;
not VAR16 (VAR11 , VAR10 );
VAR4 VAR12 (VAR6, VAR15, VAR5, VAR8 );
VAR14 VAR7 VAR3 (VAR1 , VAR6, VAR13, VAR11);
buf VAR9 (VAR2 , VAR1 );
end... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/dbg_if/dbg_cpu.v | 26,416 | module MODULE1(
VAR128,
VAR5,
VAR28,
VAR41,
VAR14,
VAR105,
VAR118,
VAR15,
VAR9,
VAR33,
VAR110,
VAR47,
VAR21, VAR20, VAR25, VAR22, VAR60,
VAR88,
VAR100, VAR71, VAR17
);
input VAR128;
input VAR5;
output VAR28;
input VAR41;
input VAR14;
input VAR105;
input VAR118;
input VAR15;
output VAR9;
output VAR33;
input VAR110;
inpu... | mit |
julioamerico/prj_crc_ip | src/SoC/hdl/host_interface.v | 3,918 | module MODULE1
(
output [31:0] VAR3,
output VAR36,
output VAR10,
output [31:0] VAR8,
output [ 1:0] VAR48,
output [ 1:0] VAR13,
output [ 1:0] VAR20,
output VAR58,
output VAR57,
output VAR51,
output VAR6,
output VAR15,
output VAR54,
input [31:0] VAR30,
input [31:0] VAR37,
input [ 2:0] VAR35,
input [ 1:0] VAR14,
input VAR... | gpl-3.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/full_jacobian/full_mat/t_block/sincos/mult_21_coeff_83443/mult_21_coeff_83443.v | 2,242 | module MODULE1 (
VAR16,
VAR13,
VAR21,
VAR18);
input VAR16;
input VAR13;
input [20:0] VAR21;
output [41:0] VAR18;
wire [41:0] VAR9;
wire [20:0] VAR20 = 21'd83443;
wire [41:0] VAR18 = VAR9[41:0];
VAR1 VAR11 (
.VAR13 (VAR13),
.VAR4 (VAR20),
.VAR16 (VAR16),
.VAR21 (VAR21),
.VAR18 (VAR9),
.VAR22 (1'b0),
.sum (1'b0));
VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.functional.v | 2,089 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR7
);
output VAR13 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR7;
wire VAR18 ;
wire VAR8 ;
wire VAR14 ;
wire VAR6;
not VAR12 (VAR8 , VAR7 );
not VAR15 (VAR14 , VAR2 );
VAR11 VAR5 (VAR6, VAR9, VAR4, VAR1 );
VAR10 VAR3 VAR17 (VAR18 , VAR6, VAR14, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3_4.v | 2,199 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR10,
VAR2,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR10;
input VAR2;
input VAR8 ;
input VAR7 ;
VAR9 VAR5 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_avalon_st_idle_inserter.v | 2,037 | module MODULE1 (
input clk,
input VAR10,
output reg VAR8,
input VAR7,
input [7: 0] VAR6,
input VAR9,
output reg VAR1,
output reg [7: 0] VAR3
);
reg VAR2;
wire VAR5, VAR4;
assign VAR4 = (VAR6 == 8'h4a);
assign VAR5 = (VAR6 == 8'h4d);
always @(posedge clk or negedge VAR10) begin
if (!VAR10) begin
VAR2 <= 0;
end else begi... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_cmp.v | 2,736 | module MODULE1(
VAR10, VAR4, VAR8, VAR13,
VAR9, VAR12, VAR6, VAR5, VAR3, VAR14, VAR11, VAR7
);
input VAR7; input VAR11; input VAR14; input VAR3; input VAR5; input VAR6; input VAR12; input VAR9;
output VAR13; output VAR8; output VAR4; output VAR10;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR13(VAR13),
.VAR4(VAR4),
.VAR10 (VAR10),
.VA... | gpl-2.0 |
aneez/nexys-fpga-exp | vSevenSegmentDisplay/ssg_display.v | 1,570 | module MODULE1(
input clk,
input VAR12,
output [7:0] VAR22,
output [3:0] VAR23
);
wire VAR15;
assign VAR15 = 1;
wire VAR20,VAR7;
VAR3 #(.VAR16(250000)) VAR5 (
.enable(VAR20),
.VAR4(clk),
.VAR12(VAR12));
VAR3 #(.VAR16(6000000)) VAR13 (
.enable(VAR7),
.VAR4(clk),
.VAR12(VAR12));
wire [15:0] VAR8;
VAR9 VAR14(.enable(VAR7)... | gpl-2.0 |
NickShaffner/rhea | rhea/cores/usbext/fpgalink/comm_fpga_fx2_v1.v | 9,588 | module
MODULE1(
input wire VAR8, input wire VAR26,
output reg VAR35, input wire [7:0] VAR3,
output wire [7:0] VAR25,
output wire VAR14,
output wire VAR6, input wire VAR24,
output wire VAR12, input wire VAR21, output reg VAR15,
output wire [6:0] VAR19,
output wire [7:0] VAR37, output reg VAR33, input wire VAR30,
input w... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_gt_es.v | 27,864 | module MODULE1 (
VAR60,
VAR46,
VAR99,
VAR107,
VAR141,
VAR93,
VAR30,
VAR104,
VAR52,
VAR31,
VAR11,
VAR58,
VAR129,
VAR25,
VAR36,
VAR89,
VAR42,
VAR39,
VAR45,
VAR130,
VAR13,
VAR3,
VAR88,
VAR101,
VAR37,
VAR121,
VAR85,
VAR116,
VAR84,
VAR82,
VAR79,
VAR96,
VAR134,
VAR71,
VAR18,
VAR7,
VAR86,
VAR114,
VAR74,
VAR22,
VAR8,
VAR105,
V... | mit |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_tx_pipeline.v | 22,383 | module MODULE1 #(
parameter VAR54 = 128, parameter VAR45 = "VAR27", parameter VAR8 = 1,
parameter VAR49 = (VAR54 == 128) ? 2 : 1, parameter VAR36 = VAR54 / 8 ) (
input [VAR54-1:0] VAR52, input VAR58, output VAR47, input [VAR36-1:0] VAR16, input VAR23, input [3:0] VAR4,
output [VAR54-1:0] VAR7, output VAR18, output VAR1... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_phy_dqs_iob.v | 8,480 | module MODULE1 #
(
parameter VAR67 = 1,
parameter VAR23 = "VAR22",
parameter VAR11 = "VAR40"
)
(
input VAR79,
input VAR41,
input VAR70,
input VAR16,
input VAR76,
input VAR51,
input VAR48,
input VAR71,
input VAR29,
input VAR38,
input VAR53,
input VAR7,
inout VAR12,
inout VAR65,
output VAR74,
output VAR28
);
wire VAR19;
... | mit |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/padder1.v | 1,134 | module MODULE1(in, VAR1, out);
input [31:0] in;
input [1:0] VAR1;
output reg [31:0] out;
always @ (*)
case (VAR1)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/control_unit.v | 19,436 | module MODULE1(
input wire clk, input wire reset,
output reg VAR72,
output reg VAR34,
output wire [25:0] VAR14,
output wire [31:0] VAR82,
input wire [31:0] VAR64,
input wire VAR39,
output reg [24:0] VAR46,
output reg [31:0] VAR73,
output reg [1:0] VAR57,
output reg [2:0] VAR9,
output wire [31:0] VAR92,
output wire [31:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.v | 2,362 | module MODULE1 (
VAR2 ,
VAR6,
VAR5 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR3 ,
VAR10
);
output VAR2 ;
input VAR6;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR10 ;
VAR8 VAR7 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/state_tx.v | 3,935 | module MODULE1
(input VAR44, input [15:0] VAR3, input [15:0] VAR15,
input [47:0] VAR39, input VAR19,
input [31:0] VAR16, input [31:0] VAR22, input [31:0] VAR5,
input [15:0] VAR17, input [2:0] VAR26, input [31:0] VAR56,
input [31:0] VAR6, input [31:0] VAR42,
input [31:0] VAR4, input [31:0] VAR8,
input [31:0] VAR21, inpu... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_axis_inf_rx.v | 6,724 | module MODULE1 (
clk,
rst,
valid,
VAR15,
VAR9,
VAR17,
VAR4,
VAR28,
VAR25);
parameter VAR12 = 16;
localparam VAR16 = VAR12 - 1;
input clk;
input rst;
input valid;
input VAR15;
input [VAR16:0] VAR9;
output VAR17;
output VAR4;
output [VAR16:0] VAR28;
input VAR25;
reg [ 2:0] VAR27 = 'd0;
reg VAR14 = 'd0;
reg [VAR16:0] VAR2... | lgpl-3.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_txfifo.v | 2,460 | module MODULE1(
input VAR6,
input VAR10,
input VAR17,
input [7:0] VAR15,
output VAR18,
input VAR4,
output reg VAR9,
input VAR23,
output reg VAR20,
output reg [3:0] VAR29
);
wire [7:0] VAR1;
wire VAR34;
reg VAR21;
reg VAR22;
always @(posedge VAR6) begin
VAR22 <= VAR34;
VAR9 <= VAR22;
end
VAR31 #(
.VAR25(8),
.VAR2(7)
) V... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_m00_data_fifo_0/synth/OpenSSD2_m00_data_fifo_0.v | 15,935 | module MODULE1 (
VAR2,
VAR80,
VAR111,
VAR44,
VAR112,
VAR101,
VAR93,
VAR70,
VAR10,
VAR88,
VAR24,
VAR114,
VAR86,
VAR46,
VAR59,
VAR69,
VAR6,
VAR90,
VAR32,
VAR17,
VAR98,
VAR4,
VAR91,
VAR27,
VAR11,
VAR75,
VAR78,
VAR77,
VAR73,
VAR8,
VAR7,
VAR29,
VAR83,
VAR87,
VAR31,
VAR58,
VAR66,
VAR49,
VAR76,
VAR30,
VAR40,
VAR54,
VAR43,
VAR... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/07e9351aee22473d/ip_design_axi_gpio_1_0_stub.v | 2,329 | module MODULE1(VAR7, VAR1, VAR11,
VAR13, VAR21, VAR10, VAR8, VAR20, VAR5,
VAR4, VAR15, VAR16, VAR2, VAR14, VAR9,
VAR17, VAR19, VAR6, VAR12, VAR3, VAR18)
;
input VAR7;
input VAR1;
input [8:0]VAR11;
input VAR13;
output VAR21;
input [31:0]VAR10;
input [3:0]VAR8;
input VAR20;
output VAR5;
output [1:0]VAR4;
output VAR15;
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.pp.blackbox.v | 1,223 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5,
VAR3,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/tart_dual_dcm.v | 8,527 | module MODULE1
(
input VAR43, input VAR34,
output VAR19, output VAR5, output VAR21, output VAR40, output VAR13, output VAR18 );
wire [7:0] VAR45;
wire VAR52, VAR14, VAR4, VAR8, VAR15;
wire VAR49, VAR31, VAR3;
wire VAR11;
assign VAR13 = VAR50 && VAR42;
assign VAR53 = 1'b1;
VAR36
) VAR44
( .VAR30(VAR43),
.VAR51(VAR52)
);... | lgpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/symmetric_mem_core.v | 4,901 | module MODULE1 #(
parameter VAR10 = 32,
parameter VAR9 = 12
)(
input wire VAR7,
input wire VAR13,
input wire VAR11,
input wire VAR17,
input wire [VAR9-1:0] VAR14,
input wire [VAR9-1:0] VAR3,
input wire [VAR10-1:0] VAR1,
input wire [VAR10-1:0] VAR15,
output reg [VAR10-1:0] VAR12,
output reg [VAR10-1:0] VAR16
);
reg [VAR... | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/ibex/ibex_fetch_fifo.v | 5,680 | module MODULE1 (
VAR42,
VAR28,
VAR1,
VAR8,
VAR19,
VAR39,
VAR31,
VAR24,
VAR17,
VAR43,
VAR5,
VAR15,
VAR3
);
parameter [31:0] VAR38 = 2;
input wire VAR42;
input wire VAR28;
input wire VAR1;
input wire VAR8;
output wire VAR19;
input wire [31:0] VAR39;
input wire [31:0] VAR31;
input wire VAR24;
output reg VAR17;
input wire ... | isc |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_gen_sora.v | 13,828 | module MODULE1(
input clk,
input rst,
input VAR30,
output VAR45,
input [63:0] VAR2,
input [31:0] VAR24,
input [23:0] VAR65,
input [7:0] VAR70,
input [63:0] VAR61, input VAR22,
input [63:0] VAR12,
input [31:0] VAR37,
input VAR63,
input [63:0] VAR40,
input [31:0] VAR31,
input VAR74,
input [63:0] VAR58,
input [31:0] VAR50... | bsd-2-clause |
zhaoyang10/mips-cpu | verilog/cpu.v | 10,564 | module MODULE1(
input wire clk);
parameter VAR4 = 20; parameter VAR3 = "VAR2.VAR1"; | gpl-3.0 |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/delay_5.v | 4,513 | module MODULE1 (
VAR14,
VAR3,
VAR4,
VAR16,
VAR17);
input VAR14;
input VAR3;
input [7:0] VAR4;
output [7:0] VAR16;
output [39:0] VAR17;
tri1 VAR14;
wire [7:0] VAR6;
wire [39:0] VAR18;
wire [7:0] VAR16 = VAR6[7:0];
wire [39:0] VAR17 = VAR18[39:0];
VAR2 VAR20 (
.VAR3 (VAR3),
.VAR14 (VAR14),
.VAR4 (VAR4),
.VAR16 (VAR6),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.blackbox.v | 1,246 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
output VAR2;
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/main.v | 13,379 | module MODULE1(
VAR198, VAR186,
VAR75, VAR81,
VAR51,
VAR6, VAR91,
VAR41, VAR128, VAR56, VAR71, VAR188, VAR144, VAR162, VAR107, VAR120, VAR115,
VAR37, VAR30, VAR54, VAR79, VAR145, VAR168, VAR204, VAR11, VAR102, VAR172, VAR73, VAR141,
VAR106, VAR142, VAR193, VAR31, VAR169, VAR116, VAR189, VAR33, VAR192, VAR138, VAR196, V... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaD_release/ports/ports.v | 12,180 | module MODULE1(
din, dout, VAR99, VAR46,
VAR97,VAR37,VAR62,VAR6,
VAR104, VAR40, VAR18,
VAR77, VAR27,
VAR58, VAR3,
VAR44, VAR76,
VAR2, VAR101,
VAR38, VAR5,
VAR64, VAR63,
VAR54, VAR73,
VAR92, VAR72, VAR91, VAR90,
VAR15, VAR88,
VAR98,
VAR53,
VAR25, VAR10,
VAR43,
VAR86,
VAR82,
VAR89,
VAR103,
VAR106, VAR45,
VAR28,
VAR79,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.behavioral.pp.v | 2,072 | module MODULE1 (
VAR12,
VAR6,
VAR13 ,
VAR4,
VAR7,
VAR9 ,
VAR15
);
input VAR12;
input VAR6;
output VAR13 ;
input VAR4;
input VAR7;
input VAR9 ;
input VAR15 ;
wire VAR15 VAR11 ;
wire VAR15 VAR2 ;
wire VAR17 ;
wire VAR14;
nand VAR5 (VAR11 , VAR7, VAR4 );
or VAR1 (VAR2 , VAR15, VAR9 );
and VAR16 (VAR17 , VAR11, VAR2 );
VAR... | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_timer_0_0/system_axi_timer_0_0_stub.v | 2,477 | module MODULE1(VAR12, VAR13, VAR23,
VAR22, VAR10, interrupt, VAR15, VAR21, VAR17, VAR24, VAR18,
VAR3, VAR7, VAR2, VAR8, VAR6, VAR16,
VAR25, VAR5, VAR11, VAR19, VAR4, VAR1,
VAR9, VAR20, VAR14)
;
input VAR12;
input VAR13;
output VAR23;
output VAR22;
output VAR10;
output interrupt;
input VAR15;
input VAR21;
input VAR17;
i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.functional.v | 1,938 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR9 ,
VAR16 ,
VAR15 ,
VAR6
);
output VAR14 ;
input VAR1 ;
input VAR9 ;
input VAR16 ;
input VAR15 ;
input VAR6;
wire VAR11 ;
wire VAR13 ;
wire VAR4;
not VAR5 (VAR13 , VAR6 );
VAR8 VAR3 (VAR4, VAR9, VAR16, VAR15 );
VAR2 VAR7 VAR10 (VAR11 , VAR4, VAR1, VAR13);
buf VAR12 (VAR14 , VAR11 );
e... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/ddr_io.v | 2,748 | module MODULE1 (
VAR24,
VAR20,
VAR11,
VAR12,
VAR13,
VAR18,
VAR26,
MODULE1
);
input VAR24;
input VAR20;
input VAR11;
input VAR12;
input VAR13;
input [1:0] VAR18;
output [1:0] VAR26;
inout MODULE1;
wire VAR1;
VAR7 VAR15 (
.VAR16 (VAR20),
.VAR21 (VAR24),
.VAR25 (1'b1),
.VAR2 (VAR18 [0]),
.VAR22 (VAR18 [1]),
.VAR14 (1'b0),... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/fetch_ctrl.v | 48,473 | module MODULE1 (
clk ,
VAR110 ,
VAR103 ,
VAR43 ,
VAR53 ,
VAR89 ,
VAR9 ,
VAR79 ,
VAR98 ,
VAR14 ,
VAR35 ,
VAR1 ,
VAR130 ,
VAR96 ,
VAR47 ,
VAR93 ,
VAR52 ,
VAR44 ,
VAR141 ,
VAR64 ,
VAR124 ,
VAR115 ,
VAR33 ,
VAR154 ,
VAR111 ,
VAR61 ,
VAR72 ,
VAR29 ,
VAR150 ,
VAR42 ,
VAR60 ,
VAR31 ,
VAR91 ,
VAR94 ,
VAR78 ,
VAR51 ,
VAR99 ,
VA... | gpl-3.0 |
asicguy/gplgpu | hdl/math/flt_add_sub_comb.v | 7,633 | module MODULE1
(
input VAR40,
input [31:0] VAR56,
input [31:0] VAR32,
output reg [31:0] VAR43
);
reg [24:0] VAR45; reg [24:0] VAR58; reg VAR9;
reg [7:0] VAR18; reg [24:0] VAR16; reg [24:0] VAR10; reg [24:0] VAR52; reg VAR35; reg [24:0] VAR27; reg [31:0] VAR2;
reg [31:0] VAR54;
reg VAR14;
reg VAR25;
reg VAR19;
reg [24:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn.functional.v | 2,043 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR12 ,
VAR16 ,
VAR11 ,
VAR17
);
output VAR5 ;
output VAR6 ;
input VAR12 ;
input VAR16 ;
input VAR11 ;
input VAR17;
wire VAR10;
wire VAR14 ;
wire VAR4 ;
wire VAR18;
not VAR7 (VAR10 , VAR17 );
not VAR1 (VAR14 , VAR11 );
not VAR15 (VAR4 , VAR16 );
VAR13 VAR3 VAR8 (VAR18 , VAR14, VAR10, VAR4... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/NTNU FPU/low-cost-fpu-src/exp_register_file.v | 2,106 | module MODULE1(VAR15, VAR3, VAR2, VAR4, VAR9, VAR5,
VAR17, VAR12, VAR10, VAR11);
parameter VAR13 = 'd9;
parameter VAR16 = 9'd0; parameter VAR8 = 9'd1; parameter VAR6 = 9'd31; parameter VAR7 = 9'd158; parameter VAR1 = 9'd127; parameter VAR19 = 9'd511;
input VAR15, VAR3;
input VAR2, VAR4;
input [VAR13-1:0] VAR9, VAR5;
in... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_nonsynth_mem_1rw_sync_assoc.v | 1,100 | module MODULE1
, parameter VAR6(VAR1)
)
(
input VAR13
, input VAR5
, input [VAR7-1:0] VAR11
, input [VAR1-1:0] VAR3
, input VAR10
, input VAR12
, output logic [VAR7-1:0] VAR4
);
wire VAR8 = VAR5;
logic [VAR7-1:0] VAR2 [longint];
logic [VAR7-1:0] VAR2 [*];
VAR9 @ (posedge VAR13) begin
if (~VAR5 & VAR10 & VAR12) begin
VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.behavioral.pp.v | 1,823 | module MODULE1 (
VAR7,
VAR9,
VAR12 ,
VAR1 ,
VAR5
);
input VAR7;
input VAR9;
output VAR12 ;
input VAR1 ;
input VAR5 ;
wire VAR12 VAR13 ;
wire VAR8 ;
wire VAR4;
not VAR3 (VAR13 , VAR5 );
or VAR2 (VAR8 , VAR13, VAR1 );
VAR6 VAR11 (VAR4, VAR8, VAR7, VAR9);
buf VAR10 (VAR12 , VAR4 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/tlm_rx_data_snk_pwr_mgmt.v | 7,958 | module MODULE1
(
input VAR16,
input VAR1,
output reg VAR15, output reg VAR5, output reg VAR7, output reg [9:0] VAR13, output reg VAR9,
input VAR20, input [7:0] VAR24, input [9:0] VAR14, input VAR8, input VAR12, input VAR18 );
localparam VAR22 = 8'b00010100;
localparam VAR3 = 8'b00011001;
localparam VAR2 = 8'b01010000;
... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/udp/udp_wrapper.v | 4,723 | module MODULE1
(input clk, input reset, input VAR9,
input VAR31, input [7:0] VAR35, input [31:0] VAR55,
input [18:0] VAR42, input VAR22, output VAR16,
output [18:0] VAR59, output VAR41, input VAR48,
output [35:0] VAR45, output VAR44, input VAR5,
input [35:0] VAR1, input VAR28, output VAR37,
output [31:0] VAR30
);
wire ... | gpl-2.0 |
mamijaz/RISC-V | src/riscv_data_cache/DATA_CACHE.v | 7,568 | module MODULE1 #(
parameter VAR41 = 32 ,
parameter VAR19 = 32 ,
parameter VAR9 = 3 ,
parameter VAR35 = 2 ,
parameter VAR17 = 32 ,
parameter VAR14 = 3'b000 ,
parameter VAR18 = 3'b010 ,
parameter VAR34 = 3'b011 ,
parameter VAR16 = 3'b100 ,
parameter VAR6 = 3'b101 ,
parameter VAR5 = 3'b110 ,
parameter VAR8 = 2'b00 ,
param... | bsd-2-clause |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_MSG.v | 16,138 | module MODULE2(VAR1, VAR26, VAR16, VAR24, VAR40, VAR35, VAR36, VAR34, VAR17);
input VAR1, VAR26;
input [7:0] VAR16;
output [39:0] VAR24;
output VAR34, VAR17;
output VAR35, VAR36;
input VAR40;
wire [7:0] VAR37;
wire [39:0] VAR4;
MODULE3 MODULE3 (
.VAR1(VAR1),
.VAR26(VAR26),
.VAR16(VAR16),
.VAR40(VAR40),
.VAR6(VAR36),
.V... | bsd-2-clause |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_us_2/synth/dma_loopback_auto_us_2.v | 14,599 | module MODULE1 (
VAR70,
VAR47,
VAR96,
VAR27,
VAR92,
VAR42,
VAR52,
VAR83,
VAR73,
VAR64,
VAR91,
VAR95,
VAR41,
VAR19,
VAR14,
VAR79,
VAR39,
VAR38,
VAR88,
VAR49,
VAR82,
VAR58,
VAR17,
VAR68,
VAR56,
VAR55,
VAR85,
VAR11,
VAR51,
VAR74,
VAR75,
VAR90,
VAR32,
VAR23,
VAR4,
VAR59,
VAR3,
VAR53,
VAR9,
VAR72,
VAR21,
VAR81,
VAR15,
VAR77... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi.pp.symbol.v | 1,396 | module MODULE1 (
input VAR9 ,
input VAR5 ,
input VAR2 ,
input VAR3 ,
input VAR4 ,
output VAR8 ,
input VAR7 ,
input VAR6,
input VAR1,
input VAR10
);
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/gowin/arith_map.v | 2,088 | module MODULE1(
module 80gw1nalu(VAR14, VAR18, VAR8, VAR30, VAR15, VAR27, VAR16);
parameter VAR19 = 0;
parameter VAR11 = 0;
parameter VAR3 = 1;
parameter VAR24 = 1;
parameter VAR25 = 1;
input [VAR3-1:0] VAR14;
input [VAR24-1:0] VAR18;
output [VAR25-1:0] VAR15, VAR27;
input VAR8, VAR30;
output [VAR25-1:0] VAR16;
wire VA... | isc |
anderson1008/NOCulator | hring/hw/buffered/src/c_nor_nto1.v | 2,270 | module MODULE1
(VAR2, VAR5);
parameter VAR1 = 2;
parameter VAR4 = 1;
input [0:VAR4*VAR1-1] VAR2;
output [0:VAR4-1] VAR5;
wire [0:VAR4-1] VAR5;
generate
genvar VAR6;
for(VAR6 = 0; VAR6 < VAR4; VAR6 = VAR6 + 1)
begin:VAR3
wire [0:VAR1-1] VAR7;
genvar VAR8;
for(VAR8 = 0; VAR8 < VAR1; VAR8 = VAR8 + 1)
begin:VAR9
assign VAR... | mit |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/picouser/spinner.v | 3,683 | module MODULE1
(
input wire VAR3,
input wire VAR2,
input wire clk,
output reg VAR6,
output reg VAR1
);
reg VAR9;
reg VAR7;
reg VAR5;
reg VAR8;
always @(posedge clk)
begin : VAR4
case ({VAR2, VAR3})
0: VAR9 <= 1'b0;
1: VAR7 <= 1'b0;
2: VAR7 <= 1'b1;
3: VAR9 <= 1'b1;
endcase
VAR5 <= VAR9;
VAR8 <= VAR7;
VAR6 <= VAR8 && !V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp.functional.v | 2,101 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR16 ,
VAR10 ,
VAR9 ,
VAR15 ,
VAR8
);
output VAR12 ;
output VAR6 ;
input VAR16 ;
input VAR10 ;
input VAR9 ;
input VAR15 ;
input VAR8;
wire VAR2 ;
wire VAR5 ;
wire VAR11;
not VAR13 (VAR5 , VAR8 );
VAR14 VAR7 (VAR11, VAR10, VAR9, VAR15 );
VAR17 VAR1 VAR3 (VAR2 , VAR11, VAR16, VAR5);
buf V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.functional.v | 1,374 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR1;
buf VAR4 (VAR1, VAR2 );
buf VAR3 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.behavioral.v | 1,607 | module MODULE1 (
VAR3 ,
VAR5,
VAR14,
VAR6,
VAR7
);
output VAR3 ;
input VAR5;
input VAR14;
input VAR6;
input VAR7;
supply1 VAR2;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR4 ;
wire VAR1 ;
wire VAR16 ;
wire VAR10;
or VAR13 (VAR1 , VAR14, VAR5 );
or VAR12 (VAR16 , VAR7, VAR6 );
and VAR9 (VAR10, VAR1, VAR16);
buf VAR15 (VAR3... | apache-2.0 |
laoreja/MineSweeperM | code/counter_26bit.v | 1,128 | module MODULE1(clk, reset, VAR1, VAR5);
parameter VAR3=26;
input clk;
input reset;
output VAR1;
output wire [VAR3-1:0] VAR5;
reg [VAR3-1:0] VAR4;
reg VAR2;
wire clk; | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/join_fadd.v | 1,421 | module MODULE1(
input clk,
input reset,
input [7:0] VAR15,
input VAR12,
output VAR8,
input [7:0] VAR22,
input VAR16,
output VAR19,
output [7:0] sum,
output VAR14,
input VAR1
);
logic [7:0] VAR24;
VAR21 begin
VAR24 = VAR15 + VAR22;
end
logic VAR9;
logic VAR4;
VAR21 begin
VAR9 = VAR12 && VAR16;
end
VAR21 begin
VAR19 = VA... | apache-2.0 |
SymbiFlow/fpga-tool-perf | src/bram-n3/bram_n3.v | 1,389 | module MODULE1
(
input wire clk,
output wire VAR11,
input wire VAR5,
input wire [15:0] VAR7,
output wire [15:0] VAR6
);
reg rst = 1;
reg VAR4 = 1;
reg VAR1 = 1;
reg VAR9 = 1;
assign VAR6[0] = rst;
assign VAR6[13:1] = VAR7[13:1];
assign VAR6[14] = ^VAR7;
assign VAR6[15] = VAR5;
always @(posedge clk) begin
VAR9 <= 0;
VAR... | isc |
tmolteno/TART | hardware/FPGA/tart_spi/bench/xilinx/IDDR2.v | 3,068 | module MODULE1
parameter VAR19 = "VAR20",
parameter VAR1 = "VAR17",
parameter VAR4 = 0,
parameter VAR3 = 0,
parameter VAR21 = 3) (
input VAR12,
input VAR18,
input VAR9,
input VAR6,
input VAR2,
input VAR22,
output VAR26,
output VAR8
);
parameter VAR5 = VAR19 == "VAR12";
parameter VAR16 = VAR19 == "VAR18";
reg VAR10, VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR7 ,
input VAR5 ,
output VAR3 ,
input VAR4 ,
input VAR2,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.