repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fa/sky130_fd_sc_hs__fa_1.v | 2,151 | module MODULE2 (
VAR8,
VAR2 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR5,
VAR7
);
output VAR8;
output VAR2 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR5;
input VAR7;
VAR6 VAR4 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8,
VAR2 ,
VAR1 ,
VAR9 ,
VAR3
)... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_qpll_reset.v | 13,930 | module MODULE1 #
(
parameter VAR46 = "VAR45", parameter VAR24 = "VAR8", parameter VAR7 = 1, parameter VAR39 = 1
)
(
input VAR5,
input VAR48,
input VAR16,
input [VAR7-1:0] VAR32,
input [(VAR7-1)>>2:0]VAR40,
input [(VAR7-1)>>2:0]VAR33,
input [ 1:0] VAR28,
input [VAR7-1:0] VAR13,
input [VAR7-1:0] VAR22,
output VAR52,
outp... | mit |
olajep/oh | src/common/hdl/oh_edgedetect.v | 1,645 | module MODULE1 (
out,
clk, VAR17, in
);
parameter VAR8 = 32;
input clk; input [1:0] VAR17; input [VAR8-1:0] in; output [VAR8-1:0] out;
reg [VAR8-1:0] VAR16;
wire [VAR8-1:0] VAR15;
wire [VAR8-1:0] VAR11;
wire [VAR8-1:0] VAR12;
wire [VAR8-1:0] VAR13;
always @ (posedge clk)
VAR16[VAR8-1:0] <= in[VAR8-1:0];
assign VAR15[VA... | mit |
scalable-networks/ext | uhd/fpga/usrp2/gpif/slave_fifo.v | 9,272 | module MODULE1
parameter VAR7 = 256,
parameter VAR31 = 32,
parameter VAR73 = 9,
parameter VAR37 = 9,
parameter VAR26 = 9,
parameter VAR34 = 9
)
( input VAR38, input VAR77,
inout [15:0] VAR61,
input [3:0] VAR14,
output reg VAR12, output reg VAR40, output reg VAR5, output reg VAR44, output reg [1:0] VAR70,
input VAR30, i... | gpl-2.0 |
cathalmccabe/PYNQ | boards/ip/boolean_generator_1.1/src/boolean_lut.v | 1,401 | module MODULE1(
input wire clk,
input wire VAR9,
input wire [4:0] VAR1,
input wire VAR16,
output wire VAR10
);
VAR15 #(
.VAR4(32'h80000000) ) VAR3 (
.VAR14(), .VAR11(VAR10), .VAR16(VAR16), .VAR6(VAR9), .VAR8(clk), .VAR7(VAR1[0]), .VAR2(VAR1[1]), .VAR5(VAR1[2]), .VAR13(VAR1[3]), .VAR12(VAR1[4]) );
endmodule | bsd-3-clause |
DougFirErickson/parallella-hw | fpga/old/emon/hdl/emon_counter.v | 4,191 | module MODULE1 (
VAR1, VAR2,
clk, reset, VAR4, VAR9, VAR3, VAR6
);
parameter VAR8 = 6;
parameter VAR5 = 32;
input clk;
input reset;
input [15:0] VAR4; input [3:0] VAR9;
input VAR3;
input [VAR5-1:0] VAR6;
output [VAR5-1:0] VAR1; output VAR2;
reg [VAR5-1:0] VAR1;
reg VAR7;
always @(posedge clk)
VAR7 <= VAR4[VAR9[3:0]];
a... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_SLVT_FF_210930.v | 242,236 | module MODULE1 (VAR5, VAR7, VAR2, VAR10, VAR8, VAR3);
output VAR5;
input VAR7, VAR2, VAR10, VAR8, VAR3;
wire VAR11, VAR4, VAR1;
wire VAR9, VAR12, VAR13;
wire VAR6;
not (VAR12, VAR3);
not (VAR9, VAR8);
not (VAR1, VAR10);
and (VAR13, VAR1, VAR9);
not (VAR4, VAR2);
not (VAR11, VAR7);
and (VAR6, VAR11, VAR4, VAR9);
or (VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4_4.v | 2,247 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR1,
VAR7,
VAR6 ,
VAR10
);
output VAR11 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR10 ;
VAR4 VAR5 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.behavioral.pp.v | 2,186 | module MODULE1 (
VAR20 ,
VAR13 ,
VAR3 ,
VAR14 ,
VAR11,
VAR15,
VAR8 ,
VAR16
);
output VAR20 ;
input VAR13 ;
input VAR3 ;
input VAR14 ;
input VAR11;
input VAR15;
input VAR8 ;
input VAR16 ;
wire VAR10 ;
wire VAR17 ;
wire VAR1 ;
wire VAR12 ;
wire VAR4;
or VAR9 (VAR10 , VAR3, VAR13 );
and VAR5 (VAR17 , VAR10, VAR14 );
and V... | apache-2.0 |
cr88192/bgbtech_bjx1core | srvcore/GpReg_0.v | 2,416 | module MODULE1(
clk,
VAR4,
VAR18,
VAR9,
VAR1,
VAR17,
VAR14,
VAR2,
VAR7,
VAR5,
VAR16,
VAR6,
VAR22,
VAR8,
VAR15,
VAR12,
VAR20,
VAR19,
VAR11
);
input clk;
input VAR4; input VAR2; input VAR8;
input VAR18; input VAR7; input VAR15;
input VAR9; input VAR5; input VAR12;
input[6:0] VAR1;
input[6:0] VAR16;
input[6:0] VAR20;
inou... | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_controller_phy.v | 14,691 | module MODULE1 (
VAR138,
VAR97,
VAR57,
VAR71,
VAR52,
VAR8,
VAR107,
VAR4,
VAR95,
VAR48,
VAR20,
VAR50,
VAR38,
VAR100,
VAR19,
VAR115,
VAR69,
VAR88,
VAR54,
VAR25,
VAR6,
VAR131,
VAR12,
VAR132,
VAR149,
VAR136,
VAR114,
VAR22,
VAR63,
VAR124,
VAR78,
VAR76,
VAR96,
VAR150,
VAR122,
VAR5,
VAR143,
VAR80,
VAR148,
VAR84,
VAR59,
VAR74,... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,686 | module MODULE1 (
VAR27,
VAR28,
clk,
VAR53,
VAR41,
VAR33,
VAR45,
VAR37,
VAR24,
VAR13,
VAR50,
VAR44,
VAR8,
VAR15,
VAR54,
VAR47,
VAR31,
VAR16,
VAR4,
VAR38,
VAR6,
VAR2,
VAR9,
VAR26,
VAR51,
VAR3,
VAR46,
VAR22,
VAR57,
VAR29,
VAR48,
VAR39,
VAR14,
VAR52,
VAR23,
VAR20
)
;
output [ 37: 0] VAR6;
output VAR2;
output VAR9;
output V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf_6.v | 2,009 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR4,
VAR2,
VAR5 ,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR7 ;
VAR1 VAR6 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR8
);
output VAR3;
input VAR8;
supply1 VAR4;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b.functional.pp.v | 2,008 | module MODULE1 (
VAR14 ,
VAR17 ,
VAR15 ,
VAR7 ,
VAR8 ,
VAR10,
VAR2,
VAR12 ,
VAR6
);
output VAR14 ;
input VAR17 ;
input VAR15 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR2;
input VAR12 ;
input VAR6 ;
wire VAR16 ;
wire VAR5 ;
wire VAR4;
not VAR1 (VAR16 , VAR17 );
and VAR11 (VAR5 , VAR16, VAR15, VAR7, VAR8 );
VAR9 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_18.v | 1,916 | module MODULE2 (
VAR2,
VAR1,
VAR6 ,
VAR3
);
input VAR2;
input VAR1;
input VAR6 ;
input VAR3 ;
VAR5 VAR4 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
VAR5 VAR4 ();
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/predict.v | 9,643 | module MODULE1
(
input VAR16,
input VAR8,
input [31:0] VAR21, input VAR2, input VAR11,
input [31:0] VAR17,
input [31:0] VAR3,
input VAR18, input VAR7,
input [31:0] VAR6, input [31:0] VAR19, input VAR5,
output reg VAR9, output reg VAR13, output reg [31:0] VAR1,
output reg VAR12,
output reg VAR15
);
parameter VAR4 = 2 ;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v | 2,036 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR8,
VAR2,
VAR4 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR8;
input VAR2;
input VAR4 ;
input VAR5 ;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/sparc_tlu_dec64.v | 1,545 | module MODULE1(
out,
in
);
input [5:0] in;
output [63:0] out;
wire [5:0] in;
reg [63:0] out;
integer VAR1;
always @ (in)
begin
for (VAR1=0;VAR1<64;VAR1=VAR1+1)
begin
if (VAR1[5:0] == in[5:0])
out[VAR1] = 1'b1;
end
else
out[VAR1] = 1'b0;
end
end
endmodule | gpl-2.0 |
brandonpelfrey/ice40-nes | src/mod_hex_display.v | 6,901 | module MODULE1(
input VAR8, input [9:0] VAR1, input [9:0] VAR3,
input VAR4,
input [7:0] VAR6, input [7:0] VAR13, input [7:0] VAR17,
input [7:0] VAR10,
input [7:0] VAR19,
input [7:0] VAR16,
input [7:0] VAR18,
input [7:0] VAR15,
input [7:0] VAR11, input [7:0] VAR2,
input [7:0] VAR14,
output [7:0] VAR9, output [7:0] VAR5,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai_4.v | 2,351 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR9,
VAR2,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR9;
input VAR2;
input VAR7 ;
input VAR6 ;
VAR4 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_16.behavioral.pp.v | 1,251 | module MODULE1( VAR5, VAR8, VAR2, VAR6, VAR3 );
input VAR5, VAR8;
inout VAR6, VAR3;
output VAR2;
VAR4 VAR7(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3));
VAR4 VAR1(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
Murailab-arch/magukara | boards/netfpga/rtl/pci.v | 20,940 | module MODULE1 (
input VAR50,
input VAR88,
inout [31:0] VAR122, output VAR133,
inout [3:0] VAR74,
output reg VAR87 = 1'b1,
inout VAR115,
output reg VAR70 = 1'b1,
inout VAR47,
output reg VAR72 = 1'b1,
inout VAR106,
output reg VAR124 = 1'b1,
inout VAR99,
output reg VAR89 = 1'b1,
inout VAR20,
output reg VAR40 = 1'b1,
inou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.functional.v | 1,424 | module MODULE1 (
VAR5 ,
VAR6,
VAR3,
VAR2
);
output VAR5 ;
input VAR6;
input VAR3;
input VAR2;
wire VAR4 ;
wire VAR1;
and VAR9 (VAR4 , VAR6, VAR3 );
nor VAR8 (VAR1, VAR2, VAR4 );
buf VAR7 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.functional.v | 1,443 | module MODULE1( VAR4, VAR7, VAR6, VAR13, VAR3 );
input VAR6, VAR4, VAR13, VAR3;
output VAR7;
wire VAR2;
not VAR10( VAR2, VAR6 );
wire VAR9;
not VAR12( VAR9, VAR4 );
wire VAR1;
and VAR5( VAR1, VAR2, VAR9 );
wire VAR16;
not VAR11( VAR16, VAR13 );
wire VAR8;
not VAR15( VAR8, VAR3 );
or VAR14( VAR7, VAR1, VAR16, VAR8 );
en... | apache-2.0 |
qiuzou/nysa_saya | rtl/link/cont_controller.v | 15,200 | module MODULE1 (
input rst, input clk,
input VAR14,
input VAR25,
input VAR62,
input [31:0] VAR9,
input VAR2,
output [31:0] VAR31,
output VAR15,
input [31:0] VAR6,
input [3:0] VAR73,
output VAR53,
output VAR30,
output VAR42,
output VAR58,
output VAR67,
output VAR18,
output VAR26,
output VAR35,
output VAR11,
output VAR36... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/ime/ime_sad_16x16_buffer.v | 4,662 | module MODULE1 (
clk ,
VAR18 ,
VAR13 ,
VAR12 ,
VAR3 ,
VAR23 ,
VAR10 ,
VAR24 ,
VAR25 ,
VAR6 ,
VAR19 ,
VAR26 ,
VAR1 ,
VAR29 ,
VAR20 ,
VAR15 ,
VAR21 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR17
);
input clk ;
input VAR18 ;
input [4 : 0] VAR13 ;
input VAR12 ;
input [1 : 0] VAR3 ;
input [VAR27+7 : 0] VAR23 ;
input [VAR27+7 : 0] VAR10 ;
inp... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_img_0_cols_V_channel.v | 3,019 | module MODULE2 (
clk,
VAR19,
VAR8,
VAR25,
VAR21);
parameter VAR6 = 32'd12;
parameter VAR26 = 32'd2;
parameter VAR4 = 32'd3;
input clk;
input [VAR6-1:0] VAR19;
input VAR8;
input [VAR26-1:0] VAR25;
output [VAR6-1:0] VAR21;
reg[VAR6-1:0] VAR5 [0:VAR4-1];
integer VAR14;
always @ (posedge clk)
begin
if (VAR8)
begin
for (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.behavioral.pp.v | 2,229 | module MODULE1 (
VAR8 ,
VAR19 ,
VAR11 ,
VAR15 ,
VAR5 ,
VAR4 ,
VAR14,
VAR9,
VAR13 ,
VAR18
);
output VAR8 ;
input VAR19 ;
input VAR11 ;
input VAR15 ;
input VAR5 ;
input VAR4 ;
input VAR14;
input VAR9;
input VAR13 ;
input VAR18 ;
wire VAR20 ;
wire VAR16 ;
wire VAR7 ;
wire VAR6;
and VAR2 (VAR20 , VAR15, VAR5 );
and VAR1 (V... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_LEDs.v | 2,233 | module MODULE1 (
address,
VAR7,
clk,
VAR5,
VAR6,
VAR3,
VAR8,
VAR4
)
;
output [ 9: 0] VAR8;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR5;
input VAR6;
input [ 31: 0] VAR3;
wire VAR2;
reg [ 9: 0] VAR1;
wire [ 9: 0] VAR8;
wire [ 9: 0] VAR9;
wire [ 31: 0] VAR4;
assign VAR2 = 1;
assign VAR9 ... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/infrastructure.v | 10,809 | module MODULE1 #
(
parameter VAR64 = 5000,
parameter VAR54 = 1,
parameter VAR85 = "VAR73",
parameter VAR99 = 1,
parameter VAR24 = 1,
parameter VAR28 = 16,
parameter VAR2 = 8,
parameter VAR44 = 2,
parameter VAR71 = 1
)
(
input VAR22,
input VAR76,
input VAR113,
input VAR15,
output VAR120,
output VAR70,
output VAR8,
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.behavioral.v | 2,694 | module MODULE1 (
VAR18 ,
VAR28 ,
VAR2 ,
VAR17 ,
VAR12 ,
VAR5,
VAR19 ,
VAR15
);
input VAR18 ;
input VAR28 ;
output VAR2 ;
input VAR17 ;
input VAR12 ;
input VAR5;
input VAR19 ;
input VAR15 ;
wire VAR20 ;
wire VAR29 ;
wire VAR10 ;
reg VAR22 ;
wire VAR26 ;
wire VAR9 ;
wire VAR14 ;
wire VAR21;
wire VAR6 ;
wire VAR13 ;
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.pp.blackbox.v | 1,305 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5,
VAR4,
VAR1,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR1;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_immu_tlb.v | 8,995 | module MODULE1(
clk, rst,
VAR18, VAR30, VAR36, VAR41, VAR12, VAR29, VAR23,
VAR7, VAR8, VAR37,
VAR27, VAR38, VAR32, VAR54, VAR53
);
parameter VAR51 = VAR52;
parameter VAR11 = VAR52;
input clk;
input rst;
input VAR18;
input [VAR11-1:0] VAR30;
output VAR36;
output [31:VAR2] VAR41;
output VAR12;
output VAR29;
output VAR23;... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_mem_if_top.v | 15,999 | module MODULE1 #
(
parameter VAR113 = 2,
parameter VAR52 = 1,
parameter VAR7 = 1,
parameter VAR60 = 10,
parameter VAR68 = 0,
parameter VAR118 = 1,
parameter VAR78 = 1,
parameter VAR93 = 1,
parameter VAR114 = 9,
parameter VAR18 = 72,
parameter VAR72 = 7,
parameter VAR85 = 8,
parameter VAR5 = 4,
parameter VAR96 = 9,
para... | lgpl-3.0 |
alan4186/Hardware-CNN | DE2_115_CAMERA/v/Line_Buffer.v | 5,098 | module MODULE1 (
VAR22,
VAR8,
VAR19,
VAR11,
VAR7,
VAR14,
VAR3);
input VAR22;
input VAR8;
input [11:0] VAR19;
output [11:0] VAR11;
output [11:0] VAR7;
output [11:0] VAR14;
output [11:0] VAR3;
tri1 VAR22;
wire [35:0] VAR4;
wire [11:0] VAR18;
wire [23:12] VAR23 = VAR4[23:12];
wire [11:0] VAR16 = VAR4[11:0];
wire [35:24] V... | mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/hdl/verilog/tri_intersect_data_array.v | 1,979 | module MODULE2 (VAR11, VAR18, VAR15, VAR8, VAR5, VAR6, VAR1, VAR4, VAR13, VAR17, clk);
parameter VAR19 = 576;
parameter VAR7 = 5;
parameter VAR10 = 20;
input[VAR7-1:0] VAR11;
input VAR18;
input[VAR19-1:0] VAR15;
input VAR8;
output reg[VAR19-1:0] VAR5;
input[VAR7-1:0] VAR6;
input VAR1;
input[VAR19-1:0] VAR4;
input VAR13... | mit |
walkthetalk/fsref | ip/fscpu/src/include/AM_ctl.v | 3,356 | module MODULE1 # (
parameter integer VAR1 = 32,
parameter integer VAR19 = 32
) (
input wire clk,
input wire VAR26,
output reg VAR12,
input wire VAR28,
input wire VAR16,
input wire [VAR19-1:0] VAR20,
input wire signed [VAR1-1:0] VAR5,
output wire VAR29 ,
input wire VAR21 ,
input wire VAR22 ,
input wire VAR2 ,
input wire... | gpl-3.0 |
ZiCog/xoro | rtl/picorv32.v | 92,469 | module MODULE1 #(
parameter [ 0:0] VAR52 = 1,
parameter [ 0:0] VAR91 = 1,
parameter [ 0:0] VAR33 = 1,
parameter [ 0:0] VAR16 = 1,
parameter [ 0:0] VAR4 = 0,
parameter [ 0:0] VAR42 = 1,
parameter [ 0:0] VAR1 = 0,
parameter [ 0:0] VAR37 = 0,
parameter [ 0:0] VAR25 = 0,
parameter [ 0:0] VAR88 = 0,
parameter [ 0:0] VAR59 =... | mit |
somethingnew2-0/CS552-CPU | rf_pipelined.v | 2,482 | module MODULE1(clk,VAR11,VAR9,VAR3,VAR8,VAR1,VAR4,VAR12,VAR10,VAR7,VAR2);
input clk;
input [3:0] VAR11, VAR9; input VAR1,VAR4; input [3:0] VAR12; input [15:0] VAR10; input VAR7; input VAR2;
output reg [15:0] VAR3,VAR8;
integer VAR6;
reg [15:0]VAR5[0:15]; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.v | 2,825 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR13 ,
VAR3 ,
VAR12,
VAR9 ,
VAR14 ,
VAR5 ,
VAR4
);
output VAR6 ;
output VAR10 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR13 ;
input VAR3 ;
input VAR12;
input VAR9 ;
input VAR14 ;
input VAR5 ;
input VAR4 ;
VAR1 VAR11 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
... | apache-2.0 |
Jside/nova1 | nova_io.v | 4,698 | module MODULE1(VAR3, VAR25,
VAR23, VAR31, VAR21, VAR20, VAR26, VAR34,
VAR8, VAR11, VAR10, VAR36, VAR1);
input VAR3;
input VAR25;
input [0:15] VAR23;
input [0:15] VAR31;
output reg [0:15] VAR21;
output reg VAR20;
output VAR26;
input VAR34;
output reg VAR8;
output reg VAR11;
output reg [0:7] VAR10;
output reg [0:15] VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.pp.symbol.v | 1,457 | module MODULE1 (
input VAR4,
input VAR2,
input VAR1 ,
input VAR7 ,
output VAR9 ,
input VAR5 ,
input VAR3,
input VAR8,
input VAR6
);
endmodule | apache-2.0 |
cathalmccabe/PYNQ | boards/ip/pattern_controller_1.1/pattern_controller.v | 3,497 | module MODULE1 #(parameter VAR19 = 18)(
input clk,
input [5:0] VAR21,
input [VAR19-1:0] VAR14, input VAR11, input VAR13,
output [VAR19-1:0] VAR18, output reg VAR5
);
reg VAR23=0, VAR12=0;
wire VAR7;
wire VAR16;
wire VAR15;
reg [VAR19-1:0] VAR17;
wire VAR4;
wire VAR9;
reg VAR6=0;
VAR3 VAR20(.VAR22(VAR21[0]&VAR21[2]), .V... | bsd-3-clause |
trevortheblack/NewLondo16 | Verilog/RFT/asr.v | 2,425 | module MODULE1(VAR1, VAR8, VAR4, VAR7, VAR6);
input [31:0] VAR1, VAR8;
input [3:0] VAR4;
output [31:0] VAR7;
input VAR6;
wire VAR3 = |VAR8[31:5];
wire VAR5 = VAR8[4:0];
wire [4:0] VAR2 = (VAR5== 32'b0) ?
( {1'b0, VAR4} + 5'b1) : (VAR5 + {1'b0, VAR4});
assign VAR7 = (VAR3==1'b1) ? 32'b0 : (
(VAR2 == 5'b00000) ? VAR1[31:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.pp.blackbox.v | 1,359 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR2 ,
VAR5,
VAR4,
VAR6 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_fifo_to_fifo.v | 16,717 | module MODULE2 #(parameter VAR66( VAR50 )
, parameter VAR61 = 0
, parameter VAR80 = 0
, parameter VAR4 = VAR80 * VAR50
, parameter VAR34 = VAR9(VAR61,VAR80)
)
(input clk, input reset
, input [VAR61-1:0] VAR98
, input [VAR50-1:0] VAR82 [VAR61-1:0]
, output [VAR50-1:0] VAR84 [VAR80-1:0]
, output [VAR80-1:0] VAR78
, input... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.functional.v | 1,443 | module MODULE1( VAR12, VAR1, VAR15, VAR9, VAR13 );
input VAR15, VAR12, VAR9, VAR13;
output VAR1;
wire VAR4;
not VAR10( VAR4, VAR15 );
wire VAR14;
not VAR11( VAR14, VAR12 );
wire VAR3;
and VAR16( VAR3, VAR4, VAR14 );
wire VAR6;
not VAR8( VAR6, VAR9 );
wire VAR7;
not VAR5( VAR7, VAR13 );
or VAR2( VAR1, VAR3, VAR6, VAR7 )... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.functional.v | 1,585 | module MODULE1( VAR2, VAR13, VAR16, VAR14, VAR18 );
input VAR16, VAR2, VAR14, VAR18;
output VAR13;
wire VAR5;
not VAR8( VAR5, VAR16 );
wire VAR10;
not VAR6( VAR10, VAR14 );
wire VAR3;
not VAR17( VAR3, VAR18 );
wire VAR1;
and VAR7( VAR1, VAR5, VAR10, VAR3 );
wire VAR15;
not VAR11( VAR15, VAR2 );
wire VAR4;
and VAR12( VA... | apache-2.0 |
darekb74/WSIZ_SW_Projekt1 | Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v | 10,304 | module MODULE1(
input wire clk, input wire [2:0] VAR16, output reg [2:0] VAR8, input wire [2:0] VAR5, output reg [1:0] VAR21, output wire [4:0] VAR17 );
parameter VAR2 = VAR9; parameter VAR6 = VAR14; parameter VAR27 = VAR3;
reg [4:0]VAR19; reg [4:0]VAR18; reg [4:0]VAR23;
assign VAR17 = VAR19;
always @(VAR5) begin
VAR18... | gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/new/kbd.v | 3,081 | module MODULE1(
output reg [511:0] VAR20,
output wire [8:0] VAR13,
output reg VAR8,
inout wire VAR19,
inout wire VAR5,
input wire rst,
input wire clk
);
parameter [1:0] VAR16 = 2'b00;
parameter [1:0] VAR23 = 2'b01;
parameter [1:0] VAR18 = 2'b10;
parameter [1:0] VAR21 = 2'b11;
parameter [7:0] VAR9 = 8'hAA;
parameter [7:... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_obuft4.v | 1,229 | module MODULE1(
input [3:0] VAR6,
input [3:0] VAR3,
output [3:0] VAR2
);
VAR5 VAR7(
.VAR6(VAR6[0]),
.VAR3(VAR3[0]),
.VAR2(VAR2[0])
);
VAR5 VAR1(
.VAR6(VAR6[1]),
.VAR3(VAR3[1]),
.VAR2(VAR2[1])
);
VAR5 VAR4(
.VAR6(VAR6[2]),
.VAR3(VAR3[2]),
.VAR2(VAR2[2])
);
VAR5 VAR8(
.VAR6(VAR6[3]),
.VAR3(VAR3[3]),
.VAR2(VAR2[3])
);
end... | lgpl-3.0 |
horia141/bachelor-thesis | prj/components/VGA1/VGA1Interface.v | 2,623 | module MODULE1(VAR13,reset,VAR9,VAR11,VAR3,VAR15,VAR10,VAR16);
input wire VAR13;
input wire reset;
input wire [63:0] VAR9;
output wire VAR11;
output wire VAR3;
output wire VAR15;
output wire VAR10;
output wire VAR16;
reg [9:0] VAR5;
reg [8:0] VAR7;
wire VAR4;
reg VAR17 = 0;
always @ (posedge VAR13) begin
if (reset) beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.symbol.v | 1,416 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR4,
input VAR8
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
secworks/fpga_entropy | src/rtl/bp_osc.v | 3,623 | module MODULE1 #(parameter VAR4 = 8)
(
input wire clk,
input wire VAR3,
input wire [(VAR4 - 1) : 0] VAR6,
input wire [(VAR4 - 1) : 0] VAR2,
output wire dout
);
reg VAR5;
reg [VAR4 : 0] sum;
reg VAR1;
assign dout = VAR5;
always @ (posedge clk or negedge VAR3)
begin
if (!VAR3)
begin
VAR5 <= 1'b0;
end
else
begin
VAR5 <= V... | bsd-2-clause |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/Radar_top.v | 1,353 | module MODULE1(
input clk,
input VAR13,
input [11:0] VAR4,
output [11:0] VAR40,
output [11:0] VAR20,
output VAR34,
output VAR39,
output VAR41,
output VAR15,
output [11:0] VAR2,
output [11:0] VAR35,
output [11:0] VAR19,
output [11:0] VAR31,
input VAR16,
input VAR14
);
wire VAR17, VAR36, VAR25;
VAR22 VAR6 (.clk(clk), .VA... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/trigger_context_pkt.v | 2,085 | module MODULE1
(input clk, input reset, input VAR14,
input VAR19, input [7:0] VAR5, input [31:0] VAR9,
input VAR12, output reg VAR13);
wire [23:0] VAR3;
wire [15:0] VAR22;
wire [6:0] VAR21;
wire [14:0] VAR6;
wire VAR1, VAR20;
reg [30:0] VAR17, VAR16;
VAR11 #(.VAR15(VAR8+4), .VAR4(0)) VAR10
(.clk(clk),.rst(reset),.VAR2(... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/CNN_Optimization2/solution1/syn/verilog/convolve_kernel_fbkb.v | 1,946 | module MODULE1
VAR8 = 0,
VAR9 = 9,
VAR6 = 32,
VAR21 = 32,
VAR22 = 32
)(
input wire clk,
input wire reset,
input wire VAR20,
input wire [VAR6-1:0] VAR10,
input wire [VAR21-1:0] VAR25,
output wire [VAR22-1:0] dout
);
wire VAR14;
wire VAR4;
wire VAR3;
wire [31:0] VAR7;
wire VAR23;
wire [31:0] VAR24;
wire VAR2;
wire [31:0]... | mit |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/stratix3_dmem.v | 7,635 | module MODULE1 (
address,
VAR4,
VAR22,
VAR3,
VAR12,
VAR14,
VAR52);
input [9:0] address;
input [1:0] VAR4;
input VAR22;
input VAR3;
input [15:0] VAR12;
input VAR14;
output [15:0] VAR52;
tri1 [1:0] VAR4;
tri1 VAR22;
tri1 VAR3;
wire [15:0] VAR25;
wire [15:0] VAR52 = VAR25[15:0];
VAR19 VAR42 (
.VAR34 (VAR22),
.VAR38 (VAR14... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b_1.v | 2,127 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR7 ,
VAR8,
VAR1,
VAR2 ,
VAR9
);
output VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR8;
input VAR1;
input VAR2 ;
input VAR9 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR6 ,
VAR5 ,
VAR7
);
output VAR6... | apache-2.0 |
kielfriedt/ece472 | lab3/alu_slice_LA.v | 1,328 | module MODULE1(VAR11, VAR5, VAR6, VAR1, sel, out, VAR9, VAR4);
input VAR11, VAR5, VAR6, VAR1;
input [2:0] sel;
output out;
output VAR9, VAR4;
wire sum, VAR12, VAR2,VAR1, VAR3, VAR10, VAR9, VAR4;
reg out;
assign VAR10 = sel[2] ^ VAR5;
assign VAR2 = VAR11 & VAR5;
assign VAR3 = VAR11 | VAR5;
VAR8 VAR7(VAR11, VAR10, VAR6, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai_2.v | 2,261 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR1 ,
VAR10 ,
VAR8,
VAR6,
VAR2 ,
VAR3
);
output VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR8;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR7 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/f_permutation.v | 2,047 | module MODULE1(clk, reset, in, VAR1, ack, out, VAR5);
input clk, reset;
input [575:0] in;
input VAR1;
output ack;
output reg [1599:0] out;
output reg VAR5;
reg [22:0] VAR8;
wire [1599:0] VAR6, VAR11;
wire [63:0] VAR9;
wire VAR3;
wire VAR7;
reg VAR4;
assign VAR7 = VAR1 & (~ VAR4);
always @ (posedge clk)
if (reset) VAR8 ... | apache-2.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/FSM_C_CORDIC.v | 10,297 | module MODULE1(
input wire VAR18, input wire VAR9, input wire VAR41, input wire VAR2, input wire VAR8, input wire VAR45, input wire [4:0] VAR28,
output reg VAR36, output reg VAR24, output reg VAR20, output reg VAR22, output reg VAR38, output reg VAR3, output reg VAR19, output reg VAR25, output reg VAR32, output reg VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.blackbox.v | 1,315 | module MODULE1 (
VAR4,
VAR2 ,
VAR1 ,
VAR3
);
output VAR4;
input VAR2 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
zeldin/logic16_bitstream | src/regaccess.v | 1,599 | module MODULE1(
input clk,
input rst,
input VAR11,
input VAR18,
output VAR7,
input VAR3,
output [6:0] VAR6,
input [7:0] VAR22,
output [7:0] VAR20,
output read,
output write
);
wire VAR9;
wire [7:0] din;
wire [7:0] dout;
reg [6:0] VAR5, VAR15;
reg VAR17, VAR4;
reg VAR12, VAR1;
reg VAR13, VAR16;
reg VAR10, VAR19;
reg VAR... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/ecc/mig_7series_v1_9_ecc_merge_enc.v | 5,947 | module MODULE1
parameter VAR3 = 100,
parameter VAR15 = 64,
parameter VAR13 = 72,
parameter VAR28 = 4,
parameter VAR4 = 1,
parameter VAR24 = 64,
parameter VAR18 = 72,
parameter VAR26 = 8,
parameter VAR10 = 4
)
(
VAR9, VAR7,
clk, rst, VAR16, VAR12, VAR27, VAR14, VAR5
);
input clk;
input rst;
input [2*VAR10*VAR15-1:0] VAR... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/Karatsubas/Karatsubas.srcs/sources_1/imports/sine_cosine_CORDIC/CORDIC_Arch2.v | 20,021 | module MODULE1 #(parameter VAR111 = 32, parameter VAR120 = 8, parameter VAR135 = 23, parameter VAR99=26, parameter VAR87 = 5)/*#(parameter VAR111 = 64, parameter VAR120 = 11, parameter VAR135 = 52, parameter VAR99 = 55, parameter VAR87 = 6) (
input wire clk, input wire rst, input wire VAR70, input wire VAR67, input wir... | gpl-3.0 |
google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram | cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.v | 16,710 | module MODULE1 (
VAR25,
VAR29,
VAR39,
VAR33,
VAR43,
VAR3,
VAR45,
VAR38,
VAR32
);
input VAR25;
input VAR29; input VAR39; input [7:0] VAR33; input [8:0] VAR43;
input [7:0] VAR3;
output [7:0] VAR45;
inout VAR38;
inout VAR32;
reg [7:0] VAR16[511:0];
reg [7:0] VAR20;
wire VAR6;
wire VAR23;
wire VAR48;
reg VAR21; reg VAR2;
r... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.blackbox.v | 1,363 | module MODULE1 (
VAR3 ,
VAR8,
VAR4 ,
VAR1 ,
VAR6,
VAR2
);
output VAR3 ;
input VAR8;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR2;
supply1 VAR7;
supply0 VAR5;
endmodule | apache-2.0 |
iamllama/EE2020 | ee2020.srcs/sources_1/new/triangle.v | 1,438 | module MODULE1(input VAR11, input signed[33:0] VAR7, input signed[33:0] VAR3, input signed[33:0] VAR6, input signed[33:0] VAR5, output[11:0] VAR14);
parameter VAR9 = 100000000;
reg signed[33:0] VAR10 = 0;
reg state = 1'b0;
wire signed[33:0] VAR1 = VAR5 < 15 ? 15 : VAR5 > 989 ? 999 : VAR5;
wire signed[33:0] VAR8 = (2 * ... | gpl-3.0 |
jameshegarty/rigel | platform/verilator/RAMB16_S18_S18.v | 3,538 | module MODULE1(
input VAR30,
input VAR65,
input VAR83,
input VAR18,
input [9:0] VAR3,
input [15:0] VAR69,
input [1:0] VAR57,
output [15:0] VAR12,
input VAR72,
input VAR49,
input VAR63,
input VAR19,
input [9:0] VAR7,
input [15:0] VAR60,
input [1:0] VAR35,
output [15:0] VAR42);
parameter VAR58 = "VAR43";
parameter VAR15 ... | mit |
r2apu/Labo_Digitales | MIniAlu_g2/actual/Collaterals.v | 13,383 | module MODULE1 # (parameter VAR60=16)
(
input wire VAR1, VAR2,
input wire [VAR60-1:0] VAR62,
input wire VAR49,
output reg [VAR60-1:0] VAR36
);
always @(posedge VAR1 )
begin
if (VAR2)
VAR36 = VAR62;
end
else
begin
if (VAR49)
VAR36 = VAR36 + 1;
end
end
endmodule
module MODULE9 (VAR40,VAR26,VAR58,VAR8, sel, out);
input wi... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_csc_1.v | 4,535 | module MODULE1 (
clk,
VAR13,
VAR18,
VAR16,
VAR1,
VAR28,
VAR10,
VAR23,
VAR8,
VAR29,
VAR17,
VAR5,
VAR6);
input clk;
input VAR13;
input VAR18;
input VAR16;
input [23:0] VAR1;
input [16:0] VAR28;
input [16:0] VAR10;
input [16:0] VAR23;
input [24:0] VAR8;
output VAR29;
output VAR17;
output VAR5;
output [ 7:0] VAR6;
wire [24... | mit |
abjordan/RECON2014 | ex3/uart_rx.v | 1,997 | module MODULE1(
input wire clk,
input wire rst,
input wire din,
output reg valid,
output reg [7:0] VAR10);
reg [8:0] VAR9;
reg [2:0] VAR2;
reg [7:0] VAR6;
reg [1:0] state;
reg VAR8;
wire VAR1 = (VAR9 == VAR7);
wire VAR4 = (VAR9 == VAR11);
always @(posedge clk) begin
VAR9 <= (VAR9 + 1);
VAR2 <= VAR2;
state <= state;
val... | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/fmlarb/fmlarb.v | 6,159 | module MODULE1 #(
parameter VAR12 = 26,
parameter VAR14 = 32
) (
input VAR28,
input VAR58,
input [VAR12-1:0] VAR70,
input VAR21,
input VAR38,
output VAR16,
input [VAR14/8-1:0] VAR66,
input [VAR14-1:0] VAR42,
output [VAR14-1:0] VAR62,
input [VAR12-1:0] VAR52,
input VAR8,
input VAR71,
output VAR44,
input [VAR14/8-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb.pp.blackbox.v | 1,255 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1,
VAR2,
VAR6 ,
VAR4
);
output VAR5 ;
output VAR3 ;
input VAR1;
input VAR2;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/SHIFTREGRAM/SHIFTREGRAM_bb.v | 3,880 | module MODULE1 (
VAR3,
VAR2,
VAR1,
VAR5,
VAR4);
input VAR3;
input VAR2;
input [12:0] VAR1;
output [12:0] VAR5;
output [168:0] VAR4;
tri1 VAR3;
endmodule | gpl-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/altera_mult_add_s1u2.v | 15,695 | module MODULE1
(
VAR245,
VAR272,
VAR226,
VAR42,
VAR233) ;
input VAR245;
input VAR272;
input [15:0] VAR226;
input [15:0] VAR42;
output [15:0] VAR233;
tri0 VAR245;
tri1 VAR272;
tri0 [15:0] VAR226;
tri0 [15:0] VAR42;
wire [15:0] VAR97;
VAR154 VAR223
(
.VAR245(VAR245),
.VAR94(),
.VAR272(VAR272),
.VAR226(VAR226),
.VAR42(VAR... | gpl-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_dma_to_memory.v | 4,698 | module MODULE1 (
clk,
reset,
VAR14,
VAR13,
VAR6,
VAR3,
VAR7,
VAR1,
VAR16,
VAR15,
VAR2,
VAR10,
VAR4
);
parameter VAR12 = 15; parameter VAR9 = 0;
parameter VAR5 = 15;
input clk;
input reset;
input [VAR12: 0] VAR14;
input VAR13;
input VAR6;
input [VAR9: 0] VAR3;
input VAR7;
input VAR1;
output VAR16;
output VAR15;
output [... | gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/Keyboard/src/hdl/top.v | 1,223 | module MODULE1(
input VAR3,
input VAR8,
input VAR13,
output [6:0]VAR17,
output [7:0]VAR6,
output VAR16,
output VAR12
);
reg VAR11=0;
wire [31:0]VAR10;
always @(posedge(VAR3))begin
VAR11<=~VAR11;
end
VAR2 VAR5 (
.clk(VAR11),
.VAR14(VAR8),
.VAR9(VAR13),
.VAR19(VAR10[31:0])
);
VAR7 VAR1 (
.VAR18(VAR10[31:0]),
.clk(VAR3),
... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_top.v | 36,514 | module MODULE1(
clk ,
VAR78 ,
VAR38 ,
VAR70 ,
VAR99 ,
VAR68 ,
VAR151 ,
VAR140 ,
VAR175 ,
VAR142 ,
VAR27 ,
VAR108 ,
VAR50 ,
VAR61 , VAR44 ,
VAR11 ,
VAR164 , VAR75 ,
VAR52 ,
VAR31 ,
VAR169 ,
VAR67 ,
VAR60 ,
VAR139 ,
VAR105 ,
VAR130 ,
VAR157 ,
VAR111 ,
VAR51 ,
VAR124 ,
VAR21 ,
VAR37 ,
VAR147 ,
VAR47 ,
VAR64 ,
VAR119 ,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.behavioral.v | 1,498 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR12 ,
VAR10 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR10 ;
input VAR1;
supply1 VAR11;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
wire VAR9 ;
wire VAR14;
not VAR6 (VAR9 , VAR1 );
or VAR13 (VAR14, VAR9, VAR10, VAR12, VAR2);
buf VAR8 (VAR7 , VAR14 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai_1.v | 2,411 | module MODULE1 (
VAR10 ,
VAR2,
VAR5,
VAR4 ,
VAR6 ,
VAR7,
VAR3,
VAR9 ,
VAR11
);
output VAR10 ;
input VAR2;
input VAR5;
input VAR4 ;
input VAR6 ;
input VAR7;
input VAR3;
input VAR9 ;
input VAR11 ;
VAR1 VAR8 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_dll_memphy.v | 5,792 | module MODULE1
(
VAR4,
VAR2) ;
input [0:0] VAR4;
output [5:0] VAR2;
wire [5:0] VAR5;
VAR7 VAR21
(
.clk(VAR4),
.VAR20(VAR5),
.VAR8(),
.VAR19(),
.VAR9(),
.VAR18()
,
.VAR3(1'b0),
.VAR23(1'b1),
.VAR6(1'b1)
,
.VAR1(1'b1),
.VAR14(1'b0)
);
= "VAR17",
VAR21.VAR13 = 8,
VAR21.VAR10 = "1876 VAR24",
VAR21.VAR12 = "true",
VAR21.VAR... | lgpl-3.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_pic.v | 6,298 | module MODULE1(
clk, rst, VAR3, VAR15, VAR7, VAR6, VAR20,
VAR19, VAR9,
VAR8
);
input clk; input rst; input VAR3; input VAR15; input [31:0] VAR7; input [31:0] VAR6; output [31:0] VAR20; output VAR19; output VAR9;
input [VAR1-1:0] VAR8;
reg [VAR1-1:2] VAR18; else
wire [VAR1-1:2] VAR18; VAR11
reg [VAR1-1:0] VAR13; else
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.behavioral.v | 1,154 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v | 7,193 | module MODULE1 #
(
parameter VAR33 = 100,
parameter VAR16 = 5, parameter VAR14 = 1
)
(
output[VAR14-1:0] VAR21,
input [VAR14-1:0] VAR28,
input VAR24,
input VAR23,
input rst
);
localparam VAR10 = (VAR16-1)/2;
reg VAR9;
reg [VAR10:0] VAR22;
reg [2:0] VAR7;
reg VAR19;
reg VAR18;
reg [2:0] VAR29;
always @(posedge VAR24 or ... | lgpl-3.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_qpll_drp.v | 20,757 | module MODULE1 #
(
parameter VAR24 = "VAR52", parameter VAR14 = "3.0", parameter VAR62 = "VAR68", parameter VAR80 = 0, parameter VAR72 = 2'd3, parameter VAR66 = 3'd6
)
(
input VAR64,
input VAR8,
input VAR82,
input VAR79,
input VAR20,
input VAR57,
input [15:0] VAR83,
input VAR55,
output [ 7:0] VAR70,
output VAR50,
outpu... | mit |
parallella/oh | mio/hdl/mtx_fifo.v | 5,265 | module MODULE1 # ( parameter VAR20 = 136, parameter VAR25 = 64, parameter VAR2 = 16, parameter VAR8 = "VAR21" )
( input clk, input VAR45, input VAR5, input VAR28, input VAR44, input VAR17, input [VAR20-1:0] VAR27, output VAR18, output [63:0] VAR40, output [7:0] VAR43, input VAR36 );
reg [1:0] VAR42;
reg [191:0] VAR6;
w... | mit |
kyzhai/NUNY | src/hardware/seven_new2_bb.v | 5,028 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.v | 2,443 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR6 ,
VAR3 ,
VAR11 ,
VAR10,
VAR12,
VAR1 ,
VAR8
);
output VAR2 ;
output VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR11 ;
input VAR10;
input VAR12;
input VAR1 ;
input VAR8 ;
VAR4 VAR7 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR10... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/mgt/rocketio_wrapper_tile.v | 67,398 | module MODULE1 #
(
parameter VAR404 = "false" )
(
input VAR292,
output VAR409,
output VAR414,
input VAR110,
output VAR289,
input VAR184,
output VAR242,
input [2:0] VAR260,
input [1:0] VAR85,
input [1:0] VAR353,
input VAR340,
output [1:0] VAR115,
output VAR303,
output VAR37,
output VAR413,
input VAR10,
input VAR328,
out... | gpl-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_xbar_0/synth/system_xbar_0.v | 14,868 | module MODULE1 (
VAR52,
VAR15,
VAR45,
VAR33,
VAR55,
VAR58,
VAR70,
VAR129,
VAR121,
VAR100,
VAR117,
VAR111,
VAR43,
VAR94,
VAR1,
VAR50,
VAR76,
VAR51,
VAR73,
VAR28,
VAR26,
VAR46,
VAR57,
VAR123,
VAR69,
VAR71,
VAR13,
VAR16,
VAR78,
VAR83,
VAR132,
VAR17,
VAR19,
VAR32,
VAR109,
VAR3,
VAR54,
VAR42,
VAR39,
VAR116
);
input wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.pp.symbol.v | 1,278 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR4 ,
output VAR1 ,
input VAR3 ,
input VAR7,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4_4.v | 2,231 | module MODULE2 (
VAR5 ,
VAR11 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR1,
VAR7,
VAR4 ,
VAR9
);
output VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR4 ;
input VAR9 ;
VAR3 VAR10 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR... | apache-2.0 |
MeshSr/onetswitch30 | ons30-gsg-2-gt_ibert/vivado/onets_7030_gt_ibert/sources/onetswitch_top.v | 2,935 | module MODULE1
(
output [(4*VAR30)-1:0] VAR24,
output [(4*VAR30)-1:0] VAR20,
input [(4*VAR30)-1:0] VAR25,
input [(4*VAR30)-1:0] VAR12,
input [VAR9-1:0] VAR10,
input [VAR9-1:0] VAR28,
input [VAR9-1:0] VAR13,
input [VAR9-1:0] VAR3
);
wire [VAR30-1:0] VAR7;
wire [VAR30-1:0] VAR16;
wire [VAR9-1:0] VAR23;
wire [VAR9-1:0] VA... | lgpl-2.1 |
Franderg/CE-4301-Arqui1 | Processor/ALU.v | 2,261 | module MODULE1(VAR11, VAR19, VAR1 , VAR22, VAR15);
output reg [31:0] VAR22;
output reg [0:0] VAR15;
input [31:0] VAR11, VAR19;
input [4:0] VAR1;
parameter VAR17 = 5'd0;
parameter VAR14 = 5'd1;
parameter VAR18 = 5'd2;
parameter VAR24 = 5'd3;
parameter VAR4 = 5'd4;
parameter VAR12 = 5'd5;
parameter VAR23 = 5'd6;
paramete... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_64x22.v | 10,969 | module MODULE1(
VAR34, VAR50, VAR23,
clk, rst, VAR46, VAR30, VAR7, addr, VAR32, VAR27
);
parameter VAR52 = 6;
parameter VAR43 = 22;
input VAR34;
input [VAR54 - 1:0] VAR23;
output VAR50;
input clk; input rst; input VAR46; input VAR30; input VAR7; input [VAR52-1:0] addr; input [VAR43-1:0] VAR32; output [VAR43-1:0] VAR27;... | gpl-3.0 |
AloriumTechnology/XLR8LFSR | extras/rtl/alorium_lfsr.v | 1,693 | module MODULE1
(
input clk,
input VAR7,
input VAR8,
input enable,
input wire [7:0] VAR3,
input VAR5,
output reg VAR1,
output reg [7:0] VAR4
);
reg [29:0] VAR6;
wire VAR2;
assign VAR2 = ~(VAR4[7] ^ VAR4[5] ^
VAR4[4] ^ VAR4[3]);
always @(posedge clk) begin
if (!VAR7) begin
VAR1 <= 0;
VAR6 <= 0;
VAR4 <= 8'h01;
end
else if... | mit |
brianbennett/fpga_nes | hw/src/cpu/apu/apu_pulse.v | 6,854 | module MODULE1
parameter [0:0] VAR33 = 1'b0 )
(
input wire VAR25, input wire VAR31, input wire VAR19, input wire VAR13, input wire VAR54, input wire VAR36, input wire [1:0] VAR5, input wire [7:0] din, input wire VAR29, output wire [3:0] VAR45, output wire VAR42 );
wire VAR43;
wire VAR48;
wire [3:0] VAR2;
VAR20 VAR55(
.... | bsd-2-clause |
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