repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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vvk/sysrek | skin_color_segm/dilation3x3.v | 2,748 | module MODULE1 #(
parameter [9:0] VAR15 = 83 )(
input clk,
input VAR1,
input rst,
input VAR11,
input VAR2,
input VAR5,
input VAR16,
output VAR27,
output VAR20,
output VAR30,
output VAR19
);
wire [3:0] VAR18;
reg [3:0] VAR12 [2:0];
wire [3:0] VAR8;
reg [3:0] VAR10 [2:0];
wire [3:0] VAR25;
reg [3:0] VAR7 [2:0];
reg [4:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.functional.pp.v | 1,757 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR3,
VAR7,
VAR4 ,
VAR5
);
output VAR12 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR5 ;
wire VAR11 ;
wire VAR10;
not VAR9 (VAR11 , VAR2 );
VAR6 VAR8 (VAR10, VAR11, VAR3, VAR7);
buf VAR1 (VAR12 , VAR10 );
endmodule | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodHYGRO_v1_0/src/PmodHYGRO.v | 9,447 | module MODULE1
(VAR106,
VAR154,
VAR43,
VAR52,
VAR29,
VAR102,
VAR150,
VAR93,
VAR90,
VAR127,
VAR157,
VAR97,
VAR51,
VAR81,
VAR117,
VAR26,
VAR27,
VAR144,
VAR46,
VAR49,
VAR3,
VAR82,
VAR112,
VAR134,
VAR30,
VAR99,
VAR123,
VAR34,
VAR89,
VAR83,
VAR94,
VAR11,
VAR70,
VAR42,
VAR128,
VAR92,
VAR115,
VAR25,
VAR12,
VAR95,
VAR85,
VAR59... | bsd-3-clause |
Giako68/SD_RAM_VIDEO | SPI.v | 3,974 | module MODULE1
( input VAR9,
output reg VAR14,
input VAR3,
output reg VAR1,
output reg VAR18,
input VAR15,
input VAR4, input [7:0] VAR5,
input VAR7,
output reg VAR2,
output reg [7:0] VAR17,
output reg VAR16,
input VAR6
);
parameter real VAR13 = 20.0;
integer VAR10;
integer VAR11;
integer VAR8;
reg [7:0] VAR12;
begin
be... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_2.v | 2,424 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR9 ,
VAR7,
VAR8,
VAR4 ,
VAR10
);
output VAR12 ;
input VAR3 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR10 ;
VAR2 VAR5 (
.VAR12(VAR12),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7... | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/db/ip/niosii/niosii.v | 55,299 | module MODULE1 (
input wire VAR66, output wire [1:0] VAR280, output wire [1:0] VAR169, output wire [7:0] VAR119, input wire VAR101, input wire VAR271, output wire VAR240 );
wire VAR124; wire VAR138; wire VAR191; wire [31:0] VAR56; wire VAR263; wire VAR187; wire [17:0] VAR78; wire [3:0] VAR25; wire VAR186; wire VAR23; w... | mit |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/cyclone2_pmem.v | 7,466 | module MODULE1 (
address,
VAR14,
VAR16,
VAR29,
VAR22,
VAR49,
VAR28);
input [11:0] address;
input [1:0] VAR14;
input VAR16;
input VAR29;
input [15:0] VAR22;
input VAR49;
output [15:0] VAR28;
tri1 [1:0] VAR14;
tri1 VAR16;
tri1 VAR29;
wire [15:0] VAR39;
wire [15:0] VAR28 = VAR39[15:0];
VAR18 VAR13 (
.VAR1 (VAR16),
.VAR53 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.behavioral.v | 1,489 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR10;
supply1 VAR11;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
wire VAR1 ;
wire VAR8;
not VAR7 (VAR1 , VAR6 );
and VAR12 (VAR8, VAR1, VAR10 );
buf VAR2 (VAR9 , VAR8 );
endmodule | apache-2.0 |
marqs85/ossc | ip/hw_crc32_qsys/CRC_Component.v | 12,003 | module MODULE2 (clk,
reset,
address,
VAR26,
VAR12,
write,
read,
VAR33,
VAR23);
parameter VAR32 = 32;
parameter VAR24 = 32'hFFFFFFFF;
parameter VAR34 = 32'h04C11DB7;
parameter VAR11 = 1;
parameter VAR4 = 1;
parameter VAR9 = 32'hFFFFFFFF;
input clk;
input reset;
input [2:0] address;
input [31:0] VAR26;
input [3:0] VAR12;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.v | 2,546 | module MODULE2 (
VAR13 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR4 ,
VAR6,
VAR12 ,
VAR10 ,
VAR7 ,
VAR2
);
output VAR13 ;
output VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR6;
input VAR12 ;
input VAR10 ;
input VAR7 ;
input VAR2 ;
VAR5 VAR1 (
.VAR13(VAR13),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(... | apache-2.0 |
jamieiles/80x86 | fpga/VGA/DACRam.v | 10,811 | module MODULE1 (
VAR3,
VAR20,
VAR45,
VAR60,
VAR12,
VAR5,
VAR59,
VAR22,
VAR53,
VAR50);
input [7:0] VAR3;
input [7:0] VAR20;
input VAR45;
input VAR60;
input [17:0] VAR12;
input [17:0] VAR5;
input VAR59;
input VAR22;
output [17:0] VAR53;
output [17:0] VAR50;
tri1 VAR45;
tri0 VAR59;
tri0 VAR22;
wire [17:0] VAR31;
wire [17:... | gpl-3.0 |
valptek/v586 | soc_rtl/tiny_spi.v | 6,651 | module MODULE1(
input VAR24,
input VAR7,
input VAR30,
input VAR40,
output [31:0] VAR5,
input [31:0] VAR4,
output VAR37,
input [2:0] VAR41,
output VAR42,
output VAR20,
input VAR27
);
parameter VAR10 = 8;
parameter VAR49 = 0;
parameter VAR46 = 0;
parameter VAR11 = 3;
parameter VAR18 = VAR49 ? VAR17(VAR49 / 2 - 1) : VAR10... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_merge_node_priority_encoder_workgroup.v | 2,511 | module MODULE1(VAR12, VAR3, VAR11,
VAR13, VAR14,
VAR7, VAR4, VAR10, VAR5,
VAR6);
parameter VAR9 = 10;
input VAR12, VAR3;
input VAR13, VAR14;
input VAR7, VAR4, VAR10;
input [VAR9-1:0] VAR6;
output VAR11, VAR5;
reg [VAR9-1:0] VAR2;
reg VAR8;
reg VAR1;
assign VAR11 = VAR1 ? 1'b1 : (VAR8 ? 1'b0 : ((VAR14 | VAR4) ? 1'b1 : 1... | mit |
cpulabs/mist1032sa | src/core/scheduler2/reservation_free_entry_count.v | 2,412 | module MODULE1(
input wire VAR3,
input wire VAR20,
input wire VAR35,
input wire VAR13,
input wire VAR6,
input wire VAR17,
input wire VAR31,
input wire VAR34,
input wire VAR2,
input wire VAR11,
input wire VAR22,
input wire VAR19,
input wire VAR5,
input wire VAR4,
input wire VAR30,
input wire VAR23,
output wire [3:0] VAR... | bsd-2-clause |
rkrajnc/minimig-mist | rtl/minimig/cia_timerd.v | 3,667 | module MODULE1
(
input clk, input VAR12,
input wr, input reset, input VAR6, input VAR10, input VAR2, input VAR4, input [7:0] VAR5, output reg [7:0] VAR13, input VAR3, output irq );
reg VAR1; reg VAR9; reg VAR7; reg [23:0] VAR11; reg [23:0] VAR14; reg [23:0] VAR8; reg VAR15;
always @(posedge clk)
if (VAR12) begin
if (re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3.blackbox.v | 1,264 | module MODULE1 (
VAR4,
VAR6,
VAR8,
VAR3
);
output VAR4;
input VAR6;
input VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.symbol.v | 1,288 | module MODULE1 (
input VAR6,
input VAR9,
input VAR3,
input VAR5,
output VAR2
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_ss_422to444.v | 4,235 | module MODULE1 #(
parameter VAR9 = 0,
parameter VAR11 = 16) (
input clk,
input VAR15,
input [VAR8:0] VAR2,
input [15:0] VAR17,
output reg [VAR8:0] VAR12,
output reg [23:0] VAR4);
localparam VAR8 = VAR11 - 1;
reg VAR7 = 'd0;
reg VAR18 = 'd0;
reg [VAR8:0] VAR13 = 'd0;
reg VAR6 = 'd0;
reg [7:0] VAR14;
reg [7:0] VAR5;
reg ... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_ic_local_mem_router.v | 3,904 | module MODULE1 #(
parameter integer VAR13 = 256,
parameter integer VAR42 = 6,
parameter integer VAR2 = 32,
parameter integer VAR9 = VAR13 / 8,
parameter integer VAR30 = 8
)
(
input logic VAR3,
input logic VAR17,
input logic [VAR30-1:0] VAR10,
input logic VAR22,
input logic VAR41,
input logic VAR34,
input logic [VAR13-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.blackbox.v | 1,464 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR1,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
combinatorylogic/soc | backends/c2/hw/nexys4ddr/nexys4.v | 9,162 | module MODULE3(input clk,
input rst,
input VAR19,
output VAR2,
output reg [31:0] VAR1,
output reg VAR16,
input [31:0] VAR8,
input [31:0] VAR18,
input [31:0] VAR5);
reg [7:0] VAR9;
reg VAR6;
reg VAR25;
reg [7:0] VAR13;
reg VAR29;
wire VAR28;
wire [7:0] VAR4;
wire VAR7;
reg VAR3;
VAR14 VAR14 (
.clk(clk),
.rst(~rst),
.VAR... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat_16.v | 3,839 | module MODULE1(
enable,
VAR5,
VAR16,
VAR17,
VAR15,
VAR12,
VAR3,
VAR9,
VAR1,
VAR8,
VAR7,
VAR2,
VAR19,
VAR13,
VAR10,
VAR6,
VAR11,
VAR4,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR18,
VAR14,
o10,
o11,
o12,
o13,
o14,
o15
);
input enable;
input VAR5;
input signed [27:0] VAR16;
input signed [27:0] VAR17;
input signed [27:0] VAR15;
i... | gpl-3.0 |
rohit21122012/CPU | CPU.v | 3,369 | module MODULE1( output VAR23, output VAR21,
output VAR32, output VAR41,
output VAR28, output VAR31, output VAR16, output VAR33,
output VAR46, output VAR39,
output VAR22, output VAR13,output [31:0] VAR10, output [1:0] VAR44,output reset,
input VAR30,input [1:0] VAR40, input VAR2,
input [31:0] VAR29, input [31:0] VAR35);... | mit |
parallella/oh | common/hdl/oh_pulse2pulse.v | 1,522 | module MODULE1 (
input VAR10, input din, input VAR9, input VAR2, input VAR8, output dout );
reg VAR3;
reg VAR1;
wire VAR6;
assign VAR6 = din ? ~VAR3 : VAR3;
always @ (posedge VAR9)
if(~VAR10)
VAR3 <= 1'b0;
else
VAR3 <= VAR6;
VAR5 sync(.dout (VAR7),
.din (VAR6),
.VAR4 (VAR2),
.clk (VAR8));
always @ (posedge VAR8)
if(!VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.pp.symbol.v | 1,261 | module MODULE1 (
input VAR5 ,
input VAR1 ,
output VAR4 ,
input VAR3 ,
input VAR7,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.functional.pp.v | 1,926 | module MODULE1 (
VAR5,
VAR4,
VAR3 ,
VAR1 ,
VAR12 ,
VAR8
);
input VAR5;
input VAR4;
output VAR3 ;
input VAR1 ;
input VAR12 ;
input VAR8 ;
wire VAR7 ;
wire VAR13 ;
wire VAR6;
or VAR14 (VAR7 , VAR12, VAR1 );
and VAR10 (VAR13 , VAR7, VAR8 );
VAR2 VAR11 (VAR6, VAR13, VAR5, VAR4);
buf VAR9 (VAR3 , VAR6 );
endmodule | apache-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/wasca_bb.v | 3,378 | module MODULE1 (
VAR3,
VAR10,
VAR36,
VAR21,
VAR26,
VAR37,
VAR33,
VAR35,
VAR23,
VAR16,
VAR32,
VAR25,
VAR19,
VAR14,
VAR28,
VAR27,
VAR13,
VAR12,
VAR4,
VAR11,
VAR30,
VAR20,
VAR29,
VAR1,
VAR5,
VAR24,
VAR18,
VAR6,
VAR9,
VAR15,
VAR7,
VAR8,
VAR34,
VAR38,
VAR31,
VAR22,
VAR17,
VAR2);
input VAR3;
output VAR10;
output VAR36;
input... | gpl-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam_bhv.v | 4,048 | module MODULE1
reg [VAR5-1:0] VAR4 [0:VAR1-1];
reg [VAR1-1:0] VAR3;
integer VAR2; | bsd-3-clause |
horia141/mv-parser | projects/SupLimit/SupLimit.v | 10,691 | module MODULE1;
reg VAR2;
reg reset;
wire [7:0] VAR1; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.functional.pp.v | 2,184 | module MODULE1 (
VAR5 ,
VAR15,
VAR17,
VAR4 ,
VAR2 ,
VAR9,
VAR13,
VAR14 ,
VAR7
);
output VAR5 ;
input VAR15;
input VAR17;
input VAR4 ;
input VAR2 ;
input VAR9;
input VAR13;
input VAR14 ;
input VAR7 ;
wire VAR19 ;
wire VAR10 ;
wire VAR16 ;
wire VAR3;
nand VAR12 (VAR19 , VAR17, VAR15 );
or VAR11 (VAR10 , VAR2, VAR4 );
nan... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx2mb/rtl/pcx2mb_link_ctr.v | 2,038 | module MODULE1 (
VAR4,
VAR10,
VAR2,
VAR1,
VAR5,
VAR9,
VAR8
);
output VAR4;
input VAR10;
input VAR2;
input VAR1;
input VAR5;
input VAR9;
input VAR8;
reg [1:0] VAR7;
wire VAR4;
wire VAR3;
wire VAR6;
assign VAR3 = VAR1 || (VAR5 && VAR9);
assign VAR6 = VAR8;
always @(posedge VAR10) begin
if (!VAR2) begin
VAR7 <= 2'b00;
end... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.blackbox.v | 1,336 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR6;
supply1 VAR2 ;
supply0 VAR1 ;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.blackbox.v | 1,238 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.functional.v | 1,170 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
Tao-J/nexys3MIPSSoC | biu.v | 4,365 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR24, input wire VAR19, input wire VAR5, input wire [31:0] VAR32, output reg VAR10, output reg [31:0] VAR28, output reg VAR8, output reg VAR4, output reg [3:0] VAR11, output reg [31:0] VAR16,
input wire VAR12, input wire VAR18, input wire VAR33, input wire [7:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.pp.blackbox.v | 1,478 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR8,
VAR10 ,
VAR7 ,
VAR9 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR8;
input VAR10 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/acl_pop.v | 3,361 | module MODULE1 (
VAR15,
VAR8,
VAR21,
VAR18,
VAR13,
VAR11,
VAR3,
VAR7,
VAR17,
VAR1,
VAR12,
VAR2,
VAR5
);
parameter VAR4 = 32;
parameter string VAR20 = "VAR10";
localparam VAR22 = VAR20 == "VAR16" ? 1 : 0;
input VAR15, VAR8, VAR17, VAR18, VAR2;
output VAR11, VAR7, VAR5;
input [VAR4-1:0] VAR13;
input VAR21;
input VAR3;
ou... | mit |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/rom16x2048.v | 6,530 | module MODULE1 (
address,
VAR30,
VAR17,
VAR16);
input [10:0] address;
input VAR30;
input VAR17;
output [15:0] VAR16;
wire [15:0] VAR57;
wire [15:0] VAR16 = VAR57[15:0];
VAR45 VAR11 (
.VAR42 (VAR30),
.VAR6 (VAR17),
.VAR24 (address),
.VAR51 (VAR57),
.VAR13 (1'b0),
.VAR19 (1'b0),
.VAR5 (1'b1),
.VAR55 (1'b0),
.VAR8 (1'b0),... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3_4.v | 2,184 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR6,
VAR4,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR10 ;
input VAR9 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
rkrajnc/minimig-mist | lib/altera/cyclonev_atoms.v | 149,806 | module MODULE1(
primitive VAR3 (VAR17, VAR21, VAR10, VAR5, VAR15, VAR12, VAR9);
input VAR10;
input VAR15;
input VAR12;
input VAR5;
input VAR21;
input VAR9;
output VAR17; reg VAR17;
VAR7 VAR17 = 1'b0;
VAR2
(??) ? ? 1 1 ? : ? : -; VAR11 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR11 ? : ? : 1;
1 1 ? 1 VAR11 ... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_decoder_add_endofpacket.v | 7,578 | module MODULE1 (
clk,
reset,
VAR14,
VAR10,
VAR8,
VAR9,
VAR15,
VAR4,
VAR12,
VAR13,
VAR11,
VAR6
);
parameter VAR16 = 15;
input clk;
input reset;
input [VAR16: 0] VAR14;
input VAR10;
input VAR8;
input VAR9;
input VAR15;
output VAR4;
output reg [VAR16: 0] VAR12;
output reg VAR13;
output reg VAR11;
output reg VAR6;
wire VAR... | gpl-2.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/misc/reset_generator.v | 1,824 | module MODULE1(
clk,
VAR5,
VAR1,
VAR3
);
parameter VAR2 = 1'b0;
input clk;
input VAR5;
input VAR1;
output reg VAR3 = VAR2;
reg VAR4 = VAR2;
always @(posedge clk or negedge VAR1) begin
if (!VAR1) begin
VAR3 <= VAR2;
VAR4 <= VAR2;
end else if (VAR5) begin
VAR3 <= VAR4;
VAR4 <= ~VAR2;
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.behavioral.v | 1,722 | module MODULE1 (
VAR9 ,
VAR14,
VAR3,
VAR15 ,
VAR10
);
output VAR9 ;
input VAR14;
input VAR3;
input VAR15 ;
input VAR10 ;
supply1 VAR6;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR16 ;
wire VAR8 ;
wire VAR11 ;
wire VAR4;
and VAR1 (VAR8 , VAR15, VAR10 );
nor VAR13 (VAR11 , VAR14, VAR3 );
nor VAR2 (VAR4, VAR11, VAR8);
buf VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.behavioral.v | 1,510 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR14 ,
VAR12,
VAR13
);
output VAR7 ;
input VAR6 ;
input VAR14 ;
input VAR12;
input VAR13;
supply1 VAR8;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR10 ;
wire VAR11;
wire VAR9;
nand VAR4 (VAR11, VAR13, VAR12 );
or VAR1 (VAR9, VAR14, VAR6, VAR11);
buf VAR3 (VAR7 , VAR9 );
endmodule | apache-2.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_register_slice_v1_0_axis_register_slice.v | 8,931 | module MODULE1 #
(
parameter VAR19 = "VAR33",
parameter integer VAR51 = 32,
parameter integer VAR10 = 1,
parameter integer VAR29 = 1,
parameter integer VAR23 = 1,
parameter [31:0] VAR37 = 32'hFF,
parameter integer VAR44 = 0
)
(
input wire VAR41,
input wire VAR6,
input wire VAR58,
input wire VAR45,
output wire VAR24,
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi_1.v | 2,477 | module MODULE2 (
VAR9 ,
VAR10,
VAR11,
VAR1 ,
VAR3 ,
VAR7,
VAR5,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR10;
input VAR11;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR5;
input VAR6 ;
input VAR4 ;
VAR8 VAR2 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.behavioral.v | 1,688 | module MODULE1 (
VAR15 ,
VAR3,
VAR4,
VAR10,
VAR13,
VAR16
);
output VAR15 ;
input VAR3;
input VAR4;
input VAR10;
input VAR13;
input VAR16;
supply1 VAR2;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR17 ;
wire VAR6 ;
wire VAR8;
or VAR12 (VAR17 , VAR13, VAR10 );
or VAR1 (VAR6 , VAR4, VAR3 );
nand VAR11 (VAR8, VAR6, ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks59.v | 5,231 | module MODULE1(VAR5, VAR12, VAR13);
input wire [58:0] VAR5;
input wire [58:0] VAR12;
output wire [116:0] VAR13;
wire [56:0] VAR9;
wire [58:0] VAR2;
wire [58:0] VAR3;
wire [29:0] VAR11;
wire [29:0] VAR10;
VAR1 VAR4(VAR5[29:0], VAR12[29:0], VAR2);
VAR8 VAR6(VAR5[58:30], VAR12[58:30], VAR9);
assign VAR11[28:0] = VAR5[58:3... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/dma/dma_sequencer.v | 1,980 | module MODULE1(
clk,
VAR1,
addr,
VAR17,
rd,
req,
VAR9,
ack,
VAR5,
VAR18,
VAR6,
VAR10,
VAR8,
VAR7,
VAR14,
VAR4
);
parameter VAR2 = 4;
input clk;
input VAR1;
input [20:0] addr [1:VAR2];
input [7:0] VAR17 [1:VAR2];
output reg [7:0] rd;
input [VAR2:1] req;
input [VAR2:1] VAR9;
output reg VAR18;
output reg VAR10;
output reg... | gpl-3.0 |
martinmiranda14/Digitales | Lab_6/project_5/project_5.srcs/sources_1/new/clock_divider.v | 1,120 | module MODULE1(
input clk,
input rst,
output reg VAR1
);
localparam VAR2 = 8000;
reg [63:0] VAR3;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
VAR3 <= 32'd0;
end
else if (VAR3 == (VAR2 - 32'd1))
VAR3 <= 32'd0;
else
VAR3 <= VAR3 + 32'b1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1... | apache-2.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_dcfilter.v | 5,357 | module MODULE1 #(
parameter VAR15 = 0) (
input clk,
input valid,
input [15:0] VAR88,
output VAR2,
output [15:0] VAR92,
input VAR81,
input [15:0] VAR66,
input [15:0] VAR58);
reg [15:0] VAR61 = 'd0;
reg [47:0] VAR63 = 'd0;
reg [47:0] VAR100 = 'd0;
reg VAR24 = 'd0;
reg [15:0] VAR72 = 'd0;
reg VAR23 = 'd0;
reg [15:0] VAR37... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.behavioral.pp.v | 1,246 | module MODULE1( VAR6, VAR3, VAR2, VAR5, VAR4 );
input VAR6, VAR2;
inout VAR5, VAR4;
output VAR3;
VAR8 VAR1(.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4));
VAR8 VAR7(.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/AutoFIFOPopControl.v | 2,410 | module MODULE1
(
VAR2 ,
VAR1 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR6
);
input VAR2 ;
input VAR1 ;
output VAR4 ;
input VAR5 ;
output VAR7 ;
input VAR6 ;
reg VAR3 ;
assign VAR4 = (!VAR5 && (!VAR3 || VAR6));
assign VAR7 = VAR3;
always @ (posedge VAR2)
if (VAR1)
VAR3 <= 1'b0;
else
if ((!VAR3 || VAR6))
VAR3 <= VAR4;
endmodule | gpl-3.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v | 7,922 | module MODULE1(VAR26,
VAR4,
VAR13,
VAR10,
VAR2,
VAR27,
VAR7,
VAR24,
VAR29,
VAR11,
VAR8,
VAR21,
VAR20,
VAR15,
VAR6,
VAR14,
VAR17,
VAR25,
VAR23,
VAR28,
VAR3,
VAR16,
VAR12,
VAR9,
VAR19,
VAR5,
VAR18,
VAR1,
VAR22);
input VAR26;
input VAR4;
output [63 : 0] VAR13;
output [63 : 0] VAR10;
output [63 : 0] VAR2;
output [63 : 0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba.blackbox.v | 1,381 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR6;
supply1 VAR7;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
lab1-ufba/Genius | fsm_top.v | 2,656 | module MODULE1( VAR6, VAR1, VAR26, VAR22, VAR18, VAR27, VAR44, VAR17, VAR42, VAR4, VAR19, VAR2, VAR15, VAR12, VAR16 );
input VAR6; input VAR1; input VAR26; input VAR22; input VAR18; input VAR27;
output VAR44; output VAR17; output VAR42; output VAR4; output [6:0] VAR19; output [6:0] VAR2; output [6:0] VAR15; output [6:0... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/extramfifo/nobl_if.v | 3,951 | module MODULE1
(
input clk,
input rst,
input [VAR24-1:0] VAR20,
output [VAR24-1:0] VAR10,
output reg VAR16,
output [VAR5-1:0] VAR11,
output reg VAR3,
output VAR25,
output VAR2,
output VAR21,
output reg VAR15,
input [VAR5-1:0] address,
input [VAR24-1:0] VAR14,
output reg [VAR24-1:0] VAR7,
output reg VAR6,
input write,
i... | gpl-2.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light_tx_dp.v | 4,417 | module MODULE1
parameter VAR36 = 8,
parameter VAR19 = 3, parameter VAR20 = 5
)(
input wire reset,
input wire VAR7,
input wire VAR15,
output wire VAR23,
input wire [VAR36-1:0] VAR22,
input wire VAR35,
input wire VAR31,
input wire VAR10,
output wire VAR39,
input wire VAR27,
output wire VAR12,
output wire VAR17
);
wire[VA... | gpl-3.0 |
secworks/sha1 | src/rtl/sha1.v | 7,842 | module MODULE1(
input wire clk,
input wire VAR31,
input wire VAR36,
input wire VAR22,
input wire [7 : 0] address,
input wire [31 : 0] VAR39,
output wire [31 : 0] VAR27,
output wire VAR1
);
localparam VAR6 = 8'h00;
localparam VAR33 = 8'h01;
localparam VAR11 = 8'h02;
localparam VAR12 = 8'h08;
localparam VAR28 = 0;
localp... | bsd-2-clause |
mashanz/FinalProject | Code/module/alucontrol.v | 1,356 | module MODULE1(input [1:0] VAR3, input [5:0] VAR7, output reg [2:0] MODULE1 );
parameter VAR5 = 6'b100000;
parameter VAR1 = 6'b100010;
parameter VAR2 = 6'b100100;
parameter VAR6 = 6'b100101;
parameter VAR4 = 6'b101010;
always @(*)
case (VAR3) 2'b00: MODULE1 = 3'b010; 2'b01: MODULE1 = 3'b110; 2'b10: case (VAR7) VAR5: MO... | gpl-3.0 |
zatslogic/UDI_example | udi/udi_inst_pow.v | 1,609 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input [31:0] VAR9 ,
input [15:0] VAR1 ,
output [31:0] VAR12 ,
input VAR18 ,
input [1:0] VAR16 ,
input VAR15
);
wire [31:0] VAR21 ;
wire [31:0] VAR10 ;
wire [31:0] VAR23 ;
wire [32:0] sum ;
wire [31:0] VAR11 ;
wire VAR13 ;
localparam VAR22 = 2'b00 ;
localparam VAR19 = 2'b01 ;
l... | gpl-3.0 |
lvd2/zxevo | fpga/current/video/video_modedecode.v | 3,786 | module MODULE1(
input wire clk,
input wire [ 1:0] VAR1, input wire [ 2:0] VAR10,
output reg VAR5,
output reg VAR4,
output reg VAR7, output reg VAR8,
output reg VAR6, output reg VAR3, output reg VAR9, output reg VAR11,
output reg VAR2,
output reg [ 1:0] VAR12 );
always @(posedge clk)
begin
case( VAR10 )
3'b010: VAR5 <= ... | gpl-3.0 |
praveendath92/securePUF | source/sirc_files/system.v | 17,901 | module MODULE1 #(
parameter VAR13 = 1,
parameter VAR96 = 1,
parameter VAR14 = 17,
parameter VAR75 = 13,
parameter VAR109 = 1,
parameter VAR62 = 48'hAAAAAAAAAAAA
)(
input wire VAR6, input wire VAR22,
output wire [7:0] VAR74, output wire VAR27, output wire VAR101, output wire VAR104, input wire [7:0] VAR58, input wire VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.behavioral.pp.v | 2,018 | module MODULE1 (
VAR17 ,
VAR11 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR9,
VAR3,
VAR12 ,
VAR5
);
output VAR17 ;
input VAR11 ;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR9;
input VAR3;
input VAR12 ;
input VAR5 ;
wire VAR14 ;
wire VAR7 ;
wire VAR16;
not VAR15 (VAR14 , VAR11 );
nand VAR1 (VAR7 , VAR10, VAR8, VAR2, VAR14 );
VAR6 V... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 2,212 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1479577008 : 2899645186;
endmodule | gpl-3.0 |
CospanDesign/nysa-sdio-device | rtl/generic/crc16.v | 2,325 | module MODULE1 #(
parameter VAR1 = 16'h1021,
parameter VAR2 = 16'h0000
)(
input clk,
input rst,
input bit,
output reg [15:0] VAR3
);
always @ (posedge clk) begin
if (rst) begin
VAR3 <= VAR2;
end
else begin
VAR3 <= bit ? ({VAR3[14:0], 1'b0} ^ VAR1) : {VAR3[14:0], 1'b0};
end
end
endmodule | mit |
tommythorn/yari | shared/rtl/soclib/hexled.v | 1,545 | module MODULE1 (input wire [3:0] VAR4,
input wire VAR2,
input wire VAR3,
output reg [6:0] VAR1);
always @*
if (VAR2)
VAR1 = ~7'b0000000;
else if ( VAR3 )
VAR1 = ~7'b1000000;
else case (VAR4)
4'h0: VAR1 = ~7'b0111111;
4'h1: VAR1 = ~7'b0000110;
4'h2: VAR1 = ~7'b1011011;
4'h3: VAR1 = ~7'b1001111;
4'h4: VAR1 = ~7'b1100110;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi_1.v | 2,348 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR5 ,
VAR2,
VAR8,
VAR4,
VAR9 ,
VAR10
);
output VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR8;
input VAR4;
input VAR9 ;
input VAR10 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
kevintownsend/inara-hdl-libraries | scratch_pad_a/scratch_pad_synthesis.v | 1,847 | module MODULE1(clk, in, out, sel);
parameter VAR9 = 8;
parameter VAR7 = 64;
parameter VAR13 = 512;
parameter VAR10 = 32;
parameter VAR19 = 32;
parameter VAR5 = VAR17(VAR10-1) + 1;
parameter VAR4 = VAR13 * VAR9;
parameter VAR2 = VAR17(VAR4-1);
parameter VAR18 = VAR17(VAR9-1);
input clk, in, sel;
output reg out;
reg rst;... | apache-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/ack_generator.v | 1,136 | module MODULE1(
input clk,
input reset,
input VAR12,
input VAR2,
input [7:0] VAR11,
output reg [7:0] VAR9,
output reg VAR3,
output reg VAR5
);
parameter VAR6 = 0;
parameter VAR4 = 1;
parameter VAR1 = 2;
parameter VAR8 = 3;
parameter VAR10 = 4;
reg [2:0] state, VAR7;
always @* begin
VAR7 = state;
VAR9 = 8'h00;
VAR3 = 1'... | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/message/qa_message_stream_combiner_one.v | 1,097 | module MODULE1
parameter VAR3 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR3-1:0] VAR1,
input wire VAR8,
output wire [VAR3-1:0] VAR7,
output wire VAR6
);
reg VAR2;
reg [VAR3-1:0] VAR5;
wire VAR4;
begin | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/0141074d64e361c1/gcd_block_design_processing_system7_0_0_stub.v | 5,217 | module MODULE1(VAR59, VAR29,
VAR15, VAR3, VAR4, VAR54,
VAR40, VAR19, VAR38, VAR65, VAR28,
VAR9, VAR47, VAR6, VAR51, VAR46,
VAR31, VAR26, VAR43, VAR34, VAR2,
VAR10, VAR36, VAR30, VAR27, VAR13,
VAR49, VAR35, VAR5, VAR64, VAR42,
VAR14, VAR18, VAR17, VAR56,
VAR57, VAR24, VAR52, VAR21, VAR66,
VAR16, VAR62, VAR11, VAR48, VAR... | mit |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/MM_slave.v | 2,029 | module MODULE1 (
input wire [7:0] VAR5, input wire VAR7, output wire [31:0] VAR11, input wire VAR6, input wire [31:0] VAR1, output wire VAR12, input wire VAR14, input wire VAR8, output wire VAR3 );
assign VAR11 = 32'b00000000000000000000000000000000;
reg VAR4;
reg VAR10;
reg [31:0] VAR9;
reg [31:0] VAR2;
reg VAR13;
ass... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.symbol.v | 1,420 | module MODULE1 (
input VAR1 ,
output VAR4 ,
output VAR6 ,
input VAR2,
input VAR7
);
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/ex_mem.v | 5,126 | module MODULE1(
input wire clk,
input wire rst,
input wire[31:0] VAR51,
input wire[31:0] VAR32,
input wire[31:0] VAR25,
input wire[2:0] VAR44,
input wire VAR1,
input wire[4:0] VAR19,
input wire[31:0] VAR46,
input wire[31:0] VAR35,
input wire VAR18,
input wire VAR15,
input wire[4:0] VAR9,
input wire VAR8,
input wire VAR... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.pp.blackbox.v | 1,397 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR6 ,
VAR4,
VAR7 ,
VAR11 ,
VAR2 ,
VAR5
);
output VAR10 ;
output VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR4;
input VAR7 ;
input VAR11 ;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | muxn.v | 6,436 | module MODULE1(VAR11, VAR3, VAR5, VAR10);
parameter VAR1 = 63;
output [VAR1:0] VAR10;
input [VAR1:0] VAR11;
input [VAR1:0] VAR3;
input VAR5;
reg [VAR1:0] VAR10;
always @(VAR11 or VAR3 or VAR5)
begin
if (VAR5 == 1'b1)
VAR10 = VAR3;
end
else
VAR10 = VAR11;
end
endmodule
module MODULE3(VAR11, VAR3, VAR14, VAR16, VAR5, VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.behavioral.v | 1,121 | module MODULE1( VAR4, VAR1 );
input VAR4;
output VAR1;
VAR3 VAR2(.VAR4(VAR4),.VAR1(VAR1));
VAR3 VAR5(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai.pp.blackbox.v | 1,436 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR4,
VAR2,
VAR8 ,
VAR6
);
output VAR9 ;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR2;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
colinww/spi-core-generator | example/results_verilog/spi_reg.v | 13,303 | module MODULE1(
VAR72, VAR73, VAR59, VAR24,
VAR34, VAR39, VAR62, VAR65,
VAR3, VAR42, VAR26, VAR64,
VAR10, VAR63, VAR76,
VAR69, VAR13, VAR36, VAR6,
VAR21, VAR29, VAR48, VAR61,
VAR33, VAR50, VAR47, VAR5,
VAR18, VAR23, VAR35, VAR66,
VAR51, VAR27, VAR40,
VAR7, VAR46, VAR2, VAR20,
VAR19, VAR1, VAR22,
VAR58, VAR31, VAR60, VA... | gpl-3.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,649 | module MODULE1 (
VAR10,
VAR23,
clk,
VAR28,
VAR20,
VAR27,
VAR38,
VAR12,
VAR59,
VAR18,
VAR58,
VAR11,
VAR33,
VAR36,
VAR57,
VAR48,
VAR37,
VAR25,
VAR54,
VAR50,
VAR35,
VAR43,
VAR4,
VAR29,
VAR44,
VAR15,
VAR1,
VAR24,
VAR60,
VAR53,
VAR26,
VAR40,
VAR9,
VAR30,
VAR14,
VAR39
)
;
output [ 37: 0] VAR35;
output VAR43;
output VAR4;
out... | apache-2.0 |
KestrelComputer/kestrel | cores/SIA/rtl/verilog/sia_wb.v | 5,549 | module MODULE1(
input VAR21,
input VAR8,
input [3:1] VAR18,
input VAR15,
input VAR24,
input VAR28,
input [1:0] VAR16,
input [15:0] VAR10,
output [15:0] VAR12,
output VAR4,
output VAR23,
output VAR19,
output [4:0] VAR6,
output VAR13,
output VAR32,
output [2:0] VAR27,
output VAR2,
output [4:0] VAR11,
output [19:0] VAR26,... | mpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v | 57,374 | module MODULE1 #
(
parameter VAR60 = 100,
parameter VAR130 = "135", parameter VAR196 = 64,
parameter VAR115 = "VAR237",
parameter VAR12 = "0", parameter VAR453 = 3, parameter VAR136 = 2, parameter VAR62 = "8", parameter VAR296 = "VAR114", parameter VAR46 = "VAR152", parameter VAR61 = 1, parameter VAR308 = 5,
parameter ... | mit |
linuxbest/lzs | decode/rtl/verilog/decode_ctl.v | 6,085 | module MODULE1 (
VAR27, VAR53, VAR35, VAR11, VAR31,
clk, rst, VAR5, VAR26, VAR47, VAR49,
VAR50
);
input clk,
rst,
VAR5,
VAR26;
input [12:0] VAR47;
input VAR49;
input VAR50;
output [3:0] VAR27;
output VAR53;
output [7:0] VAR35;
output VAR11;
output VAR31;
reg VAR53;
reg [3:0] VAR27;
parameter [2:0]
VAR20 = 3'h0,
VAR3 = ... | gpl-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/EmbededSystem/MEM_256B.v | 3,706 | module MODULE1 (inout [31:0] VAR5, output reg VAR18, input VAR6, VAR21, input [7:0] VAR16, input VAR7,VAR8);
reg [31:0] VAR19;
reg [7:0] VAR17[0:255];wire [7:0] VAR1[0:3];
reg [7:0] VAR14;
assign VAR1[0] = VAR5[31:24];
assign VAR1[1] = VAR5[23:16];
assign VAR1[2] = VAR5[15:8];
assign VAR1[3] = VAR5[7:0];
assign VAR5 = ... | apache-2.0 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/Verilog_L1.v | 21,244 | module MODULE3(VAR2) ;
endmodule
[]
module MODULE2 (VAR10, VAR15, VAR4, VAR7) ;
input VAR10, VAR15; output VAR4, VAR7;
assign VAR4 = VAR10 ^ VAR15;assign VAR7 = VAR10 & VAR15;
endmodule
assign VAR4 = VAR10 ^ VAR15;
assign [delay] VAR8 VAR1 VAR3 = VAR11;
[]
[]
module MODULE1 (VAR10, VAR15, VAR5, VAR14);
input VAR10, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.behavioral.v | 38,795 | module MODULE1 (
VAR56,
VAR14,
VAR25,
VAR45,
VAR30,
VAR7,
VAR6,
VAR42,
VAR48,
VAR8,
VAR49,
VAR18,
VAR59,
VAR50,
VAR21,
VAR2,
VAR46,
VAR55,
VAR29,
VAR57,
VAR70,
VAR34,
VAR16,
VAR51,
VAR63,
VAR1,
VAR32,
VAR67,
VAR61,
VAR65,
VAR58,
VAR15
);
wire VAR69;
wire VAR74;
wire VAR72;
supply1 VAR31;
supply1 VAR22;
supply1 VAR35;
s... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_rank_common.v | 20,487 | module MODULE1 #
(
parameter VAR45 = 100,
parameter VAR105 = "VAR52",
parameter VAR89 = 40,
parameter VAR16 = 4,
parameter VAR100 = 4,
parameter VAR48 = 2,
parameter VAR31 = 20,
parameter VAR62 = 2,
parameter VAR57 = 4,
parameter VAR28 = 39,
parameter VAR115 = 640000
)
(
VAR4, VAR35, VAR40, VAR93, VAR110,
VAR15, VAR106... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.functional.pp.v | 1,783 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3 ,
VAR8,
VAR12,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR8;
input VAR12;
input VAR1 ;
input VAR4 ;
wire VAR11 ;
wire VAR9;
and VAR13 (VAR11 , VAR7, VAR3 );
VAR6 VAR5 (VAR9, VAR11, VAR8, VAR12);
buf VAR10 (VAR2 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.blackbox.v | 1,297 | module MODULE1 (
VAR4,
VAR1 ,
VAR6,
VAR8
);
output VAR4;
input VAR1 ;
input VAR6;
input VAR8 ;
supply1 VAR3;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.behavioral.pp.v | 1,147 | module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/jp_vpi/verilog/vpi_debug_module.v | 47,487 | module MODULE1
(output reg VAR7,
output reg VAR100,
output reg VAR96,
input VAR84,
input VAR97,
input enable);
parameter VAR57 = 1;
parameter VAR61 = 50; parameter VAR64 = 0; parameter VAR30 = 0;
localparam VAR41 = 4;
localparam VAR48 = 4'b0000;
localparam VAR89 = 4'b0001;
localparam VAR19 = 4'b0010;
localparam VAR9 = ... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_fp_sincos_fused.v | 1,548 | module MODULE1(VAR6, VAR15, VAR10, VAR12, VAR13, enable);
input VAR6, VAR15, enable;
input [31:0] VAR10;
output [31:0] VAR12; output [31:0] VAR13;
VAR7 VAR5(
.VAR8(VAR6),
.reset(~VAR15),
.enable(enable),
.VAR2(VAR10[31]),
.VAR14(VAR10[30:23]),
.VAR11(VAR10[22:0]),
.VAR16(VAR12[31]),
.VAR9(VAR12[30:23]),
.VAR4(VAR12[22:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap.blackbox.v | 1,191 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/fake_rgmii_phy.v | 1,625 | module MODULE1
(input [3:0] VAR6,
input VAR20,
input VAR26,
output [3:0] VAR27,
output VAR39,
output VAR4,
inout VAR34,
inout VAR32,
input VAR1);
reg [7:0] VAR24;
reg VAR35;
reg VAR23;
wire VAR3;
wire [7:0] VAR36;
wire VAR38;
wire VAR28;
wire VAR14;
assign VAR3 = VAR26;
wire [3:0] VAR31 = {1'b1, 1'b0, 1'b1, 1'b1};
alwa... | apache-2.0 |
freecores/eco32 | fpga/src/eco32.v | 10,025 | module MODULE1(VAR104,
VAR10,
VAR118,
VAR51,
VAR70,
VAR100,
VAR89,
VAR67,
VAR131,
VAR63,
VAR119,
VAR33,
VAR56,
VAR29,
VAR24,
VAR159,
VAR117,
VAR2,
VAR38,
VAR96,
VAR72,
VAR92,
VAR30,
VAR1,
VAR9,
VAR124,
VAR8,
VAR81,
VAR120,
VAR6,
VAR32,
VAR147,
VAR37,
VAR14,
VAR19,
VAR41,
VAR91,
VAR15,
VAR20,
VAR80,
VAR144,
VAR114,
VAR1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.blackbox.v | 1,295 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR1;
supply1 VAR3;
supply0 VAR6;
endmodule | apache-2.0 |
jairov4/accel-oil | solution_spartan3/impl/verilog/sample_iterator_get_offset.v | 50,086 | module MODULE1 (
VAR34,
VAR135,
VAR116,
VAR77,
VAR117,
VAR54,
VAR37,
VAR113,
VAR127,
VAR71,
VAR70,
VAR36,
VAR49,
VAR125,
VAR52,
VAR136,
VAR81,
VAR32,
VAR13,
VAR50,
VAR56,
VAR82,
VAR89,
VAR26,
VAR131,
VAR63,
VAR130,
VAR43,
VAR1,
VAR133,
VAR92,
VAR42,
VAR76,
VAR80,
VAR75,
VAR120,
VAR35,
VAR79,
VAR68
);
input VAR34;
input... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2.functional.pp.v | 1,745 | module MODULE1( VAR17, VAR28, VAR23, VAR21, VAR26, VAR25, VAR20, VAR10, VAR9 );
input VAR21, VAR23, VAR26, VAR17, VAR28, VAR20, VAR10, VAR9;
output VAR25;
not VAR11( VAR22, VAR26 );
wire VAR5;
not VAR24( VAR5, VAR23 );
wire VAR16;
not VAR15( VAR16, VAR17 );
wire VAR27;
and VAR19( VAR27, VAR5, VAR16 );
wire VAR7;
not VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp_2.v | 2,329 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR1 ,
VAR9,
VAR3 ,
VAR10 ,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR6 ;
input VAR1 ;
input VAR9;
input VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR7 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODU... | apache-2.0 |
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