repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.behavioral.v | 1,355 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR8;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR9 ;
wire VAR5;
not VAR7 (VAR5, VAR1 );
buf VAR2 (VAR6 , VAR5 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9434/axi_ad9434_if.v | 7,350 | module MODULE1 (
VAR26,
VAR25,
VAR1,
VAR19,
VAR53,
VAR12,
VAR58,
VAR18,
VAR49,
VAR10,
VAR57,
VAR13,
VAR65,
VAR50,
VAR67,
VAR30,
VAR40,
VAR44,
VAR5,
VAR11,
VAR59,
VAR32,
VAR14,
VAR42,
VAR20,
VAR31,
VAR61);
parameter VAR47 = 0; parameter VAR56 = "VAR21";
localparam VAR17 = VAR47;
localparam VAR66 = 0;
input VAR26;
input ... | gpl-3.0 |
alanachtenberg/CSCE-350 | Project3/RegisterFile.v | 1,701 | module MODULE1(VAR1, VAR7, VAR5, VAR8, VAR3, VAR9, VAR2, VAR4, VAR6);
output [31:0] VAR1;
output [31:0] VAR7;
input [31:0] VAR5;
input [4:0] VAR8, VAR3, VAR9;
input VAR2, VAR4, VAR6;
reg [31:0] VAR10 [0:31];
always @(posedge VAR6)
begin
VAR10[0]=0;
VAR10[1]=0;
VAR10[2]=0;
VAR10[3]=0;
VAR10[4]=0;
VAR10[5]=0;
VAR10[6]=0;... | gpl-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/CLS_Scanner_Module.v | 3,630 | module MODULE1
parameter VAR14 = 50000000 )
(
input [1:0] VAR7,
output [9:0] VAR3,
input VAR12
);
localparam VAR2 = 1000;
wire VAR8;
VAR13
.VAR14( VAR14 )
)
VAR5
(
.VAR7( VAR7 ),
.VAR6( VAR8 ),
.VAR12( VAR12 )
);
wire VAR9;
VAR10
.VAR14( VAR14 ), .VAR4( VAR2 ) )
VAR11
(
.VAR1( VAR9 ),
.VAR12( VAR12 )
);
begin
begin
beg... | mit |
tommythorn/yari | shared/rtl/soclib/pdm.v | 1,202 | module MODULE1(clk, VAR1, VAR2);
parameter VAR3 = 16;
input wire clk;
input wire [VAR3-1:0] VAR1;
output wire VAR2;
reg [VAR3+1:0] VAR4 = 0;
assign VAR2 = ~VAR4[VAR3+1];
always @(posedge clk) VAR4 <= VAR4 + {VAR2,VAR2,VAR1};
endmodule | gpl-2.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_top.v | 52,187 | module MODULE1 #
(
parameter VAR185 = "VAR5",
parameter integer VAR144 = 0,
parameter integer VAR43 = 1,
parameter integer VAR205 = 0,
parameter integer VAR14 = 32,
parameter integer VAR189 = 32,
parameter integer VAR66 = 64,
parameter integer VAR8 = 1,
parameter integer VAR27 = 1,
parameter integer VAR26 = 0,
paramete... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v | 5,207 | module MODULE1(
VAR15, VAR13, VAR10, VAR8, VAR2, VAR12, VAR14, VAR9
);
parameter VAR5 = 68;
parameter VAR17 = VAR16;
parameter VAR6 = VAR1;
input VAR15; input VAR13; input [VAR5-1:0] VAR10; input VAR8; input VAR2; output [VAR5-1:0] VAR12; output VAR14; output VAR9;
reg [VAR5-1:0] VAR4 [VAR6-1:0];
reg [VAR5-1:0] VAR12;
... | gpl-2.0 |
mshr-h/verilog_building_block | rtl/altera/ram_sp_altera.v | 2,191 | module MODULE1
parameter VAR7=8,
parameter VAR30=12,
parameter VAR19="./memory.VAR26"
) (
input tri1 VAR48,
input wire VAR5,
input wire [VAR30-1:0] address,
input wire [VAR7-1:0] VAR12,
output wire [VAR7-1:0] VAR17
);
VAR28 VAR50
(
.VAR41 ( address ),
.VAR20 ( VAR48 ),
.VAR2 ( VAR12 ),
.VAR13 ( VAR5 ),
.VAR18 ( VAR17 )... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/pcie_reset_delay_v6.v | 3,948 | module MODULE1 # (
parameter VAR10 = "VAR8",
parameter VAR5 = 0, parameter VAR7 = 1
)
(
input wire VAR2,
input wire VAR4,
output VAR1
);
localparam VAR3 = (VAR10 == "VAR8") ? ((VAR5 == 1) ? 20: (VAR5 == 0) ? 20 : 21) : 2;
reg [7:0] VAR12;
reg [7:0] VAR11;
reg [7:0] VAR6;
wire [23:0] VAR9;
assign VAR9 = {VAR6, VAR11, VA... | lgpl-3.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/EX_MEM.v | 4,433 | module MODULE1
(
input clk,
input rst,
input en,
input [VAR37-1:0] VAR26,
input [VAR37-1:0] VAR11,
input VAR36,
input VAR18,
input VAR32,
input VAR33,
input VAR21,
input VAR1,
input VAR24,
input [4:0] VAR25,
input [VAR37-1:0] VAR38,
input [4:0] VAR23,
input [VAR37-1:0] VAR15,
output [VAR37-1:0] VAR14,
output [VAR37-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.behavioral.pp.v | 1,922 | module MODULE1 (
VAR15 ,
VAR12 ,
VAR14 ,
VAR1 ,
VAR8,
VAR10,
VAR13 ,
VAR6
);
output VAR15 ;
input VAR12 ;
input VAR14 ;
input VAR1 ;
input VAR8;
input VAR10;
input VAR13 ;
input VAR6 ;
wire VAR7 ;
wire VAR9;
VAR2 VAR11 (VAR7 , VAR12, VAR14, VAR1 );
VAR5 VAR4 (VAR9, VAR7, VAR8, VAR10);
buf VAR3 (VAR15 , VAR9 );
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.pp.blackbox.v | 1,414 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR6,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu.v | 29,942 | module MODULE1(
output VAR166,
output VAR64,
output VAR377,
output VAR81,
output VAR367,
output VAR58,
output VAR132,
output VAR311,
output VAR136,
input [VAR188-1:0] VAR46,
input VAR419,
input [VAR290-1:0] VAR222,
input [VAR7-1:0] VAR164,
input VAR272,
input VAR184,
input VAR262,
output [VAR416-1:0] VAR318,
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.functional.v | 1,852 | module MODULE1 (
VAR3,
VAR9,
VAR16 ,
VAR10 ,
VAR15 ,
VAR14 ,
VAR7 ,
VAR6 ,
VAR11
);
input VAR3;
input VAR9;
output VAR16 ;
input VAR10 ;
input VAR15 ;
input VAR14 ;
input VAR7 ;
input VAR6 ;
input VAR11 ;
wire VAR1 ;
wire VAR4;
VAR5 VAR2 (VAR1 , VAR10, VAR15, VAR14, VAR7, VAR6, VAR11 );
VAR12 VAR13 (VAR4, VAR1, VAR3, V... | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_channel_error_detect.v | 6,004 | module MODULE1
(
VAR3,
VAR9,
VAR2,
VAR10,
VAR7,
VAR6,
VAR5,
VAR4
);
input [0:3] VAR3;
input [0:3] VAR9;
input [0:3] VAR2;
input VAR10;
input VAR7;
output VAR6;
output VAR5;
output VAR4;
reg VAR6;
reg VAR5;
reg VAR4;
reg [0:3] VAR12;
reg [0:3] VAR1;
wire VAR11;
wire VAR13;
wire VAR8;
always @(posedge VAR10)
begin
VAR12 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv_16.v | 2,009 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR4,
VAR7,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR6 ;
input VAR4;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR4;
supply0 VAR7;... | apache-2.0 |
monotone-RK/FACE | CQ/src/riffa/tx_multiplexer_128.v | 18,831 | module MODULE1
parameter VAR93 = 128,
parameter VAR11 = 12,
parameter VAR68 = 5, parameter VAR24 = "VAR40"
)
(
input VAR10,
input VAR98,
input [VAR11-1:0] VAR8, input [(VAR11*VAR51)-1:0] VAR65, input [(VAR11*VAR41)-1:0] VAR91, input [(VAR11*VAR93)-1:0] VAR37, output [VAR11-1:0] VAR64, output [VAR11-1:0] VAR108,
input [... | mit |
jas0n1ee/THU-DSD | FB/cpu_jtag_debug_module_wrapper.v | 9,444 | module MODULE1 (
VAR3,
VAR37,
clk,
VAR46,
VAR45,
VAR40,
VAR13,
VAR10,
VAR39,
VAR36,
VAR23,
VAR59,
VAR47,
VAR53,
VAR41,
VAR55,
VAR34,
VAR24,
VAR7,
VAR12,
VAR35,
VAR14,
VAR1,
VAR43,
VAR56,
VAR54,
VAR52,
VAR25,
VAR15,
VAR11,
VAR27,
VAR18,
VAR6,
VAR16,
VAR28,
VAR22
)
;
output [ 37: 0] VAR35;
output VAR14;
output VAR1;
outp... | mit |
lowRISC/flexpret | HardRegister.v | 4,827 | module MODULE1(VAR16, VAR10, VAR5, VAR9, VAR3, VAR4) ;
parameter VAR12 = 32,
VAR7 = {VAR12{1'VAR1}},
VAR6 = 0,
VAR2 = 0,
VAR13 = {VAR12{1'b0}},
VAR14 = {VAR12{1'b1}};
input VAR16, VAR9, VAR10, VAR5;
input [VAR12-1:0] VAR3;
output reg [VAR12-1:0] VAR4 = VAR7 ;
generate if (VAR6) begin:VAR15
if (VAR2) begin:VAR11
always ... | bsd-3-clause |
vad-rulezz/megabot | minsoc/bench/verilog/minsoc_bench.v | 40,759 | module MODULE1();
localparam VAR43 = 1'b1;
localparam VAR43 = 1'b0;
localparam VAR43 = 1'b1;
reg VAR31, reset;
wire VAR13;
wire VAR37;
wire VAR22;
wire VAR39;
wire VAR27;
wire VAR2;
wire VAR29;
reg VAR44;
wire VAR46;
wire [1:0] VAR15;
wire VAR25;
reg VAR34;
reg VAR7;
reg VAR11;
wire VAR1;
reg VAR9;
wire VAR4;
wire VAR2... | gpl-2.0 |
iori-yja/ball_detector | pll_bb.v | 13,136 | module MODULE1 (
VAR4,
VAR1,
VAR3,
VAR2,
VAR5);
input VAR4;
output VAR1;
output VAR3;
output VAR2;
output VAR5;
endmodule | mit |
dnet/proxmark3 | fpga/fpga_hf.v | 6,140 | module MODULE1(
input VAR14, output VAR53, input VAR92, input VAR2,
input VAR10, input VAR35, input VAR21,
output VAR9, output VAR94,
output VAR27, output VAR84, output VAR46, output VAR72,
input [7:0] VAR63, output VAR57, output VAR5,
output VAR79, output VAR13, input VAR16, output VAR37,
input VAR74, input VAR86,
out... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/Top_10/synth/Top.v | 5,625 | module MODULE1 (
input wire VAR30, input wire reset, input wire [6:0] VAR7, output wire [31:0] VAR12, input wire VAR38, input wire VAR9, input wire VAR41, input wire [31:0] VAR1, output wire [3:0] VAR44, output wire [31:0] VAR35, output wire [31:0] VAR45, output wire [7:0] VAR6, output wire [2:0] VAR18, output wire [1:... | mit |
unihd-cag/openhmc | rtl/building_blocks/rams/openhmc_ram.v | 4,113 | module MODULE1 #(
parameter VAR4 = 78, parameter VAR7 = 9, parameter VAR8 = 0
) (
input wire clk,
input wire VAR3,
input wire [VAR4-1:0] VAR13,
input wire [VAR7-1:0] VAR6,
input wire VAR10,
input wire [VAR7-1:0] VAR5,
output wire [VAR4-1:0] VAR2
);
wire [VAR4-1:0] VAR1;
generate
if (VAR8 == 0)
begin
assign VAR2 = VAR1;... | lgpl-3.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/new/Key.v | 1,505 | module MODULE1
( input clk,
input rst,
input VAR7,
input VAR8,
input VAR9,
input VAR6,
output reg[7:0] VAR5
);
reg [31:0]VAR1;
reg VAR4;
reg VAR3;
reg VAR2;
reg VAR10;
always@(posedge clk or negedge rst) begin
if(!rst) begin
VAR1 <= 0;
VAR5 <= 8'b0;
VAR4 <= 0;
VAR3 <= 0;
VAR2 <= 0;
VAR10 <= 0;
end
else begin
if(VAR1 ==... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.behavioral.pp.v | 2,824 | module MODULE1 (
VAR18 ,
VAR7 ,
VAR12 ,
VAR15 ,
VAR29 ,
VAR13,
VAR22 ,
VAR25 ,
VAR5 ,
VAR11
);
output VAR18 ;
input VAR7 ;
input VAR12 ;
input VAR15 ;
input VAR29 ;
input VAR13;
input VAR22 ;
input VAR25 ;
input VAR5 ;
input VAR11 ;
wire VAR9 ;
wire VAR6 ;
wire VAR20 ;
reg VAR1 ;
wire VAR24 ;
wire VAR28 ;
wire VAR8 ;
w... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pcie_pipe_misc.v | 8,383 | module MODULE1 #
(
parameter VAR16 = 0 )
(
input wire VAR29 , input wire VAR3 , input wire VAR24 , input wire VAR11 , input wire [2:0] VAR18 , input wire VAR7 ,
output wire VAR13 , output wire VAR25 , output wire VAR26 , output wire VAR22 , output wire [2:0] VAR6 , output wire VAR8 ,
input wire VAR30 , input wire VAR17... | gpl-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_macstatus.v | 12,771 | module MODULE1(
VAR32, VAR27, VAR21, VAR4, VAR25, VAR53,
VAR26, VAR8, VAR42, VAR22, VAR14, VAR45, VAR33,
VAR50, VAR12, VAR17, VAR47,
VAR54, VAR10, VAR46, VAR30, VAR52, VAR3,
VAR28, VAR36, VAR18, VAR20, VAR24, VAR9, VAR15,
VAR35, VAR39, VAR41, VAR43, VAR49, VAR55, VAR11,
VAR29, VAR56, VAR23, VAR5, VAR16, VAR34, VAR13,
V... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/eth_axis_rx.v | 15,291 | module MODULE1 #
(
parameter VAR3 = 8,
parameter VAR24 = (VAR3>8),
parameter VAR2 = (VAR3/8)
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR19,
input wire [VAR2-1:0] VAR15,
input wire VAR6,
output wire VAR26,
input wire VAR5,
input wire VAR9,
output wire VAR18,
input wire VAR17,
output wire [47:0] VAR20,
... | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_alt_ddrx_controller_wrapper.v | 17,975 | module MODULE1 (
VAR59,
VAR49,
VAR69,
VAR4,
VAR62,
VAR47,
VAR107,
VAR117,
VAR29,
VAR76,
VAR12,
VAR114,
VAR52,
VAR99,
VAR32,
VAR44,
VAR15,
VAR113,
VAR2,
VAR116,
VAR55,
VAR80,
VAR102,
VAR10,
VAR9,
VAR111,
VAR45,
VAR70,
VAR87,
VAR97,
VAR57,
VAR11,
VAR30,
VAR27,
VAR112,
VAR43,
VAR110,
VAR14,
VAR36,
VAR22,
VAR101,
VAR66,
VA... | apache-2.0 |
Masahiro000Shimasaki/NeuralNetwork | Hardware/Perceptron_xor/fp_multiplier.v | 34,685 | module MODULE1
(
VAR100,
VAR68,
VAR8,
VAR40) ;
input VAR100;
input [31:0] VAR68;
input [31:0] VAR8;
output [31:0] VAR40;
reg VAR91;
reg VAR34;
reg VAR46;
reg VAR96;
reg VAR32;
reg VAR9;
reg VAR77;
reg VAR24;
reg [9:0] VAR18;
reg [9:0] VAR94;
reg [9:0] VAR86;
reg VAR75;
reg VAR26;
reg VAR62;
reg VAR81;
reg [23:0] VAR31;... | mit |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_pixel/bg_pixel_stub.v | 1,289 | module MODULE1(VAR2, VAR4, VAR1, VAR3, VAR5)
;
input VAR2;
input [0:0]VAR4;
input [16:0]VAR1;
input [11:0]VAR3;
output [11:0]VAR5;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.pp.symbol.v | 1,294 | module MODULE1 (
input VAR6 ,
input VAR7 ,
output VAR3 ,
input VAR4 ,
input VAR5,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
hoglet67/opc | opc6/opc6cpu.v | 5,785 | module MODULE1(input[15:0] din,input clk,input VAR70,input[1:0] VAR42,input VAR50,output VAR7,output VAR6,output VAR36,output[15:0] dout,output[15:0] address,output VAR74);
parameter VAR43=5'h0,VAR51=5'h1,VAR76=5'h2,VAR59=5'h3,VAR5=5'h4,VAR33=5'h5,VAR48=5'h6,VAR31=5'h7,VAR65=5'h8,VAR10=5'h9,VAR23=5'hA,VAR26=5'hB,VAR67=... | gpl-3.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/duc.v | 2,747 | module MODULE1(input VAR10,
input reset,
input enable,
input [3:0] VAR21,
input [3:0] VAR27,
output VAR28,
input [31:0] VAR18,
input [15:0] VAR24,
input [15:0] VAR26,
output [15:0] VAR15,
output [15:0] VAR41
);
parameter VAR25 = 16;
parameter VAR35 = 16;
wire [15:0] VAR29, VAR20;
wire [31:0] VAR3;
wire VAR12, VAR16;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.pp.symbol.v | 1,341 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR2 ,
output VAR8 ,
input VAR6 ,
input VAR7,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.behavioral.v | 1,396 | module MODULE1 (
VAR3,
VAR7,
VAR4,
VAR6
);
output VAR3;
input VAR7;
input VAR4;
input VAR6;
supply1 VAR11;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
wire VAR9;
xnor VAR10 (VAR9, VAR7, VAR4, VAR6 );
buf VAR2 (VAR3 , VAR9 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/upd77c25_datram.v | 10,764 | module MODULE1 (
VAR56,
VAR36,
VAR29,
VAR4,
VAR45,
VAR13,
VAR8,
VAR47,
VAR51);
input [9:0] VAR56;
input [10:0] VAR36;
input VAR29;
input [15:0] VAR4;
input [7:0] VAR45;
input VAR13;
input VAR8;
output [15:0] VAR47;
output [7:0] VAR51;
tri1 VAR29;
tri0 VAR13;
tri0 VAR8;
wire [15:0] VAR50;
wire [7:0] VAR55;
wire [15:0] V... | gpl-2.0 |
ptracton/Picoblaze | library/wb_uart/uart_sync_flops.v | 6,050 | module MODULE1
(
VAR1,
VAR9,
VAR7,
VAR2,
VAR10,
VAR4
);
parameter VAR5 = 1;
parameter VAR6 = 1;
parameter VAR8 = 1'b0;
input VAR1; input VAR9; input VAR7; input VAR2; input [VAR6-1:0] VAR10; output [VAR6-1:0] VAR4;
reg [VAR6-1:0] VAR4;
reg [VAR6-1:0] VAR3;
always @ (posedge VAR9 or posedge VAR1)
begin
if (VAR1)
VAR3 <=... | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/decoder.v | 10,520 | module MODULE1 (
input wire [VAR50] VAR9, input wire [VAR4] VAR72, input wire VAR14,
input wire [VAR4] VAR5, input wire [VAR4] VAR61, output wire [VAR43] VAR73, output wire [VAR43] VAR22,
input wire VAR60, input wire [VAR43] VAR19, input wire VAR25, input wire [VAR13] VAR44, input wire VAR54, input wire [VAR43] VAR45, ... | mit |
wgml/sysrek | skin_color_segm/ipcore_dir/counter19.v | 23,257 | module MODULE1 (
clk, VAR65, VAR46, VAR23
);
input clk;
input VAR65;
input VAR46;
output [18 : 0] VAR23;
wire \VAR34/VAR96 ;
wire \VAR34/VAR25 ;
wire \VAR51/VAR8 ;
wire \VAR51/VAR40 ;
wire \VAR51/VAR48<17>VAR22 ;
wire \VAR51/VAR48<16>VAR22 ;
wire \VAR51/VAR48<15>VAR22 ;
wire \VAR51/VAR48<14>VAR22 ;
wire \VAR51/VAR48<13... | gpl-2.0 |
merckhung/zet | cores/zet/rtl-syn/fpga_zet_top.v | 2,587 | module MODULE1 (
input VAR6,
input VAR28,
input [15:0] VAR23,
output reg [15:0] VAR13,
output reg [19:1] VAR8,
output reg VAR10,
output reg VAR18, output reg [ 1:0] VAR11,
output reg VAR3,
output reg VAR21,
input VAR7,
input VAR29,
output reg VAR20,
input [ 3:0] VAR15,
output reg [19:0] VAR9
);
reg [15:0] VAR22;
wire [... | gpl-3.0 |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/DE1_TOP.v | 9,844 | module MODULE1
(
VAR75, VAR160, VAR166, VAR70, VAR99, VAR167, VAR95, VAR10, VAR169, VAR5, VAR68, VAR122, VAR118, VAR31, VAR134, VAR32, VAR179, VAR48, VAR88, VAR54, VAR165, VAR72, VAR89, VAR26, VAR38, VAR17,
VAR123, VAR36, VAR126, VAR115,
VAR93, VAR135, VAR182, VAR12, VAR152, VAR78, VAR46 );
input [1:0] VAR75; input [1:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.functional.v | 1,912 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR3 ,
VAR1 ,
VAR12 ,
VAR13
);
input VAR10 ;
input VAR6 ;
output VAR3 ;
input VAR1 ;
input VAR12 ;
input VAR13;
wire VAR11 ;
wire VAR8 ;
wire VAR5;
not VAR9 (VAR8 , VAR13 );
not VAR14 (VAR5, VAR1 );
VAR15 VAR2 VAR7 (VAR11 , VAR12, VAR5, VAR8, VAR10, VAR6);
buf VAR4 (VAR3 , VAR11 );
endmo... | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegN.v | 2,208 | module MODULE1(VAR8, VAR6, VAR2, VAR5, VAR4);
parameter VAR3 = 1;
parameter VAR9 = { VAR3 {1'b0} } ;
input VAR8;
input VAR6;
input VAR4;
input [VAR3 - 1 : 0] VAR5;
output [VAR3 - 1 : 0] VAR2;
reg [VAR3 - 1 : 0] VAR2;
always@(posedge VAR8)
begin
if (VAR6 == VAR1)
VAR2 <= VAR7 VAR9;
end
else
begin
if (VAR4)
VAR2 <= VAR7 ... | mit |
Gilberto-Lopez/Arquitectura-Computadoras | Practica5/Divisor.v | 1,214 | module MODULE1(
input wire [31:0] VAR6,
input wire [31:0] VAR2,
output reg [31:0] VAR5,
output reg VAR3
);
reg [31:0] VAR4 = 32'b0;
reg [31:0] VAR8 = 32'b0;
reg [31:0] VAR7 = 32'b0;
integer VAR1 = 0;
always @* begin
if(!VAR2[30:0]) begin
VAR5 = 32'b0;
VAR3 = 1'b1;
end
else if(!VAR6[30:0]) begin
VAR5 = 32'b0;
VAR3 = 1'b... | lgpl-3.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_incr.v | 3,462 | module MODULE1
(VAR3, VAR5);
parameter VAR1 = 3;
parameter [0:VAR1-1] VAR4 = 0;
parameter [0:VAR1-1] VAR7 = (1 << VAR1) - 1;
localparam VAR9 = VAR7 - VAR4 + 1;
localparam VAR10 = VAR6(VAR9);
input [0:VAR1-1] VAR3;
output [0:VAR1-1] VAR5;
wire [0:VAR1-1] VAR5;
wire VAR2;
assign VAR2 = &VAR3[(VAR1-VAR10):VAR1-1];
wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.pp.symbol.v | 1,271 | module MODULE1 (
input VAR5 ,
input VAR4 ,
output VAR2 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
karatekid/ultrasonic-fountain | hardware/src/hcsr04.v | 2,446 | module MODULE1 #(
parameter VAR5 = 500,
parameter VAR11 = 3000000
)(
input rst,
input clk,
input VAR15,
input VAR7,
input VAR3,
output reg [15:0] VAR1,
output reg valid,
output reg VAR19
);
localparam VAR16 = 3,
VAR17 = 16;
localparam VAR14 = 3'd0,
VAR13 = 3'd1,
VAR10 = 3'd2,
VAR12 = 3'd3,
VAR23 = 3'd4;
reg [VAR17-1:0]... | gpl-3.0 |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | Verilog_AES/AES/Ram.v | 1,429 | module MODULE1
parameter VAR3 = 4,
parameter VAR5 = 8,
parameter VAR4 = 64
)(
input clk,
input[VAR3-1:0] VAR1,
input[VAR3-1:0] VAR9,
input VAR13,
input VAR15,
input[VAR5-1:0] VAR8,
input[VAR5-1:0] VAR12,
output reg[VAR5-1:0] VAR7,
output reg[VAR5-1:0] VAR6
);
reg [VAR5-1:0] VAR14 [0:VAR4-1];
always@(posedge clk)
begin:... | lgpl-2.1 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/tdm_slave_if.v | 4,566 | module MODULE1(
clk, rst, VAR4, VAR3, VAR1,
din, dout
);
input clk;
input rst;
input VAR4;
input VAR3;
output VAR1;
input [7:0] din;
output [7:0] dout;
reg [2:0] VAR2;
reg [7:0] dout;
reg VAR1;
always @(posedge clk or posedge rst)
if (rst)
VAR2 <= 3'b000;
else if (VAR4)
VAR2 <= 3'b001;
else
VAR2 <= VAR2 + 1;
always @(p... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.blackbox.v | 1,230 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_srl_register.v | 3,001 | module MODULE1 #
(
parameter VAR2 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR2-1:0] VAR15,
input wire VAR3,
output wire VAR10,
input wire VAR8,
input wire VAR16,
output wire [VAR2-1:0] VAR13,
output wire VAR1,
input wire VAR12,
output wire VAR7,
output wire VAR11
);
reg [VAR2+2-1:0] VAR5[1:0];
reg VAR9[1:0]... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/cmd/sd_cmd_layer.v | 8,548 | module MODULE1 (
input clk,
input rst,
output VAR55,
input VAR5,
input VAR43,
input [15:0] VAR48,
input [31:0] VAR53,
output reg VAR27,
output reg [7:0] VAR30,
input VAR6,
output reg VAR16,
input [5:0] VAR28,
input [31:0] VAR18,
input VAR29,
output [127:0] VAR33,
input VAR3,
input VAR54,
input [23:0] VAR10,
output reg ... | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/asyn_256_139_bb.v | 5,970 | module MODULE1 (
VAR3,
VAR6,
VAR2,
VAR1,
VAR8,
VAR7,
VAR5,
VAR4);
input VAR3;
input [138:0] VAR6;
input VAR2;
input VAR1;
input VAR8;
input VAR7;
output [138:0] VAR5;
output [7:0] VAR4;
tri0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b_1.v | 2,147 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR7,
VAR3,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR7;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR8 VAR6 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR4,
VAR9
);
output VAR5 ... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_issp_0/altera_in_system_sources_probes_171/synth/altsource_probe_top.v | 2,966 | module MODULE1
parameter VAR17 = "VAR7", parameter VAR4 = "VAR13",
parameter VAR3 = "VAR10", parameter VAR9 = 0, parameter VAR1 = 4746752 + VAR9, parameter VAR14 = 4,
parameter VAR8 = "VAR13", parameter VAR2 = 1, parameter VAR15= 1, parameter VAR16 = "0", parameter VAR11 = "VAR5" )
(
input [VAR2 - 1 : 0] VAR21, output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3_lp.v | 2,161 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR4,
VAR9,
VAR5 ,
VAR1
);
output VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR9;
input VAR5 ;
input VAR1 ;
VAR8 VAR3 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
rad-/65C816_SoftCore | 65816_Interface_System.srcs/sources_1/bd/Interface_Master_BD/ip/Interface_Master_BD_auto_pc_0/synth/Interface_Master_BD_auto_pc_0.v | 13,174 | module MODULE1 (
VAR99,
VAR44,
VAR113,
VAR20,
VAR18,
VAR59,
VAR34,
VAR8,
VAR33,
VAR68,
VAR48,
VAR17,
VAR102,
VAR72,
VAR10,
VAR1,
VAR39,
VAR49,
VAR74,
VAR41,
VAR26,
VAR65,
VAR52,
VAR112,
VAR21,
VAR22,
VAR83,
VAR58,
VAR3,
VAR109,
VAR76,
VAR63,
VAR54,
VAR25,
VAR98,
VAR4,
VAR89,
VAR75,
VAR94,
VAR7,
VAR107,
VAR27,
VAR95,
VA... | gpl-3.0 |
bubnikv/omniasdrbasicfirmware | basic.cydsn/ToneSequencer/ToneSequencer.v | 1,458 | module MODULE1(input clk, input VAR3, input VAR5, input VAR4, input VAR1, output [1:0] mux);
reg [1:0] VAR2;
always @(posedge clk)
begin
if (VAR2 == 0)
begin
VAR2 <= VAR3 ? 1 : 0;
end
else if ((VAR2 == 1 && VAR5) || (VAR2 == 2 && VAR4))
begin
VAR2 <= VAR3 ? 2 : 3;
end
else if (VAR2 == 3 && VAR1)
begin
VAR2 <= VAR3 ? 1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.functional.pp.v | 1,580 | module MODULE1 (
VAR3,
VAR5,
VAR4 ,
VAR9
);
input VAR3;
input VAR5;
output VAR4 ;
output VAR9 ;
wire VAR2;
pullup VAR6 (VAR2);
VAR8 VAR7 (VAR4 , VAR2, VAR3, VAR5);
pulldown VAR1 (VAR9 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/trash.v | 55,284 | module MODULE1 (VAR30,VAR32,VAR24,VAR23,VAR3);
output [0:127] VAR3;
input [0:127] VAR30;
input [0:127] VAR32;
input [0:1] VAR24;
input [0:4] VAR23;
integer VAR27;
reg [0:127] VAR3;
reg [0:127] VAR11;
reg [0:15] VAR20;
reg [0:15] VAR5;
reg [0:15] VAR6;
reg [0:15] VAR22;
reg [0:15] VAR14;
reg [0:15] VAR10;
reg [0:15] VAR... | mit |
gbraad/minimig-de1 | rtl/minimig/Cart.v | 4,039 | module MODULE1
(
input wire clk,
input wire VAR18,
input wire VAR16,
input wire [24-1:1] VAR5,
input wire [24-1:1] VAR7,
input wire VAR25,
input wire VAR21,
input wire VAR8,
input wire VAR20,
input wire [32-1:0] VAR3,
input wire VAR26,
input wire VAR12,
input wire VAR19,
output wire [16-1:0] VAR24,
output reg VAR17 = 1... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_rdmatctl.v | 19,191 | module MODULE1(
VAR3, VAR60, VAR94,
VAR64, VAR89,
VAR21, VAR29, VAR2,
VAR1, VAR12,
VAR7, VAR32,
VAR24, VAR18, VAR71,
VAR139, VAR97, VAR22, VAR45,
VAR27, VAR86,
VAR56,
VAR23, VAR119, VAR107,
VAR90, VAR142,
VAR146, VAR120, VAR46,
VAR99, VAR135, VAR63,
VAR124, VAR47, VAR92, VAR117, VAR52, VAR88, VAR50,
VAR80, VAR113,
VAR4... | gpl-2.0 |
Digilent/vivado-library | ip/PWM_Analyzer_1.0/hdl/pulseLength.v | 4,152 | module MODULE1 (
input wire clk,
input wire reset,
output reg [30:0] VAR7,
output reg [30:0] VAR6,
output reg [31:0] VAR8,
input wire VAR2
);
reg [1:0] VAR13, VAR11;
parameter
VAR10 = 2'b00,
VAR9 = 2'b01,
VAR5 = 2'b10,
VAR4 = 2'b11;
reg VAR3;
reg [30:0] VAR1, VAR12; | mit |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/TERASIC_ADC_READ.v | 1,403 | module MODULE1(
clk,
VAR2,
VAR20,
VAR13,
VAR16,
VAR14,
VAR18,
VAR4,
VAR12,
VAR9,
VAR3
);
input clk;
input VAR2;
input VAR20;
input VAR13;
output reg [15:0] VAR16;
input VAR14;
input [15:0] VAR18;
output VAR4;
output VAR12;
input VAR9;
output VAR3;
reg VAR19;
wire VAR8;
wire [11:0] VAR15;
reg [2:0] VAR5;
always @ (posed... | gpl-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_port_channel_gate_128.v | 7,054 | module MODULE1 #(
parameter VAR10 = 9'd128,
parameter VAR23 = 8,
parameter VAR1 = VAR10+1
)
(
input VAR32,
input VAR5, output [VAR1-1:0] VAR31, output VAR35, input VAR11,
input VAR3, input VAR36, output VAR13, input VAR28, input [31:0] VAR22, input [30:0] VAR17, input [VAR10-1:0] VAR40, input VAR20, output VAR19 );
reg... | bsd-3-clause |
amerc/TCP3 | NEXYS3/user_design.v | 279,730 | module MODULE1(VAR30,VAR45,VAR4,VAR51,VAR64,VAR11,VAR24,VAR26,VAR16,VAR65,VAR31,clk,rst,VAR41,VAR8,VAR37,VAR59,VAR50,VAR62,VAR33,VAR44,VAR13,VAR66);
integer VAR10;
real VAR54;
input [15:0] VAR30;
input [15:0] VAR45;
input [15:0] VAR4;
input [15:0] VAR51;
input VAR64;
input VAR11;
input VAR24;
input VAR26;
input VAR16;
... | mit |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/mod.v | 2,935 | module MODULE1(
VAR17, VAR1, VAR32, VAR3, VAR23, VAR33,
VAR25, VAR9, VAR19, VAR31, VAR10, VAR8,
VAR6, VAR2, VAR14, VAR22
);
input VAR25;
input VAR9;
input VAR19;
wire VAR26 = VAR9;
input [23:0] VAR31;
output VAR17;
input [63:0] VAR10;
input VAR8;
input VAR6;
input VAR2;
output VAR1;
output [63:0] VAR32;
output VAR3;
in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.pp.blackbox.v | 1,347 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR6 ,
VAR1 ,
VAR2 ,
VAR3,
VAR4,
VAR7 ,
VAR5
);
output VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.blackbox.v | 2,911 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR10 ,
VAR17 ,
VAR2 ,
VAR37 ,
VAR27,
VAR25 ,
VAR5 ,
VAR14 ,
VAR30 ,
VAR6 ,
VAR21 ,
VAR3 ,
VAR20 ,
VAR22 ,
VAR8 ,
VAR18 ,
VAR11 ,
VAR12 ,
VAR31 ,
VAR15 ,
VAR24 ,
VAR26 ,
VAR33 ,
VAR34 ,
VAR19
);
input VAR1 ;
input VAR16 ;
input VAR10 ;
input VAR17 ;
input VAR2 ;
input VAR37 ;
input VAR27... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/hdl/verilog/doHistStretch.v | 62,393 | module MODULE1 (
VAR158,
VAR99,
VAR193,
VAR239,
VAR179,
VAR50,
VAR303,
VAR177,
VAR330,
VAR329,
VAR77,
VAR207,
VAR147,
VAR97,
VAR254,
VAR78,
VAR108,
VAR165,
VAR12,
VAR285,
VAR93,
VAR327,
VAR273,
VAR321,
VAR244,
VAR175,
VAR20,
VAR94,
VAR234,
VAR116,
VAR42,
VAR192,
VAR320,
VAR70,
VAR219,
VAR289,
VAR127,
interrupt
);
param... | gpl-3.0 |
wamgoo/FPGA-Imaging-Library | Connector/ColorGray2Channels/srcs/ColorGray2Channels.v | 1,581 | module MODULE1(
VAR4,
VAR7
);
parameter VAR8 = 8;
parameter VAR3 = 3;
input[VAR8 - 1 : 0] VAR4;
output[VAR3 * VAR8 - 1 : 0] VAR7;
genvar VAR5;
generate
for (VAR5 = 0; VAR5 < VAR3; VAR5 = VAR5 + 1) begin: VAR2
assign VAR7[VAR1 : VAR6] = VAR4;
end
endgenerate
endmodule | lgpl-2.1 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_crossbar.v | 4,329 | module MODULE1
(VAR11, VAR8, VAR1);
parameter VAR5 = 5;
parameter VAR22 = 5;
parameter VAR16 = 32;
parameter VAR19 = VAR20;
input [0:VAR5*VAR22-1] VAR11;
input [0:VAR5*VAR16-1] VAR8;
output [0:VAR22*VAR16-1] VAR1;
wire [0:VAR22*VAR16-1] VAR1;
wire [0:VAR22*VAR5-1] VAR21;
VAR6
.VAR17(VAR5))
VAR25
(.VAR15(VAR11),
.VAR27(... | gpl-2.0 |
lloves/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_COUNT_TO_64.v | 2,708 | module MODULE1(
input clk,
input rst,
input VAR1,
input VAR3,
output reg [5:0] VAR2
);
wire [5:0] VAR4;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
VAR2 = 6'h00;
end
else begin
case({VAR1,VAR3})
2'b00: VAR2 = VAR4;
2'b01: VAR2 = VAR4;
2'b10: VAR2 = VAR4 - 1;
2'b11: VAR2 = VAR4 + 1;
default: VAR2 = 6'h00;
... | bsd-2-clause |
skyfex/svo-raycaster | orlink/hw/bench.v | 3,999 | module MODULE1
(
);
reg clk;
reg rst;
reg VAR10;
reg VAR13;
reg [7:0] VAR12;
wire [7:0] VAR3;
reg VAR4;
reg VAR9;
output VAR8;
output VAR17;
output VAR15;
output [1:0] VAR11;
output VAR7;
wire [7:0] VAR14;
assign VAR3 = VAR13 ? VAR12 : 8'VAR16;
VAR6 VAR1
(
.VAR2(rst),
.VAR5(clk),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4)... | mit |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/erx_protocol.v | 12,535 | module MODULE1 (
VAR10, VAR37, VAR17, VAR18,
VAR32, VAR20, VAR6,
VAR42, VAR38,
reset, VAR19, VAR11, VAR43, VAR1,
VAR39
);
input reset;
input VAR19; input [7:0] VAR11;
input [63:0] VAR43;
output VAR10; output VAR37;
output VAR17;
output VAR18;
output [1:0] VAR32;
output [3:0] VAR20;
output [31:0] VAR6;
output [31:0] VAR... | gpl-3.0 |
nrclark/async_fifo | hdl/sync_fifo.v | 2,388 | module MODULE1 #(
parameter VAR17 = 8,
parameter VAR14 = 16
)(
input wire VAR9,
input wire VAR19,
input wire VAR4,
input wire VAR12,
input wire [VAR17-1:0] VAR7,
output wire VAR20,
output wire VAR2,
output reg [VAR17-1:0] VAR5 = 0
);
parameter VAR1 = VAR18(VAR14);
reg [VAR1-1:0] VAR8 = 0;
reg [VAR1-1:0] VAR16 = 0;
reg ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a_2.v | 2,248 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR3 ,
VAR1 ,
VAR6,
VAR2,
VAR7 ,
VAR10
);
output VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR6;
input VAR2;
input VAR7 ;
input VAR10 ;
VAR9 VAR5 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
olajep/oh | src/common/hdl/oh_reg1.v | 1,279 | module MODULE1 #(parameter VAR7 = 1 )
( input VAR6, input clk, input [VAR7-1:0] in, output [VAR7-1:0] out );
localparam VAR2 = VAR1;
generate
if(VAR2)
begin : VAR5
VAR4 VAR8 [VAR7-1:0] (.VAR6(VAR6),
.clk(clk),
.in(in[VAR7-1:0]),
.out(out[VAR7-1:0]));
end
else
begin
reg [VAR7-1:0] VAR3;
always @ (posedge clk or negedge ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.functional.v | 1,344 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
wire VAR1;
not VAR4 (VAR1, VAR3 );
buf VAR2 (VAR5 , VAR1 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController/src/m_axi_write.v | 15,404 | module MODULE1 # (
parameter VAR52 = 32,
parameter VAR20 = 64,
parameter VAR69 = 1,
parameter VAR97 = 1,
parameter VAR80 = 1,
parameter VAR13 = 1
)
(
input VAR90,
input VAR44,
output [VAR69-1:0] VAR21,
output [VAR52-1:0] VAR84,
output [7:0] VAR91,
output [2:0] VAR62,
output [1:0] VAR55,
output [1:0] VAR45,
output [3:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.blackbox.v | 1,191 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
jacgoudsmit/P8X32A_Emulation | P8X32A_Nexys4/src/top.v | 5,759 | module MODULE1
(
input VAR24, VAR79 VAR9
input VAR76, else
input VAR17, VAR78
inout [31:0] VAR64, output [7:0] VAR19, output VAR74, output VAR13, output VAR11, output VAR53 );
reg VAR49;
wire [7:0] VAR35;
wire [31:0] VAR40, VAR56, VAR26;
wire VAR70, VAR12, clk;
reg [31:0] VAR67;
reg VAR23;
wire VAR60;
reg [7:0] VAR18;
... | gpl-3.0 |
racerxdl/LVDS-7-to-1-Serializer | src/video_lvds.v | 2,162 | module MODULE1(
input VAR8,
input VAR28,
input VAR26,
input VAR41,
input [5:0] VAR27,
input [5:0] VAR20,
input [5:0] VAR24,
output VAR22,
output VAR5,
output VAR32,
output VAR9,
output VAR36,
output VAR3,
output VAR11,
output VAR29
);
wire VAR10, VAR12, VAR37,VAR14,VAR1,VAR2, VAR38, VAR7;
wire [20:0] VAR30;
VAR18 #(.VA... | mit |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_ctlif.v | 2,952 | module MODULE1 #(
parameter VAR20 = 4'h0,
parameter VAR1 = 26
) (
input VAR19,
input VAR10,
input [13:0] VAR21,
input VAR6,
input [31:0] VAR7,
output reg [31:0] VAR2,
output reg VAR16,
output reg [10:0] VAR12,
output reg [10:0] VAR8,
output reg [10:0] VAR5,
output reg [10:0] VAR11,
output reg [10:0] VAR15,
output reg [... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_pdl_even.v | 4,038 | module MODULE1(
VAR3, VAR9,
VAR19, VAR11,
VAR14, VAR10,
VAR1, VAR17,
VAR15, VAR8,
VAR6, VAR12,
VAR13, VAR16,
VAR20, VAR7,
VAR18, VAR2,
VAR4, VAR5
);
output VAR3 ;
output VAR9 ;
output VAR19 ;
output VAR11 ;
output VAR14 ;
output VAR10 ;
output VAR1 ;
output VAR17 ;
output VAR15 ;
output VAR8 ;
input VAR6;
input VAR12;
... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_dc_top.v | 12,420 | module MODULE1(
clk, rst,
VAR11, VAR7, VAR31, VAR53, VAR10, VAR28, VAR68,
VAR57, VAR1, VAR70,
VAR6,
VAR39, VAR38, VAR19,
VAR56, VAR77, VAR3, VAR14,
VAR45, VAR59, VAR71, VAR69, VAR35,
VAR13, VAR49, VAR9,
VAR2, VAR30, VAR18
);
parameter VAR52 = VAR66;
input clk;
input rst;
output [VAR52-1:0] VAR11;
output [31:0] VAR7;
ou... | gpl-2.0 |
svofski/mahponk | src/soundnik.v | 1,633 | module MODULE1(clk, VAR14, VAR4, VAR10, VAR8);
parameter VAR7 = 98; parameter VAR12 = 196; parameter VAR6 = 144;parameter VAR9 = 0;
input clk; output VAR14;
input VAR4;
input [3:0] VAR10;
input VAR8;
reg [7:0] VAR13;
reg [3:0] VAR5;
always @(posedge clk) begin
VAR13 <= VAR13 + 1;
if (VAR13 == 0) begin
VAR5 <= VAR5 + 1;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.symbol.v | 1,365 | module MODULE1 (
input VAR7,
input VAR8,
input VAR1,
input VAR5,
input VAR6,
output VAR2
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/DECODER.v | 99,101 | module MODULE1 ( VAR325, VAR259, VAR477, VAR62, VAR233, VAR28, VAR405, VAR156, VAR39, VAR47, VAR115, VAR338, VAR185,
VAR50, VAR98, VAR284, VAR319, VAR273, VAR392, VAR364, VAR365,
VAR114, VAR237, VAR384, VAR122, VAR66, VAR373, VAR310, VAR239, VAR432, VAR12, VAR11, VAR413, VAR75, VAR301, VAR444,
VAR278, VAR91, VAR379, VA... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/z80/zclock.v | 5,027 | module MODULE1(
input VAR28,
input VAR12,
input VAR21,
input VAR6,
output reg VAR7,
output reg VAR13,
output reg VAR1,
input wire VAR27,
input [1:0] VAR24,
output reg [1:0] VAR3,
input wire VAR17,
input wire VAR15,
input wire VAR14,
input VAR26,
input VAR18 );
reg VAR9;
wire VAR10; wire VAR22;
reg [2:0] VAR8;
reg VAR11... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.behavioral.v | 1,802 | module MODULE1( VAR5, VAR8, VAR2, VAR6, VAR4 );
input VAR2, VAR8, VAR6, VAR4;
output VAR5;
VAR3 VAR1(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4));
VAR3 VAR7(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/correlator.v | 8,565 | module MODULE1
parameter VAR5 = 120'hb1a191817161b0a090807060,
parameter VAR7 = VAR44 - 1,
parameter VAR42 = 3)
(
input VAR14, input rst,
input VAR41, input VAR19,
input VAR21,
input VAR10, input VAR11, output reg VAR33 = 0,
input [4:0] VAR38,
input [VAR7:0] VAR1,
output reg [VAR7:0] VAR37,
input VAR36, input en, input... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai_1.v | 2,202 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR8 ,
VAR3,
VAR5,
VAR2
);
output VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR3;
input VAR5;
input VAR2;
VAR1 VAR4 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7 ,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR8 ... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dc_top.v | 10,482 | module MODULE1(
clk, rst,
VAR74, VAR37, VAR44, VAR40, VAR12, VAR77, VAR26,
VAR64, VAR41, VAR29,
VAR10,
VAR53, VAR4, VAR20,
VAR31, VAR14, VAR51, VAR27,
VAR54, VAR55, VAR18, VAR22, VAR32,
VAR13, VAR1, VAR73,
VAR58, VAR70, VAR2
);
parameter VAR39 = VAR59;
input clk;
input rst;
output [VAR39-1:0] VAR74;
output [31:0] VAR37... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_pr_pp_pkg_sn.blackbox.v | 1,519 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR4 ,
VAR3,
VAR2 ,
VAR6 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3;
input VAR2 ;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha_2.v | 2,184 | module MODULE2 (
VAR2,
VAR7 ,
VAR5 ,
VAR8 ,
VAR1,
VAR6,
VAR10 ,
VAR3
);
output VAR2;
output VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR6;
input VAR10 ;
input VAR3 ;
VAR9 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODULE2... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_serdes_1sgx_x4_12500.v | 19,463 | module MODULE1 (
VAR34,
VAR29,
VAR81,
VAR35,
VAR78,
VAR62,
VAR76,
VAR3,
VAR123,
VAR10,
VAR114,
VAR22,
VAR41,
VAR122,
VAR84,
VAR113,
VAR47,
VAR63,
VAR71,
VAR39);
input [0:0] VAR34;
input [0:0] VAR29;
input [0:0] VAR81;
input [0:0] VAR35;
input [3:0] VAR78;
input [3:0] VAR62;
input [3:0] VAR76;
input [3:0] VAR3;
input [3... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3.pp.blackbox.v | 1,297 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR5,
VAR2,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR5;
input VAR2;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
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