repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_stub.v | 5,946 | module MODULE1(VAR54, VAR42, VAR28, VAR25,
VAR75, VAR66, VAR19, VAR55, VAR40, VAR73,
VAR67, VAR5, VAR2, VAR47, VAR11, VAR9,
VAR45, VAR34, VAR36, VAR16, VAR43, VAR10, VAR30,
VAR61, VAR49, VAR44, VAR18, VAR60, VAR22,
VAR72, VAR1, VAR74, VAR62, VAR15, VAR32, VAR65,
VAR77, VAR56, VAR41, VAR39, VAR46, VAR50, VAR33,
VAR4, VA... | mit |
mindrobots/P8X32A_Emulation | P8X32A_Pipistrello/src/dig.v | 5,097 | module MODULE1
(
input VAR32,
output [7:0] VAR27,
input VAR8, input VAR16,
input [31:0] VAR5, output [31:0] VAR15, output [31:0] VAR19,
output [7:0] VAR25 );
reg [31:0] VAR7;
always @(posedge VAR8)
if (VAR32)
VAR7 <= VAR7 + 1'b1;
reg VAR10;
always @(posedge VAR8 or negedge VAR32)
if (!VAR32)
VAR10 <= 1'b0;
else
VAR10 <... | gpl-3.0 |
chaohu/Daily-Learning | Digital-Logic/lab/lab4/lab4_1/lab4_1_1/lab4_1.srcs/sources_1/new/lab4_1.v | 1,615 | module MODULE1(
input VAR11,VAR7,VAR9,VAR1,VAR14,VAR12,VAR6,VAR2,
output reg VAR4,VAR3,VAR10,VAR8,VAR13
);
reg [3:0] VAR5;
always @(posedge VAR11 or negedge VAR2 or negedge VAR6)
begin
if(VAR2 == 0)
begin
VAR5 = 0;
{VAR4,VAR3,VAR10,VAR8} = VAR5;
VAR13 = 1;
end
else if(VAR6 == 0)
begin
VAR5 = {VAR9,VAR1,VAR14,VAR12};
{V... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_sq_rx_fifo.v | 5,906 | module MODULE1 # (
parameter VAR54 = 128,
parameter VAR48 = 4
)
(
input clk,
input VAR17,
input VAR50,
input [VAR48-1:0] VAR42,
input [VAR54-1:0] VAR7,
input [VAR48:0] VAR25,
input [VAR48:0] VAR15,
input [6:4] VAR33,
output VAR20,
input VAR13,
output [VAR54-1:0] VAR55,
input VAR27,
input [6:4] VAR4,
output VAR45
);
loc... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v | 20,787 | module MODULE1 (
clk,
reset,
VAR42,
VAR109,
VAR26,
VAR3,
VAR95
);
parameter VAR67 = 18;
parameter VAR55 = 27;
parameter VAR119 = 14;
localparam VAR74 = 33;
input clk;
input reset;
input VAR42;
input VAR109;
input [VAR67-1:0] VAR26; output VAR3;
output [VAR67-1:0] VAR95;
localparam VAR38 = 18; localparam VAR82 = 36; loc... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.pp.blackbox.v | 1,309 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6,
VAR3,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/SpecialMultDescale.v | 4,649 | module MODULE1(
input [31:0] VAR1,
input [31:0] VAR14,
input [7:0] VAR10,
input VAR18,
input VAR9,
input [31:0] VAR7,
input reset,
input VAR16,
output reg VAR5 = 1'b0,
output reg [32:0] VAR20,
output reg [32:0] VAR12,
output reg [32:0] VAR3,
output reg [7:0] VAR22,
output reg VAR21,
output reg [31:0] VAR2
);
wire VAR15... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_ic_to_avm.v | 2,625 | module MODULE1 #(
parameter integer VAR15 = 256,
parameter integer VAR21 = 6,
parameter integer VAR20 = 32,
parameter integer VAR5 = VAR15 / 8,
parameter integer VAR19 = 1
)
(
output logic VAR10,
output logic VAR8,
output logic [VAR15-1:0] VAR22,
output logic [VAR21-1:0] VAR16,
output logic [VAR20-1:0] VAR7,
output log... | mit |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkSepRouterAllocator.v | 24,728 | module MODULE1(VAR8,
VAR145,
VAR30,
VAR44,
VAR76,
VAR61,
VAR91);
input VAR8;
input VAR145;
input VAR30;
input [24 : 0] VAR44;
input VAR76;
output [24 : 0] VAR61;
input VAR91;
wire [24 : 0] VAR61;
reg VAR69;
wire VAR50, VAR123;
reg VAR93;
wire VAR138, VAR82;
reg VAR25;
wire VAR111, VAR28;
reg VAR101;
wire VAR115, VAR89;... | gpl-2.0 |
freecores/rc4-prbs | rc4.v | 3,586 | module MODULE1(clk,rst,VAR13,VAR14,VAR6);
input clk; input rst; input [7:0] VAR14; output VAR13; output [7:0] VAR6;
wire clk, rst; reg VAR13;
wire [7:0] VAR14;
reg [7:0] VAR2[0:VAR7-1];
reg [7:0] VAR11[0:256];
reg [10:0] VAR3;
reg [3:0] VAR9;
reg [7:0] VAR12; reg [7:0] VAR8;
reg [7:0] VAR6;
always @ (posedge clk or pos... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/sync_bits.v | 3,395 | module MODULE1
(
input [VAR5-1:0] in,
input VAR1,
input VAR3,
output [VAR5-1:0] out
);
parameter VAR5 = 1;
parameter VAR2 = 1;
reg [VAR5-1:0] VAR4 = 'h0;
reg [VAR5-1:0] VAR6 = 'h0;
always @(posedge VAR3)
begin
if (VAR1 == 1'b0) begin
VAR4 <= 'b0;
VAR6 <= 'b0;
end else begin
VAR4 <= in;
VAR6 <= VAR4;
end
end
assign out ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn_1.v | 2,150 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR7,
VAR1,
VAR3,
VAR5 ,
VAR9
);
output VAR8 ;
input VAR6 ;
input VAR7;
input VAR1;
input VAR3;
input VAR5 ;
input VAR9 ;
VAR4 VAR2 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8 ,
VAR6 ,
VAR7
);
output VAR8 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi_2.v | 2,361 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR9 ,
VAR10,
VAR8,
VAR5 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR10;
input VAR8;
input VAR5 ;
input VAR3 ;
VAR1 VAR11 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/dvi_gen/dvi_gen_top.v | 17,131 | module MODULE1 (
input wire VAR89,
input wire VAR57,
input wire [15:0] VAR58,
input wire [15:0] VAR117,
output wire [3:0] VAR68,
output wire [3:0] VAR130,
output wire VAR114,
input wire VAR112,
input wire VAR13,
input wire VAR8,
input wire [7:0] VAR12,
input wire [7:0] VAR83,
input wire [7:0] VAR15
);
wire VAR98;
wire ... | gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/multi_QI/multi_QI_stub.v | 1,202 | module MODULE1(VAR4, VAR1, VAR3, VAR2)
;
input VAR4;
input [15:0]VAR1;
input [15:0]VAR3;
output [31:0]VAR2;
endmodule | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_pmu.v | 25,263 | module MODULE1(
input VAR4,
input reset,
input VAR152,
input VAR205,
input VAR206,
input VAR219,
output VAR207,
output VAR54,
output VAR66,
output VAR95,
output VAR46,
input VAR110,
input [3:0] VAR93,
output [3:0] VAR91,
input VAR33,
input [31:0] VAR48,
output [31:0] VAR132,
input VAR103,
input [31:0] VAR221,
output [3... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.behavioral.v | 1,024 | module MODULE1( VAR4 );
output VAR4;
VAR2 VAR1(.VAR4(VAR4));
VAR2 VAR3(.VAR4(VAR4)); | apache-2.0 |
sudov/options-accel | zedboard/xillinux-eval-zedboard-1.1/system/pcores/xillyvga_v1_00_a/hdl/verilog/xillyvga_core.v | 1,509 | module MODULE1
(
input VAR30,
input [31:0] VAR36,
input VAR31,
input VAR22,
input [31:0] VAR50,
input VAR20,
input VAR42,
input VAR44,
input [31:0] VAR45,
input [3:0] VAR21,
input VAR8,
input VAR32,
input VAR34,
input VAR57,
input VAR29,
input VAR17,
input [1:0] VAR54,
input VAR6,
input [31:0] VAR33,
input VAR38,
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.behavioral.pp.v | 2,173 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR18 ,
VAR1 ,
VAR6 ,
VAR2,
VAR11,
VAR10 ,
VAR16
);
output VAR12 ;
input VAR3 ;
input VAR18 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR11;
input VAR10 ;
input VAR16 ;
wire VAR9 ;
wire VAR5 ;
wire VAR14 ;
wire VAR7;
and VAR19 (VAR9 , VAR1, VAR6 );
and VAR8 (VAR5 , VAR3, VAR18 );
or ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.blackbox.v | 1,252 | module MODULE1 (
VAR2,
VAR3,
VAR7,
VAR5
);
output VAR2;
input VAR3;
input VAR7;
input VAR5;
supply1 VAR1;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | DDR3/phy/phy_rdctrl_sync.v | 7,493 | module MODULE1 #
(
parameter VAR9 = 100
)
(
input clk,
input VAR10, input VAR8,
input [4:0] VAR14,
input VAR3,
input VAR22,
output reg VAR15,
output reg VAR17,
output reg VAR21 );
localparam VAR4 = 10;
wire VAR12;
wire VAR7;
wire VAR1;
reg [VAR4-1:0] VAR18;
assign VAR12 = (VAR8) ? VAR3 : VAR22;
VAR6 VAR19
(
.VAR2 (VAR1... | gpl-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_multiplexer.v | 16,278 | module MODULE1
parameter VAR49 = 128,
parameter VAR37 = 12,
parameter VAR55 = 5,
parameter VAR27 = "VAR44",
parameter VAR71 = 10
)
(
input VAR6,
input VAR40,
input [VAR37-1:0] VAR14, input [(VAR37*VAR1)-1:0] VAR61, input [(VAR37*VAR28)-1:0] VAR18, input [(VAR37*VAR49)-1:0] VAR59, output [VAR37-1:0] VAR66, output [VAR37... | bsd-3-clause |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_tx_buf.v | 8,070 | module MODULE1
(
input VAR14,
input rst,
input VAR15,
input VAR29,
input VAR22,
input VAR18,
input VAR32,
input [7:0] VAR25,
input VAR21,
input VAR8,
output [7:0] VAR27,
output VAR12
);
parameter VAR6 = 16'd40000;
wire [8:0] VAR11 = {VAR8, VAR25};
wire VAR16 = VAR21 && VAR32;
wire [8:0] VAR5;
wire VAR10;
wire VAR26;
VA... | mit |
osrf/wandrr | firmware/motor_controller/fpga/meganode.v | 16,612 | module MODULE1
( input VAR193, input VAR107, input VAR75, input VAR213, input VAR83,
output VAR78, output VAR244, inout VAR267, output [3:0] VAR60,
output [1:0] VAR276, output [3:0] VAR332,
input [1:0] VAR52, input [3:0] VAR284,
output [4:0] VAR164, output [4:0] VAR144,
inout [4:0] VAR302, inout [4:0] VAR258,
input VAR... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_clock_and_reset.v | 4,262 | module MODULE2 #
( parameter
VAR19 = 4,
VAR9 = 1,
VAR15 = 4,
VAR17 = 1
)
(
VAR12,
VAR18,
VAR2,
VAR10,
VAR8,
VAR16
);
input VAR12;
input VAR18;
input VAR2;
input VAR10;
output [VAR9 - 1 : 0] VAR8;
output [VAR17 - 1 : 0] VAR16;
MODULE1 #(
.VAR1 (VAR19),
.VAR3 (VAR9)
) VAR4 (
.VAR7 (VAR18),
.clk (VAR12),
.VAR11 (VAR8)
);
... | apache-2.0 |
jotego/jt12 | hdl/jt12_op.v | 9,597 | module MODULE1(
input rst,
input clk,
input VAR20 ,
input [9:0] VAR21,
input [9:0] VAR32, input [2:0] VAR6, input VAR55,
input VAR12,
input VAR37,
input VAR11,
input VAR60,
input VAR44,
input VAR57,
input VAR51,
input VAR52,
input VAR59,
input VAR68,
input VAR23,
output signed [ 8:0] VAR63,
output signed [13:0] VAR69
)... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_bank_timer.v | 61,887 | module MODULE1 #
( parameter
VAR98 = 2,
VAR69 = 4,
VAR256 = 16, VAR224 = 3, VAR225 = "VAR11",
VAR111 = 2, VAR6 = 1,
VAR148 = 1,
VAR243 = 4,
VAR65 = 4,
VAR267 = 8,
VAR158 = 0, VAR123 = 0,
VAR241 = 4,
VAR161 = 4,
VAR162 = 3,
VAR250 = 4,
VAR193 = 10,
VAR13 = 4,
VAR201 = 5,
VAR47 = 6,
VAR196 = 3,
VAR213 = 5,
VAR25 = 4,
VAR... | gpl-3.0 |
AndreaCorallo/KPU | rtl/kpu/reg.v | 11,631 | module MODULE1(
input VAR3,
input VAR1,
input VAR2,
input wire in,
output reg out); | gpl-3.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkUART.v | 123,471 | module MODULE1(VAR124,
VAR277,
VAR161,
VAR94,
VAR165,
VAR248,
VAR45,
VAR56,
VAR335,
VAR323,
VAR315,
VAR117,
VAR322,
VAR61,
VAR227,
VAR194,
VAR18,
VAR198,
VAR284,
VAR336,
VAR337,
VAR281,
VAR264,
VAR206,
VAR180,
VAR131,
VAR92,
VAR112,
VAR113,
VAR76,
VAR302,
VAR181,
VAR199,
VAR179,
VAR320,
VAR276,
VAR295,
VAR200,
VAR59,
V... | apache-2.0 |
yunqu/PYNQ | boards/ip/address_remap_1.0/hdl/address_remap_v1_0.v | 7,259 | module MODULE1 #
(
parameter integer VAR50 = 1,
parameter integer VAR90 = 32,
parameter integer VAR84 = 6,
parameter integer VAR68 = 0,
parameter integer VAR54 = 0,
parameter integer VAR8 = 0,
parameter integer VAR73 = 0,
parameter integer VAR35 = 0,
parameter VAR97 = 32'h40000000,
parameter integer VAR94 = 16,
paramet... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/cmm_intr.v | 9,133 | module MODULE1 (
VAR31, VAR1,
VAR36,
VAR2,
VAR3, VAR10,
VAR15,
VAR6,
VAR27,
VAR19,
VAR37,
VAR30,
VAR7,
VAR13,
VAR9,
VAR29,
rst,
clk
) ;
output VAR31; output VAR1;
output [1:0] VAR36;
output VAR2;
output [7:0] VAR19;
input VAR10;
input [7:0] VAR15;
input [15:0] VAR27;
input [2:0] VAR6;
input VAR3; input [15:0] VAR37;
in... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/LOAGDA_St_N16_M4_P8_syn.v | 3,615 | module MODULE1 ( VAR123, VAR32, VAR84 );
input [15:0] VAR123;
input [15:0] VAR32;
output [16:0] VAR84;
wire VAR3, VAR73, VAR80, VAR109, VAR75, VAR59, VAR66,
VAR92, VAR119, VAR28, VAR69, VAR100, VAR21, VAR51, VAR121, VAR68, VAR70, VAR6, VAR60, VAR10, VAR31,
VAR105, VAR9, VAR104, VAR14, VAR40, VAR83, VAR52, VAR117, VAR86... | gpl-3.0 |
mbus/mbus | mbus/verilog/no_pwr_gating_ben/mbus_layer_wrapper.Ben.v | 4,040 | module MODULE1
(
input VAR40,
input VAR9,
input VAR41,
output VAR23,
output VAR22,
input [VAR52-1:0] VAR20,
input [VAR6-1:0] VAR37,
input VAR68,
input VAR43,
input VAR63,
output VAR74,
output [VAR52-1:0] VAR49,
output [VAR6-1:0] VAR32,
output VAR61,
input VAR39,
output VAR7,
output VAR47,
output VAR66,
output VAR50,
ou... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/impl/verilog/contact_discoverybkb.v | 1,461 | module MODULE1 (VAR8, VAR5, VAR4, VAR1, VAR7, clk);
parameter VAR2 = 8;
parameter VAR6 = 13;
parameter VAR3 = 8192;
input[VAR6-1:0] VAR8;
input VAR5;
input[VAR2-1:0] VAR4;
input VAR1;
output reg[VAR2-1:0] VAR7;
input clk;
reg [VAR2-1:0] VAR9[0:VAR3-1];
begin
begin
begin
end | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.functional.v | 1,717 | module MODULE1 (
VAR2,
VAR1,
VAR7 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR5
);
input VAR2;
input VAR1;
output VAR7 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR5 ;
wire VAR9 ;
wire VAR8;
or VAR10 (VAR9 , VAR5, VAR6, VAR11, VAR4 );
VAR3 VAR13 (VAR8, VAR9, VAR2, VAR1);
buf VAR12 (VAR7 , VAR8 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_source_sync_upstream.v | 11,160 | module MODULE1
, parameter VAR56 = 6
, parameter VAR1 = 3
, parameter VAR41 = 0
, parameter VAR47 = {VAR27 { 2'b10 } }
)
( input VAR46
, input VAR30
, input VAR54
, input VAR48
, input VAR35
, input [VAR27-1:0] VAR73
, input VAR40
, output VAR4
, output logic [VAR27-1:0] VAR52 , output logic VAR39 , input VAR70 , input... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb.functional.pp.v | 1,831 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR1,
VAR10,
VAR8 ,
VAR9
);
output VAR7 ;
output VAR4 ;
input VAR1;
input VAR10;
input VAR8 ;
input VAR9 ;
wire VAR3 ;
wire VAR2;
pullup VAR11 (VAR3 );
VAR6 VAR12 (VAR7 , VAR3, VAR1, VAR10 );
pulldown VAR13 (VAR2);
VAR6 VAR5 (VAR4 , VAR2, VAR1, VAR10);
endmodule | apache-2.0 |
ThomasLee969/verilog-homework | big_homework/cpu/InstructionMemory.v | 1,175 | module MODULE1(VAR2, VAR1);
input [31:0] VAR2;
output reg [31:0] VAR1;
always @(*)
case (VAR2[9:2])
8'd0 : VAR1 <= {6'h08, 5'd0, 5'd4, 16'd3};
8'd1 : VAR1 <= {6'h03, 26'd3};
8'd2 : VAR1 <= {6'h04, 5'd0, 5'd0, -16'd1};
8'd3 : VAR1 <= {6'h08, 5'd29, 5'd29, -16'd8};
8'd4 : VAR1 <= {6'h2b, 5'd29, 5'd31, 16'd4};
8'd5 : VAR1... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_time_out.v | 1,868 | module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 5: 0] VAR6;
input VAR4;
wire VAR5;
wire [ 5: 0] VAR3;
wire [ 5: 0] VAR2;
reg [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR2 = {6 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR4)
begin
if (VAR4... | gpl-3.0 |
neale/CS-program | 474-VLSI/Lab_ADC/Display_PLL_bb.v | 11,254 | module MODULE1 (
VAR3,
VAR2,
VAR1,
VAR4);
input VAR3;
input VAR2;
output VAR1;
output VAR4;
tri0 VAR3;
endmodule | unlicense |
freecores/sha3 | high_throughput_core/rtl/padder.v | 3,069 | module MODULE1(clk, reset, in, VAR6, VAR9, VAR8, VAR7, out, VAR3, VAR2);
input clk, reset;
input [63:0] in;
input VAR6, VAR9;
input [2:0] VAR8;
output VAR7;
output reg [575:0] out;
output VAR3;
input VAR2;
reg state;
reg VAR1;
reg [8:0] VAR10;
wire [63:0] VAR5;
reg [63:0] VAR12;
wire VAR11,
VAR4;
assign VAR7 = VAR10[8]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.pp.symbol.v | 1,340 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR9 ,
input VAR8 ,
output VAR5 ,
input VAR3 ,
input VAR7,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out.v | 6,089 | module MODULE1
,parameter VAR43(VAR7)
,parameter VAR20 = 0 ,parameter VAR28 = 0 )
(input VAR42
,input VAR45
,input VAR9
,input [VAR7-1:0][VAR25-1:0] VAR47
,output VAR40
,output VAR35
,output [VAR25-1:0] VAR3
,input VAR15
);
logic [VAR7-1:0][VAR25-1:0] VAR26;
if (VAR20 == 0)
begin: VAR1
assign VAR26 = VAR47;
end
else
be... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_avm_to_ic.v | 3,591 | module MODULE1 #(
parameter integer VAR18 = 256,
parameter integer VAR5 = 256,
parameter integer VAR21 = 6,
parameter integer VAR23 = 32,
parameter integer VAR29 = VAR18 / 8,
parameter integer VAR1 = 1,
parameter VAR13=1 )
(
input logic VAR25,
input logic VAR11,
input logic [VAR5-1:0] VAR7,
input logic [VAR21-1:0] VAR1... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_gt_common.v | 7,154 | module MODULE1 #(
parameter VAR5 = "VAR2", parameter VAR4 = "VAR49", parameter VAR15 = "2.1", parameter VAR56 = "VAR32", parameter VAR44 = 0 )
(
input VAR14,
input VAR17,
input VAR33,
input VAR30,
input VAR27,
input VAR19,
input VAR11,
input VAR29,
output [5:0] VAR23,
output [8:0] VAR57,
output VAR24,
output VAR35,
out... | gpl-3.0 |
jamesbowman/swapforth | j1b/verilog/j1.v | 3,585 | module MODULE1(
input wire clk,
input wire VAR20,
output wire VAR26,
output wire VAR8,
output wire [15:0] VAR25,
output wire VAR29,
output wire [VAR2-1:0] dout,
input wire [VAR2-1:0] VAR34,
input wire [VAR2-1:0] VAR9,
output wire [12:0] VAR38,
input wire [15:0] VAR7);
reg [4:0] VAR11, VAR16; reg [VAR2-1:0] VAR18; reg [... | bsd-3-clause |
donnaware/AGC | rtl/de0/modules/ng_MEB.v | 7,609 | module MODULE1(
input VAR8, input [ 5:0] VAR47, input [ 15:0] VAR32, input [ 13:0] VAR48, input [100:0] VAR7, input VAR15, output [15:0] VAR58, output VAR53 );
assign VAR58[15 ] = VAR27[15 ]; assign VAR58[14 ] = VAR27[15 ];
assign VAR58[13:0] = VAR27[13:0];
wire VAR4 = VAR47[VAR22(VAR4)];
wire [15:0] VAR26;
wire [15:0]... | gpl-3.0 |
jcrono/sd-host | src/cmd/control/sd_ctrl.v | 1,825 | module MODULE1(reset,
VAR7,
VAR5,
VAR18,
VAR16,
VAR10,
VAR12,
VAR4,
VAR17,
VAR6,
VAR11,
VAR3,
VAR13,
VAR9
);
input reset, VAR7, VAR17, VAR4, VAR16, VAR17, VAR13;
output reg VAR6, VAR11, VAR3, VAR12, VAR9;
input [135:0] VAR5;
output [47:0] VAR18;
parameter VAR14 = 0, VAR20 = 1, VAR19 = 2, VAR15 = 3, VAR2 = 4;
reg [2:0] ... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/acl_atomics_arb_stall.v | 2,661 | module MODULE1
parameter integer VAR14 = 6
)
(
input logic VAR4,
input logic VAR8,
VAR1 VAR3,
VAR1 VAR6
);
reg VAR5 [0:VAR14-1];
wire VAR7;
wire VAR13;
integer VAR12;
assign VAR6.req.request = ( VAR3.req.request & ~VAR13 ); assign VAR6.req.read = ( VAR3.req.read & ~VAR13 ); assign VAR6.req.write = ( VAR3.req.write & ~V... | mit |
nyaxt/dmix | spdif_dai_t.v | 5,131 | module MODULE1;
reg [31:0] VAR2 [262143:0];
integer VAR1;
begin
begin
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.functional.pp.v | 2,015 | module MODULE1 (
VAR16 ,
VAR9 ,
VAR1 ,
VAR14 ,
VAR17 ,
VAR3,
VAR4,
VAR5 ,
VAR10
);
output VAR16 ;
input VAR9 ;
input VAR1 ;
input VAR14 ;
input VAR17 ;
input VAR3;
input VAR4;
input VAR5 ;
input VAR10 ;
wire VAR13 ;
wire VAR12 ;
wire VAR11;
or VAR6 (VAR13 , VAR1, VAR9, VAR14 );
and VAR8 (VAR12 , VAR13, VAR17 );
VAR2 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.pp.blackbox.v | 1,289 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR3,
VAR8,
VAR6 ,
VAR2
);
output VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR8;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/TxFifo.v | 4,872 | module MODULE1(
VAR17,
VAR13,
VAR23,
VAR21,
VAR6,
VAR14,
VAR15,
VAR25,
VAR24,
VAR26,
VAR28,
VAR4,
VAR33 );
parameter VAR5 = 64;
parameter VAR8 = 6;
input VAR17;
input VAR13;
input VAR23;
input VAR21;
input VAR6;
output VAR14;
input [2:0] VAR15;
input VAR25;
input VAR24;
input VAR26;
input [7:0] VAR28;
output [7:0] VAR4... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/dest_axi_stream.v | 4,534 | module MODULE1 (
input VAR37,
input VAR43,
input enable,
output VAR26,
input VAR19,
output VAR9,
input [VAR17-1:0] VAR11,
output [VAR17-1:0] VAR14,
output [VAR17-1:0] VAR4,
input VAR3,
input VAR35,
input VAR12,
output VAR44,
output [VAR21-1:0] VAR31,
output VAR1,
input VAR28,
input [VAR21-1:0] VAR39,
input VAR24,
outpu... | mit |
olofk/oh | xilibs/hdl/fifo_async_104x16.v | 2,217 | module MODULE1
(
VAR5, VAR12, VAR3, dout, VAR8, valid,
VAR6, VAR7, VAR10, VAR2, VAR1, din, VAR11
);
parameter VAR14 = 104; parameter VAR9 = 16;
input VAR6; input VAR7; input VAR10; input VAR2;
input VAR1;
input [VAR14-1:0] din;
output VAR5;
output VAR12;
output VAR3;
input VAR11;
output [VAR14-1:0] dout;
output VAR8;
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.pp.v | 1,882 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR9,
VAR8 ,
VAR5 ,
VAR10 ,
VAR3
);
output VAR2 ;
input VAR12 ;
input VAR9;
input VAR8 ;
input VAR5 ;
input VAR10 ;
input VAR3 ;
wire VAR11 ;
wire VAR7;
buf VAR13 (VAR11 , VAR12 );
VAR6 VAR1 (VAR7, VAR11, VAR9, VAR5);
buf VAR4 (VAR2 , VAR7 );
endmodule | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,158 | module MODULE1(
VAR29,
VAR13,
VAR31,
VAR15,
VAR5,
VAR28,
VAR21,
VAR2,
VAR18,
VAR32
);
parameter VAR14 = 1;
parameter VAR22 = 8;
parameter VAR12 = 2;
parameter VAR11 = 2;
parameter VAR4 = 1;
localparam VAR7 = VAR14 * VAR22;
input VAR29;
input VAR13;
output VAR31;
input VAR15;
input [VAR7-1:0] VAR5;
input VAR28;
input VA... | gpl-2.0 |
fpgasystems/Centaur | rtl/fthread/user_tx_wr_if.v | 14,064 | module MODULE1 #(parameter VAR25 = VAR2)
(
input wire clk,
input wire VAR47,
input wire VAR53,
input wire VAR51,
output wire VAR59,
input wire VAR70,
input wire [57:0] VAR57,
input wire VAR95,
input wire [57:0] VAR79,
input wire [VAR25-1:0] VAR49,
input wire [511:0] VAR80,
input wire VAR85,
output wire VAR36,
output re... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.behavioral.pp.v | 1,167 | module MODULE1( VAR4, VAR5, VAR2, VAR7 );
input VAR4;
inout VAR2, VAR7;
output VAR5;
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR1 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
olajep/oh | src/common/hdl/oh_pwr_isolo.v | 1,031 | module MODULE1 #(parameter VAR8 = 1 )
(
input VAR6, input [VAR8-1:0] in, output [VAR8-1:0] out );
localparam VAR5 = VAR4;
generate
if(VAR5)
begin : VAR1
VAR3 VAR2 [VAR8-1:0] (.VAR6(VAR6),
.in(in[VAR8-1:0]),
.out(out[VAR8-1:0]));
end
else
begin : VAR7
assign out[VAR8-1:0] = {(VAR8){~VAR6}} & in[VAR8-1:0];
end
endgenerat... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o_1.v | 2,364 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR11 ,
VAR8 ,
VAR5,
VAR3,
VAR9 ,
VAR10
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR8 ;
input VAR5;
input VAR3;
input VAR9 ;
input VAR10 ;
VAR6 VAR7 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VA... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v | 51,675 | module MODULE1 #
(
parameter VAR124 = 100, parameter VAR7 = 2, parameter VAR132 = 5, parameter VAR32 = "0",
parameter VAR83 = 5, parameter VAR88 = "VAR11", parameter VAR147 = 1, parameter VAR59 = 3, parameter VAR18 = 8, parameter VAR122 = 8, parameter VAR23 = "VAR125", parameter VAR86 = "VAR46", parameter VAR134 = 3, p... | mit |
velizarefremov/MIPS | Part 4/Verilog Code/cpu_fpga.v | 1,471 | module MODULE1(
output [6:0] VAR1,
output [3:0] sel,
output VAR29,
output VAR25,
input VAR22,
input VAR20,
input VAR21
);
wire VAR16, VAR3;
assign VAR29 = VAR16;
assign VAR25 = VAR20;
wire VAR7;
VAR12 #(.VAR11(19)) VAR14(.VAR5(VAR7), .clk(VAR21));
wire [15:0] VAR6;
wire [15:0] VAR8;
VAR18 VAR17(
.VAR27(VAR1),
.VAR19(se... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.blackbox.v | 1,322 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
YoelRP/PROYECTO | bin/DFx/CRC5_D5.v | 1,568 | module MODULE1(
VAR5,
VAR6,
VAR2
);
output reg [4:0] VAR5;
input wire [10:0] VAR6;
input wire [4:0] VAR2;
reg [10:0] VAR4;
reg [4:0] VAR1;
reg [4:0] VAR3;
always @ (*)
begin
VAR4 [10:0] = VAR6 [10:0];
VAR1 [4:0] = VAR2 [4:0];
VAR3[0] = VAR4[10] ^ VAR4[9] ^ VAR4[6] ^ VAR4[5] ^ VAR4[3] ^ VAR4[0] ^ VAR1[0] ^ VAR1[3] ^ VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.functional.v | 1,233 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR3;
bufif0 VAR2 (VAR1 , VAR4, VAR3 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1rw_large.v | 3,535 | module MODULE1 #(parameter VAR19(VAR38 )
, parameter VAR19(VAR40 )
, parameter VAR9 = 0
)
(input VAR37
, input VAR14
, input [VAR38-1:0] VAR17
, input VAR5
, input VAR30
, output VAR10
, output VAR32
, output [VAR38-1:0] VAR23
);
localparam VAR1 = VAR18(VAR40);
logic [VAR1-1:0] VAR42, VAR39;
logic VAR35;
wire VAR29 = V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.blackbox.v | 1,277 | module MODULE1 (
VAR7,
VAR8,
VAR6,
VAR2
);
output VAR7;
input VAR8;
input VAR6;
input VAR2;
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_axi4lite_downsizer.v | 14,621 | module MODULE1 #
(
parameter VAR75 = "none",
parameter integer VAR62 = 32,
parameter integer VAR72 = 1,
parameter integer VAR55 = 1
)
(
input wire VAR65,
input wire VAR51,
input wire [VAR62-1:0] VAR61,
input wire [3-1:0] VAR2,
input wire VAR71,
output wire VAR17,
input wire [64-1:0] VAR58,
input wire [64/8-1:0] VAR21,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.behavioral.v | 3,381 | module MODULE1 (
VAR2 ,
VAR21 ,
VAR15 ,
VAR35 ,
VAR1 ,
VAR14,
VAR6
);
output VAR2 ;
input VAR21 ;
input VAR15 ;
input VAR35 ;
input VAR1 ;
input VAR14;
input VAR6;
supply1 VAR36;
supply1 VAR22 ;
supply0 VAR34 ;
supply1 VAR20 ;
supply0 VAR33 ;
wire VAR31 ;
wire VAR16 ;
wire VAR10 ;
reg VAR28 ;
wire VAR12 ;
wire VAR17 ;
... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/models/fifo_1c_4k.v | 1,392 | module MODULE1 ( VAR6, VAR19, VAR1, VAR7, VAR15, VAR17, VAR18,
VAR11, VAR5, VAR8, VAR14, VAR9, VAR4);
parameter VAR16 = 32;
parameter VAR12 = 4096;
input [31:0] VAR6;
input VAR19;
input VAR1;
input VAR7;
input VAR15;
input VAR17;
output [31:0] VAR18;
output VAR11;
output VAR5;
output [7:0] VAR8;
output VAR14;
output VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/common/rtl/iobdg_1r1w_rf16x160.v | 4,671 | module MODULE1 (
VAR12, VAR2, dout,
VAR11, VAR10, VAR1, VAR19, VAR9, VAR20, VAR22, VAR8,
VAR13, VAR17, VAR21, VAR18, VAR7, din, VAR4,
VAR15
);
input [19:0] VAR4; input [159:0] din; input [3:0] VAR7; input VAR18; input VAR21; input VAR17; input VAR13; input VAR8; input VAR22; input VAR20; input VAR9; input [3:0] VAR19; ... | gpl-2.0 |
ultraembedded/altor32 | rtl/cpu/altor32_ram_dp.v | 3,803 | module MODULE1
parameter VAR16 = 8,
parameter VAR11 = 14
)
(
input VAR10 ,
output [(VAR16 - 1):0] VAR8 ,
input [(VAR16 - 1):0] VAR3 ,
input [(VAR11 - 1):0] VAR7 ,
input VAR15 ,
input VAR14 ,
output [(VAR16 - 1):0] VAR6 ,
input [(VAR16 - 1):0] VAR2 ,
input [(VAR11 - 1):0] VAR12 ,
input VAR13
);
reg [(VAR16 - 1):0] VAR9 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.blackbox.v | 1,259 | module MODULE1 (
VAR5,
VAR7,
VAR1
);
output VAR5;
input VAR7;
input VAR1 ;
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/bach_new_bb.v | 5,026 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4 ,
VAR5,
VAR6,
VAR2 ,
VAR9
);
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR5;
input VAR6;
input VAR2 ;
input VAR9 ;
endmodule | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/RS232/Altera_UP_Avalon_RS232.v | 7,251 | module MODULE1 (
clk,
reset,
address,
VAR35,
VAR33,
read,
write,
VAR21,
VAR5,
irq,
VAR30,
VAR11
);
parameter VAR27 = 9;
parameter VAR25 = 9'd1;
parameter VAR23 = 9'd433;
parameter VAR3 = 9'd216;
parameter VAR13 = 10;
parameter VAR29 = 8;
parameter VAR19 = 1'b0;
input clk;
input reset;
input address;
input VAR35;
input ... | mit |
sorgelig/Apogee_MIST | font.v | 6,596 | module MODULE1 (
address,
VAR33,
VAR13);
input [10:0] address;
input VAR33;
output [5:0] VAR13;
tri1 VAR33;
wire [5:0] VAR50;
wire [5:0] VAR13 = VAR50[5:0];
VAR5 VAR47 (
.VAR22 (address),
.VAR20 (VAR33),
.VAR31 (VAR50),
.VAR43 (1'b0),
.VAR21 (1'b0),
.VAR34 (1'b1),
.VAR41 (1'b0),
.VAR3 (1'b0),
.VAR4 (1'b1),
.VAR16 (1'b1... | bsd-2-clause |
aquaxis/FPGAMAG18 | src/fmrv32im_artya7.v | 13,384 | module MODULE1
parameter VAR78 = "../../../VAR94/VAR160.VAR170"
)
(
input VAR151,
input VAR55,
output VAR18,
output [3:0] VAR79
);
wire VAR119;
assign VAR119 = VAR151;
wire VAR177;
assign VAR177 = 1'b1;
wire [31:0] VAR16;
wire [15:0] VAR57;
wire [3:0] VAR45;
wire [2:0] VAR46;
wire VAR144;
wire VAR20;
wire [31:0] VAR77;... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_stub.v | 5,788 | module MODULE1(VAR29, VAR78, VAR36,
VAR40, VAR77, VAR75, VAR32, VAR55, VAR44,
VAR11, VAR39, VAR45, VAR57, VAR4, VAR71,
VAR31, VAR74, VAR50, VAR56, VAR53, VAR58, VAR15,
VAR34, VAR63, VAR22, VAR16, VAR60, VAR12,
VAR17, VAR27, VAR20, VAR18, VAR66, VAR28,
VAR54, VAR37, VAR14, VAR80, VAR9, VAR13, VAR23,
VAR25, VAR62, VAR48,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf.pp.symbol.v | 1,258 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR4 ,
input VAR6,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.pp.symbol.v | 1,290 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR2 ,
output VAR4 ,
input VAR5 ,
input VAR8,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | prueba_lectura_rtc - copia.v | 5,210 | module MODULE1
(
input wire clk, reset,
input wire VAR9,
inout [7:0]VAR63,
output wire VAR27, VAR65, VAR40, VAR79,
output [7:0] VAR48,
output VAR24, VAR45
);
reg [7:0]VAR55;
wire [7:0]VAR8;
wire [7:0]VAR52;
wire VAR72;
wire VAR80;
wire VAR16;
wire interrupt;
wire [7:0]VAR68,VAR91,VAR11;
wire [7:0]VAR94,VAR98,VAR86;
wir... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Frequency_To_Volts.v | 2,794 | module MODULE1
(
VAR9,
VAR4,
VAR21,
VAR5
);
input signed [31:0] VAR9; input signed [17:0] VAR4; input signed [17:0] VAR21; output signed [17:0] VAR5;
wire signed [31:0] VAR3; wire signed [17:0] VAR11; wire signed [18:0] VAR17; wire signed [18:0] VAR8; wire signed [17:0] VAR1; wire signed [35:0] VAR20; wire signed [36:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.functional.pp.v | 1,833 | module MODULE1 (
VAR1,
VAR7,
VAR3 ,
VAR2 ,
VAR13
);
input VAR1;
input VAR7;
output VAR3 ;
input VAR2 ;
input VAR13 ;
wire VAR3 VAR6 ;
wire VAR12 ;
wire VAR10;
not VAR8 (VAR6 , VAR13 );
or VAR5 (VAR12 , VAR6, VAR2 );
VAR11 VAR9 (VAR10, VAR12, VAR1, VAR7);
buf VAR4 (VAR3 , VAR10 );
endmodule | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_static_top.v | 16,608 | module MODULE1 #
(
parameter VAR33 = 32 ,
parameter VAR10 = 1 ,
parameter VAR56 = 1 ,
parameter VAR20 = 1 ,
parameter VAR30 = 1 ,
parameter VAR6 = 32 ,
parameter VAR96 = 32'h12A00000 ,
parameter VAR101 = 32'h13A00000 ,
parameter VAR4 = 32'h12A00FFF,
parameter VAR78 = 32'h13A00FFF,
parameter VAR65 = 0 ,
parameter VAR72 ... | mit |
SymbiFlow/symbiflow-arch-defs | xc/xc7/techmap/carry_map.v | 3,464 | module MODULE1(
output [3:0] VAR17,
output [3:0] VAR48,
input VAR19,
input VAR8,
input [3:0] VAR2, VAR41
);
parameter VAR39 = 1;
parameter VAR44 = 1'b0;
parameter VAR7 = 1;
parameter VAR13 = 1'b0;
localparam [0:0] VAR5 = (
VAR39 == 1 && VAR44 == 0 &&
VAR7 == 1 && VAR13 == 0);
localparam [0:0] VAR42 = (
VAR39 == 1 && VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.behavioral.v | 1,110 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/rx_client_fifo_8.v | 30,612 | module MODULE1
(
input VAR119,
input VAR59,
output reg [7:0] VAR114,
output reg VAR42,
output VAR11,
input VAR117,
input VAR110,
input VAR9,
input [7:0] VAR33,
input VAR121,
input VAR83,
output reg VAR52,
input VAR55,
output [3:0] VAR63,
output VAR54
);
wire VAR105;
wire VAR20;
wire [8:0] VAR88;
parameter VAR46 = 3'b00... | mit |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg.v | 35,123 | module MODULE1 (
VAR30, VAR28, VAR107, VAR114, VAR147, VAR146, VAR68, VAR122, VAR97, VAR140,
VAR116, VAR129, VAR37, VAR113, VAR193, VAR67, VAR185, VAR126, VAR165, VAR84, VAR135, VAR173, VAR192, VAR43, VAR92, VAR65, VAR136, VAR74, VAR80, VAR115, VAR184, VAR72 );
output VAR30; output VAR28; output VAR107; output VAR114; ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep.blackbox.v | 1,477 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
supply1 VAR8;
supply1 VAR6 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
mfkiwl/parallella-platform | hdl/fifo_mem.v | 1,596 | module MODULE1 (
VAR9,
VAR10, VAR8, VAR4, VAR7, VAR1
);
parameter VAR6 = 104;
parameter VAR2 = 2;
localparam VAR3 = 1<<VAR2;
input VAR10; input VAR8;
input [VAR6-1:0] VAR4;
input [VAR2-1:0] VAR7;
input [VAR2-1:0] VAR1;
output [VAR6-1:0] VAR9;
reg [VAR6-1:0] VAR5[VAR3-1:0];
always @(posedge VAR10)
if(VAR8)
VAR5[VAR7[VAR... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/vfabric_buffered_fifo.v | 2,247 | module MODULE1(VAR3, VAR7,
VAR12, VAR11, VAR19,
VAR21, VAR17, VAR5);
parameter VAR15 = 32;
parameter VAR14 = 64;
parameter VAR1 = 32; parameter VAR10 = "VAR8";
localparam VAR2=VAR14-VAR1;
input VAR3, VAR7;
input [VAR15-1:0] VAR12;
input VAR11;
output VAR19;
output [VAR15-1:0] VAR21;
output VAR17;
input VAR5;
wire VAR9;... | mit |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/intr_capturer.v | 1,596 | module MODULE1 #(
parameter VAR3 = 32
)(
input clk,
input VAR7,
input [VAR3-1:0] VAR5,
input addr,
input read,
output [31:0] VAR13
);
reg [VAR3-1:0] VAR11;
reg [31:0] VAR10;
wire [31:0] VAR9;
wire [31:0] VAR6;
wire [31:0] VAR2;
wire VAR4;
wire VAR12;
always @(posedge clk or negedge VAR7) begin
if (!VAR7) VAR11 <= 'b0;
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.behavioral.v | 3,096 | module MODULE1( VAR3, VAR6, VAR5, VAR1, VAR8 );
input VAR6, VAR1, VAR5;
output VAR8, VAR3;
VAR4 VAR7(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8));
VAR4 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
rcls/discus | verilog/swinterface.v | 4,375 | module MODULE1(input wire VAR39,
input wire VAR3,
input wire VAR1,
output wire VAR21,
input wire VAR45,
input wire VAR34,
input wire VAR11,
output reg VAR40,
output wire [7:0] VAR37);
reg VAR22;
reg VAR9;
reg VAR14;
reg VAR4;
reg VAR15;
wire VAR23;
reg [7:0] memory[0:255];
reg [7:0] VAR5[0:255];
wire VAR30;
wire write;... | gpl-3.0 |
drichmond/riffa | fpga/xilinx/NetFPGA/NetFPGA_Gen3x4If128/hdl/NetFPGA_Gen3x4If128.v | 25,630 | module MODULE1
parameter VAR204 = 4,
parameter VAR211 = 128,
parameter VAR70 = 256,
parameter VAR9 = 6)
(output [(VAR204 - 1) : 0] VAR106,
output [(VAR204 - 1) : 0] VAR58,
input [(VAR204 - 1) : 0] VAR105,
input [(VAR204 - 1) : 0] VAR37,
output [1:0] VAR41,
input VAR182,
input VAR82,
input VAR130);
wire VAR208;
wire VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.pp.blackbox.v | 1,295 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR1,
VAR5,
VAR4 ,
VAR7
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/Bluetooth/speed_select.v | 1,263 | module MODULE1(
input clk,VAR4,VAR2,
output VAR3
);
reg[13:0] VAR1; reg VAR5;
reg[2:0] VAR6;
always @(posedge clk or negedge VAR4)
if(!VAR4)
VAR1<=14'd0;
else if((VAR1==5207)|| !VAR2) VAR1<=14'd0;
else
VAR1<=VAR1+1'b1;
always @(posedge clk or negedge VAR4) begin
if(!VAR4)
VAR5<=1'b0;
end
else if(VAR1==2603) VAR5<=1'b1;... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/dispatch.v | 6,396 | module MODULE1(
input clk,
input VAR3,
input VAR12,
input [133:0] VAR2,
input VAR6,
input VAR22,
output reg VAR16,
input VAR21,
input VAR8, output reg VAR1,
output [133:0] VAR19,
output reg VAR4,
output VAR14,
input VAR23,
output reg VAR5,
output [133:0] VAR18,
output reg VAR17,
output VAR9,
input VAR13
);
reg [133:0] ... | apache-2.0 |
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