repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s298.v | 4,740 | module MODULE1 (VAR235,VAR280,VAR1);
input VAR235,VAR1;
output VAR280;
wire VAR2,VAR12;
trireg VAR203,VAR217;
nmos VAR254 (VAR217,VAR1,VAR12);
not VAR156 (VAR2,VAR217);
nmos VAR193 (VAR203,VAR2,VAR235);
not VAR92 (VAR280,VAR203);
not VAR112 (VAR12,VAR235);
endmodule
module MODULE2(VAR125,VAR28,VAR235,VAR168,VAR179,VAR1... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/uart_tx.v | 2,859 | module MODULE1 (
input reset,
input clk,
input [1:0] VAR1,
input VAR8,
input [7:0] VAR3,
input VAR10,
output reg VAR9,
output reg VAR7
);
parameter VAR11 = 0;
reg [7:0] VAR2;
reg [3:0] VAR5;
reg [9:0] VAR6;
reg VAR4;
always @ (posedge clk) begin
if (reset) begin
VAR4 <= 1'b0;
VAR6 <= 10'b0;
VAR2 <= 8'd0;
VAR7 <= 1'b1;
... | gpl-3.0 |
YosysHQ/yosys | techlibs/xilinx/brams_xcu_map.v | 5,949 | module MODULE2 (...);
parameter VAR57 = 0;
parameter VAR108 = "VAR87";
parameter VAR80 = 0;
parameter VAR13 = 1;
parameter VAR90 = 1;
parameter VAR7 = 1;
parameter VAR95 = 1;
parameter VAR34 = 1;
parameter VAR16 = "VAR69";
parameter VAR23 = 0;
parameter VAR21 = 1;
parameter VAR72 = 1;
parameter VAR84 = 1;
parameter VAR... | isc |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/txc_engine_ultrascale.v | 22,404 | module MODULE1
parameter VAR68 = 128,
parameter VAR54 = 1,
parameter VAR158 = 1,
parameter VAR143 = 10,
parameter VAR10 = 256
)
(
input VAR87,
input VAR41,
input [VAR40-1:0] VAR1,
input VAR162,
output VAR134,
output VAR99,
output [VAR68-1:0] VAR36,
output [(VAR68/32)-1:0] VAR79,
output [VAR154-1:0] VAR140,
input VAR133... | gpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab6/ADD_SUB.v | 4,645 | module MODULE1(VAR15, VAR11, VAR14, VAR13, VAR12, VAR9, clk, VAR1, VAR3);
output [3:0] VAR14;
output [3:0] VAR13;
output [3:0] VAR15;
output [3:0] VAR11;
output VAR12;
input [1:0] VAR3;
input [3:0] VAR9;
input VAR1;
input clk;
reg [3:0] VAR2, VAR7, VAR4, VAR8;
reg VAR5;
reg VAR6;
reg VAR10;
always @(posedge clk) begin
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.behavioral.pp.v | 1,865 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1,
VAR3,
VAR5 ,
VAR12
);
output VAR8 ;
input VAR7 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR12 ;
wire VAR4 ;
wire VAR11;
buf VAR2 (VAR4 , VAR7 );
VAR9 VAR6 (VAR11, VAR4, VAR1, VAR3);
buf VAR10 (VAR8 , VAR11 );
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SOC_jtag_uart_0.v | 16,514 | module MODULE1 (
clk,
VAR2,
VAR57,
VAR47,
VAR44,
VAR51,
VAR1
)
;
output VAR47;
output [ 7: 0] VAR44;
output VAR51;
output [ 5: 0] VAR1;
input clk;
input [ 7: 0] VAR2;
input VAR57;
wire VAR47;
wire [ 7: 0] VAR44;
wire VAR51;
wire [ 5: 0] VAR1;
always @(posedge clk)
begin
if (VAR57)
("%VAR22", VAR2);
end
assign VAR1 = {6... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.symbol.v | 1,341 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR2
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.symbol.v | 1,602 | module MODULE1 (
input VAR7 ,
output VAR3 ,
input VAR6
);
supply1 VAR1 ;
supply0 VAR5 ;
supply1 VAR2;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_gtp_pipe_rate.v | 16,174 | module MODULE1 #
(
parameter VAR3 = "VAR6", parameter VAR48 = 4'd15
)
(
input VAR20,
input VAR24,
input [ 1:0] VAR35,
input VAR32,
input VAR5,
input VAR44,
input VAR47,
input VAR1,
input VAR25,
output VAR2,
output VAR15,
output VAR42,
output [ 2:0] VAR52,
output VAR34,
output VAR45,
output VAR36,
output [ 4:0] VAR33
);... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_stub.v | 1,360 | module MODULE1(VAR6, VAR2, VAR5, VAR3, VAR4,
VAR1, VAR7)
;
output VAR6;
output VAR2;
output VAR5;
output VAR3;
input VAR4;
output VAR1;
input VAR7;
endmodule | apache-2.0 |
ptracton/UART_ECHO | rtl/uart_echo.v | 3,406 | module MODULE1 (
VAR5,
VAR1, VAR3, VAR6
) ;
input VAR1;
input VAR3;
input VAR6;
output VAR5;
reg [7:0] VAR14;
reg VAR15;
reg VAR4;
wire [7:0] VAR13;
wire irq;
wire VAR2;
wire VAR10;
wire VAR9;
wire VAR7;
VAR11 VAR11(
.VAR13 (VAR13[7:0]),
.VAR8 (VAR5),
.irq (irq),
.VAR2 (VAR2),
.VAR10 (VAR10),
.VAR9 (VAR9),
.VAR14 (VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.functional.v | 1,581 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR3;
wire VAR7 ;
wire VAR9;
not VAR4 (VAR7 , VAR3 );
VAR8 VAR2 (VAR9 , VAR1, VAR7 );
buf VAR6 (VAR5 , VAR9 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/source/pcie_bram_top_v6.v | 5,872 | module MODULE1
parameter VAR28 = 0,
parameter VAR29 = 31,
parameter VAR20 = 24,
parameter VAR10 = 1,
parameter VAR16 = 2,
parameter VAR31 = 1,
parameter VAR7 = 'h1FFF,
parameter VAR23 = 1,
parameter VAR12 = 2,
parameter VAR18 = 1
)
(
input VAR4,
input VAR27,
input VAR17,
input [12:0] VAR19,
input [71:0] VAR32,
input VA... | lgpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/register_file.v | 1,214 | module MODULE1(
input VAR6,
input VAR8,
input [2:0] VAR3,
input [2:0] VAR9,
input [15:0] VAR7,
input [2:0] VAR11,
input VAR10,
output reg [15:0] VAR4,
output reg [15:0] VAR5
);
reg [15:0] VAR2 [7:0];
integer VAR1; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.pp.symbol.v | 1,340 | module MODULE1 (
input VAR6 ,
output VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR7 ,
input VAR1,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/d_BCH_SC_top.v | 22,885 | module MODULE1(
input wire VAR118,
input wire VAR17,
input wire VAR114,
input wire VAR96,
input wire [4:0] VAR128,
output wire VAR51,
input wire VAR156, input wire VAR70, input wire [VAR164-1:0] VAR55, output reg VAR61,
output wire VAR37, output wire VAR180, output wire VAR170, output reg VAR132,
output reg VAR7, outpu... | gpl-3.0 |
mashanz/FinalProject | Code/fpga/spartan3a/alucontrol.v | 1,775 | module MODULE1(input [1:0] VAR3, input [5:0] VAR7, output reg [2:0] MODULE1 );
parameter VAR1 = 6'b100000;
parameter VAR4 = 6'b100010;
parameter VAR5 = 6'b100100;
parameter VAR2 = 6'b100101;
parameter VAR6 = 6'b101010;
always @(*)
case (VAR3) 2'b00: MODULE1 = 3'b010; 2'b01: MODULE1 = 3'b110; 2'b10: case (VAR7) VAR1: MO... | gpl-3.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/ethmac/eth_transmitcontrol.v | 10,538 | module MODULE1 (VAR3, VAR8, VAR30, VAR1, VAR16, VAR13,
VAR4, VAR27, VAR2, VAR5, VAR11,
VAR24, VAR18, VAR21, VAR25, VAR7, VAR19,
VAR12, VAR33, VAR14
);
parameter VAR23 = 1;
input VAR3;
input VAR8;
input VAR30;
input VAR1;
input VAR16;
input VAR13;
input VAR4;
input VAR27;
input VAR2;
input VAR5;
input VAR11;
input [15:0... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ui/ui_top.v | 14,294 | module MODULE1 #
(
parameter VAR7 = 100,
parameter VAR67 = 256,
parameter VAR72 = 32,
parameter VAR16 = 3,
parameter VAR34 = 12,
parameter VAR3 = 5,
parameter VAR10 = 5,
parameter VAR1 = "VAR63",
parameter VAR52 = "VAR63",
parameter VAR9 = "VAR60",
parameter VAR8 = 2,
parameter VAR31 = 4,
parameter VAR23 = "VAR19", par... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/Arty/fpga/rtl/fpga.v | 5,762 | module MODULE1 (
input wire clk,
input wire VAR21,
input wire [3:0] VAR108,
input wire [3:0] VAR88,
output wire VAR17,
output wire VAR67,
output wire VAR31,
output wire VAR20,
output wire VAR78,
output wire VAR76,
output wire VAR94,
output wire VAR58,
output wire VAR74,
output wire VAR30,
output wire VAR96,
output wire... | mit |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/I2C/I2C_CCD_Config.v | 21,234 | module MODULE1 ( VAR15,
VAR10,
VAR14,
VAR7 );
input VAR15;
input VAR10;
output VAR14;
inout VAR7;
reg [15:0] VAR17;
reg [23:0] VAR20;
reg VAR18;
reg VAR1;
wire VAR23;
wire VAR2;
reg [15:0] VAR22;
reg [9:0] VAR9;
reg [3:0] VAR8;
parameter VAR3 = 50000000; parameter VAR11 = 20000; parameter VAR6 = 166;
always@(posedge VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi_4.v | 2,348 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR9 ,
VAR2,
VAR10,
VAR3,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR2;
input VAR10;
input VAR3;
input VAR7 ;
input VAR4 ;
VAR8 VAR6 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.pp.symbol.v | 1,448 | module MODULE1 (
input VAR7,
input VAR9,
input VAR8 ,
input VAR6 ,
output VAR1 ,
input VAR5 ,
input VAR2,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.behavioral.v | 1,524 | module MODULE1 (
VAR13 ,
VAR2,
VAR6,
VAR11
);
output VAR13 ;
input VAR2;
input VAR6;
input VAR11;
supply1 VAR10;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR12 ;
wire VAR9 ;
wire VAR5;
and VAR1 (VAR9 , VAR2, VAR6 );
nor VAR7 (VAR5, VAR11, VAR9 );
buf VAR8 (VAR13 , VAR5 );
endmodule | apache-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_daala_idct4_stream_0_1/hdl/daala_idct4_stream_v1_0_S00_AXIS.v | 4,930 | module MODULE1 #
(
parameter integer VAR9 = 32
)
(
input wire VAR5,
input wire VAR21,
output wire VAR22,
input wire [VAR9-1 : 0] VAR1,
input wire [(VAR9/8)-1 : 0] VAR17,
input wire VAR11,
input wire VAR3
);
function integer VAR4 (input integer VAR18);
begin
for(VAR4=0; VAR18>0; VAR4=VAR4+1)
VAR18 = VAR18 >> 1;
end
endf... | bsd-2-clause |
saisrivathsa/Image-Watermarking | ipcore_dir/Amul.v | 12,789 | module MODULE2 (
clk, VAR124, VAR95
);
input clk;
output [7 : 0] VAR124;
input [7 : 0] VAR95;
wire \VAR85/VAR9 ;
wire \VAR85/VAR93 ;
wire \VAR85/VAR123 ;
wire \VAR85/VAR66 ;
wire \VAR85/VAR113 ;
wire \VAR85/VAR3 ;
wire \VAR85/VAR143 ;
wire \VAR85/VAR43 ;
wire \VAR85/VAR105 ;
wire \VAR85/VAR34 ;
wire \VAR85/VAR99 ;
wire... | mit |
jessegit/proxmark3 | fpga/fpga_hf.v | 5,997 | module MODULE1(
input VAR46, output VAR56, input VAR91, input VAR84,
input VAR44, input VAR29, input VAR89,
output VAR14, output VAR38,
output VAR9, output VAR58, output VAR6, output VAR64,
input [7:0] VAR94, output VAR20, output VAR25,
output VAR10, output VAR83, input VAR67, output VAR87,
input VAR92, input VAR15,
ou... | gpl-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/NIOS_Sys_jtag_uart_0.v | 17,487 | module MODULE5 (
clk,
VAR7,
VAR32,
VAR49,
VAR24,
VAR8,
VAR35
)
;
output VAR49;
output [ 7: 0] VAR24;
output VAR8;
output [ 5: 0] VAR35;
input clk;
input [ 7: 0] VAR7;
input VAR32;
wire VAR49;
wire [ 7: 0] VAR24;
wire VAR8;
wire [ 5: 0] VAR35;
always @(posedge clk)
begin
if (VAR32)
("%VAR45", VAR7);
end
assign VAR35 = {... | gpl-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/code/exin.v | 1,194 | module MODULE1(VAR1,rst,VAR3,VAR2
);
input VAR1,rst;
input [31:0] VAR3;
output reg [7:0] VAR2;
always @(posedge VAR1 or posedge rst)
begin
if (rst)
VAR2=8'd0;
end
else
case(VAR3[31:26])
6'b000000:
begin
case(VAR3[5:0])
6'b100000:
begin
VAR2=(|VAR3[15:11])?8'd1:8'd0;
end
6'b100010:VAR2=8'd2;
6'b100100:VAR2=8'd3;
6'b1001... | gpl-2.0 |
kyzhai/NUNY | src/hardware/pass_new_bb.v | 5,016 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.functional.pp.v | 1,804 | module MODULE1( VAR9, VAR8, VAR18, VAR22, VAR1, VAR14, VAR3 );
input VAR1, VAR22, VAR8, VAR9;
inout VAR14, VAR3;
output VAR18;
wire VAR11;
not VAR16( VAR11, VAR1 );
wire VAR5;
not VAR6( VAR5, VAR8 );
wire VAR7;
and VAR24( VAR7, VAR11, VAR5 );
wire VAR2;
not VAR12( VAR2, VAR9 );
wire VAR15;
and VAR17( VAR15, VAR11, VAR2... | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/bench/verilog/msp_debug.v | 16,547 | module MODULE1 (
VAR119, VAR40, VAR26, VAR61, VAR19, VAR18, VAR60,
VAR35 );
output [8*32-1:0] VAR119; output [8*32-1:0] VAR40; output [31:0] VAR26; output [8*32-1:0] VAR61; output [31:0] VAR19; output [15:0] VAR18; output [8*32-1:0] VAR60;
input VAR35;
function [64*8-1:0] VAR46;
input [32*8-1:0] VAR89;
input [32*8-1:0]... | bsd-3-clause |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_020bits.v | 1,917 | module MODULE2 (
clk,
VAR11, VAR33, VAR32, VAR13, VAR26, VAR28, VAR4, VAR21,
sum,
);
input clk;
input [VAR5+0-1:0] VAR11, VAR33, VAR32, VAR13, VAR26, VAR28, VAR4, VAR21;
output [VAR5 :0] sum;
reg [VAR5 :0] sum;
wire [VAR5+3-1:0] VAR22;
wire [VAR5+2-1:0] VAR9, VAR27;
wire [VAR5+1-1:0] VAR31, VAR8, VAR7, VAR17;
reg [VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b.behavioral.v | 1,477 | module MODULE1 (
VAR13 ,
VAR9,
VAR8 ,
VAR12
);
output VAR13 ;
input VAR9;
input VAR8 ;
input VAR12 ;
supply1 VAR7;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
wire VAR1 ;
wire VAR11;
not VAR10 (VAR1 , VAR9 );
and VAR2 (VAR11, VAR12, VAR1, VAR8 );
buf VAR4 (VAR13 , VAR11 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.behavioral.v | 1,341 | module MODULE1( VAR7, VAR5, VAR6, VAR1, VAR4 );
input VAR6, VAR4, VAR5, VAR1;
output VAR7;
VAR8 VAR3(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4));
VAR8 VAR2(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3.behavioral.pp.v | 1,819 | module MODULE1 (
VAR14 ,
VAR2 ,
VAR4 ,
VAR12 ,
VAR8,
VAR10,
VAR1 ,
VAR7
);
output VAR14 ;
input VAR2 ;
input VAR4 ;
input VAR12 ;
input VAR8;
input VAR10;
input VAR1 ;
input VAR7 ;
wire VAR9 ;
wire VAR5;
and VAR11 (VAR9 , VAR12, VAR2, VAR4 );
VAR3 VAR6 (VAR5, VAR9, VAR8, VAR10);
buf VAR13 (VAR14 , VAR5 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.behavioral.pp.v | 1,246 | module MODULE1( VAR7, VAR2, VAR8, VAR6, VAR3 );
input VAR7, VAR2;
inout VAR6, VAR3;
output VAR8;
VAR1 VAR4(.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR3(VAR3));
VAR1 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/sfp/act_led.v | 1,754 | module MODULE1(
clk,
reset,
VAR2,
VAR3,
VAR8);
input clk;
input reset;
input VAR2;
input VAR3;
output VAR8;
reg [23:0] VAR6;
reg VAR8;
reg [1:0]VAR4;
parameter VAR1=2'b0,
VAR5 =2'b01,
VAR7=2'b10;
always@(posedge clk or negedge reset)
if(!reset)
begin
VAR6 <= 24'b0;
VAR8 <= 1'b1;
VAR4 <= VAR1;
end
else
begin
case(VAR4)
... | apache-2.0 |
hakehuang/pycpld | ips/ip/qdec/qdec.v | 2,288 | module MODULE1(VAR6, VAR3, enable, VAR1, VAR13,VAR4, VAR9);
input VAR6;
input VAR3;
input enable;
output VAR1;
output VAR13;
output VAR4;
output VAR9;
reg VAR10;
reg VAR2;
reg VAR7;
reg[7:0] VAR5;
reg VAR9;
reg [31:0] VAR11;
reg VAR8;
always @(posedge VAR3 or negedge VAR6) begin
if (!VAR6) begin
VAR11 <= 0;
VAR8 <= 0;
... | mit |
SiLab-Bonn/basil | basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v | 4,992 | module MODULE1 (
input VAR54,
input VAR21, VAR34,
output reg VAR37,
input VAR18, VAR41,
output reg VAR6,
input VAR53,
output VAR13, VAR29,
input [3:0] VAR45, VAR12,
output [13:0] VAR31, VAR50, VAR33, VAR44
);
wire VAR32;
wire VAR51;
wire [3:0] VAR36;
wire VAR3;
reg [3:0] VAR30;
always @(negedge VAR54)
VAR37 <= VAR32;
a... | bsd-3-clause |
Beck-Sisyphus/EE471 | Lab3/sourceCode/DE1_SoC.v | 2,746 | module MODULE1 (VAR23, VAR8, VAR21, VAR2);
input VAR23; output reg [9:0] VAR8;
input [9:0] VAR21;
input [3:0] VAR2;
wire clk;
wire [15:0] VAR15;
reg [6:0] VAR5;
reg VAR16, VAR20;
reg [10:0] VAR24;
reg [15:0] VAR9;
wire [1:0] state, VAR18;
wire VAR1, rst, VAR4, VAR7;
reg [4:0] VAR12, VAR26, VAR22;
reg [31:0] VAR19;
wire... | mit |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/cpu_ctl.v | 3,492 | module MODULE1(VAR25,VAR30,VAR42,VAR31,VAR4,VAR7,VAR36,VAR24,VAR20,VAR19,VAR23,VAR28,VAR33,VAR8,VAR14,VAR13,VAR5,VAR10
);
input wire [5:0] VAR25, VAR30;
input wire [4:0] VAR31;
input wire VAR42;
output wire VAR4,VAR7,VAR36,VAR24,VAR20,VAR19,VAR23,VAR28,VAR33,VAR8,VAR14,VAR10;
output wire [4:0] VAR13;
output wire [1:0] ... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/common/reset_sync.v | 3,775 | module MODULE1 #(
parameter VAR7 = 2'b11
)
(
input VAR10,
input clk,
input enable,
output VAR6
);
wire VAR8;
wire VAR13;
VAR2 #(
.VAR4 (VAR7[0])
) VAR14 (
.VAR9 (clk),
.VAR1 (enable),
.VAR12(VAR10),
.VAR3 (1'b0),
.VAR11 (VAR8)
);
VAR2 #(
.VAR4 (VAR7[1])
) VAR5 (
.VAR9 (clk),
.VAR1 (enable),
.VAR12(VAR10),
.VAR3 (VAR8),... | lgpl-3.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/shift_right_32.v | 1,626 | module MODULE1(
input[31:0] VAR1, output[31:0] out );
assign out[0] = VAR1[1];
assign out[1] = VAR1[2];
assign out[2] = VAR1[3];
assign out[3] = VAR1[4];
assign out[4] = VAR1[5];
assign out[5] = VAR1[6];
assign out[6] = VAR1[7];
assign out[7] = VAR1[8];
assign out[8] = VAR1[9];
assign out[9] = VAR1[10];
assign out[10] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.symbol.v | 1,358 | module MODULE1 (
input VAR6,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.behavioral.pp.v | 1,179 | module MODULE1( VAR7, VAR1, VAR5, VAR6 );
input VAR7;
inout VAR5, VAR6;
output VAR1;
VAR4 VAR2(.VAR7(VAR7),.VAR1(VAR1),.VAR5(VAR5),.VAR6(VAR6));
VAR4 VAR3(.VAR7(VAR7),.VAR1(VAR1),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
manu3193/TextEditor | Controlador_Menu.v | 6,141 | module MODULE1(
clk,
reset,
VAR28,
VAR1,
VAR2,
VAR7,
VAR30,
VAR10,
VAR33,
VAR6,
VAR18,
VAR9,
VAR22,
VAR25,
VAR14,
VAR17,
VAR32,
VAR11,
VAR26,
VAR20,
VAR3,
VAR12
);
input clk, reset;
input VAR28, VAR1, VAR2, VAR7, VAR30;
wire VAR8, VAR16, VAR21, VAR23, VAR15;
VAR13 VAR19(
.VAR4 (clk),
.VAR28 (VAR28),
.VAR1 (VAR1),
.VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.pp.symbol.v | 1,341 | module MODULE1 (
input VAR5 ,
input VAR6 ,
input VAR3 ,
input VAR7 ,
output VAR4 ,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/matrix_mult/matrix_mult_N_M_2.v | 1,025 | module MODULE1
parameter VAR1=3,
parameter VAR15=32
)
(
clk,
rst,
VAR4,
VAR10,
VAR19
);
input clk,rst;
input[VAR1*VAR15-1:0] VAR4;
input[VAR1*VAR15-1:0] VAR10;
output reg[VAR15-1:0] VAR19;
wire [VAR15-1:0] VAR9[VAR1-1:0];
wire [VAR15-1:0] VAR2[VAR1-1:0];
wire [2*VAR15-1:0] VAR8[VAR1-1:0];
wire [VAR15-1:0] VAR18[VAR1:0]... | gpl-3.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/vgpr/vgpr.v | 14,062 | module MODULE1(
VAR136,
VAR3,
VAR28,
VAR106,
VAR7,
VAR42,
VAR234,
VAR242,
VAR205,
VAR239,
VAR30,
VAR240,
VAR49,
VAR56,
VAR238,
VAR204,
VAR82,
VAR105,
VAR225,
VAR32,
VAR12,
VAR133,
VAR9,
VAR141,
VAR129,
VAR127,
VAR188,
VAR83,
VAR151,
VAR124,
VAR40,
VAR230,
VAR4,
VAR185,
VAR65,
VAR98,
VAR134,
VAR223,
VAR214,
VAR100,
VAR8... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.behavioral.v | 1,645 | module MODULE1 (
VAR4 ,
VAR15,
VAR7,
VAR9,
VAR14
);
output VAR4 ;
input VAR15;
input VAR7;
input VAR9;
input VAR14;
supply1 VAR3;
supply0 VAR6;
supply1 VAR11 ;
supply0 VAR5 ;
wire VAR2 ;
wire VAR12 ;
wire VAR8;
nand VAR13 (VAR2 , VAR7, VAR15 );
nand VAR16 (VAR12 , VAR14, VAR9 );
and VAR10 (VAR8, VAR2, VAR12);
buf VAR1 ... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function_block2.v | 2,237 | module MODULE1
(
VAR3,
reset,
VAR9,
VAR5,
VAR11,
VAR1
);
input VAR3;
input reset;
input VAR9;
input [1:0] VAR5; output [1:0] VAR11; output VAR1;
parameter [1:0] VAR13 = 2; parameter [1:0] VAR10 = 3;
reg [1:0] VAR6; reg VAR2;
reg [1:0] VAR4; reg [1:0] VAR8; reg [1:0] VAR12;
always @(posedge VAR3)
begin : VAR7
if (reset ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.behavioral.v | 1,530 | module MODULE1 (
VAR4 ,
VAR3,
VAR6,
VAR5,
VAR10
);
output VAR4 ;
input VAR3;
input VAR6;
input VAR5;
input VAR10;
supply1 VAR12;
supply0 VAR9;
supply1 VAR14 ;
supply0 VAR8 ;
wire VAR1 ;
wire VAR2;
and VAR13 (VAR1 , VAR5, VAR3, VAR6 );
or VAR7 (VAR2, VAR1, VAR10 );
buf VAR11 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i_2.v | 2,214 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR2,
VAR9,
VAR10 ,
VAR5
);
output VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR2;
input VAR9;
input VAR10 ;
input VAR5 ;
VAR1 VAR8 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/fifo_0_wr_en.v | 2,697 | module MODULE1 ( clk,
reset,
din,
VAR9,
dout);
input clk;
input reset;
input din;
output VAR9;
output dout;
wire VAR2;
parameter VAR7 = 1'b1;
assign VAR9 = ~VAR2;
assign dout = din | VAR2;
VAR8 VAR5 (.VAR4(VAR2), .VAR6(clk), .VAR3(VAR7), .VAR10 (reset), .VAR1(din));
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.symbol.v | 1,416 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR8,
input VAR6
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_controller_interrupt_counter.v | 7,037 | module MODULE1 (
address,
VAR24,
clk,
VAR29,
VAR17,
VAR18,
irq,
VAR22
)
;
output irq;
output [ 15: 0] VAR22;
input [ 2: 0] address;
input VAR24;
input clk;
input VAR29;
input VAR17;
input [ 15: 0] VAR18;
wire VAR5;
wire VAR11;
wire VAR21;
reg [ 3: 0] VAR15;
wire VAR23;
reg VAR27;
wire VAR30;
wire [ 31: 0] VAR32;
reg [ ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n_1.v | 2,317 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR8,
VAR9 ,
VAR4 ,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR8;
input VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR1 ;
VAR6 VAR7 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR2 ,
VAR8
);
output VA... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_auto_pc_1/gcd_block_design_auto_pc_1_stub.v | 4,589 | module MODULE1(VAR38, VAR58, VAR33, VAR59,
VAR31, VAR50, VAR18, VAR42, VAR52, VAR10,
VAR47, VAR53, VAR37, VAR34, VAR9, VAR2, VAR46,
VAR35, VAR45, VAR5, VAR23, VAR43, VAR4, VAR55,
VAR13, VAR21, VAR41, VAR19, VAR29, VAR36,
VAR7, VAR15, VAR54, VAR12, VAR6, VAR57, VAR8,
VAR1, VAR22, VAR49, VAR48, VAR3, VAR25,
VAR26, VAR20,... | mit |
Murailab-arch/magukara | cores/gmii2fifo72/rtl/gmii2fifo72.v | 1,764 | module MODULE1 # (
parameter VAR4 = 4'h2
) (
input VAR5,
input VAR9,
input VAR2,
input [7:0] VAR6,
output [71:0] din,
input VAR11,
output reg VAR1,
output VAR3
);
assign VAR3 = VAR9;
reg [2:0] VAR10 = 3'h0;
reg [63:0] VAR7 = 64'h00;
reg [7:0] VAR8 = 8'h0;
reg [3:0] VAR12 = 4'h0;
always @(posedge VAR9) begin
if (VAR5) b... | gpl-3.0 |
medav/conware | conware_final/system/pcores/conware_v1_00_a/hdl/verilog/conware.v | 2,734 | module MODULE1 #(
parameter VAR19 = 32,
parameter VAR32 = 8,
parameter VAR16 = 1
)(
VAR6,
VAR31,
VAR37,
VAR3,
VAR13,
VAR10,
VAR28,
VAR21,
VAR17,
VAR15,
VAR39,
VAR7,
VAR18,
VAR8,
VAR30,
VAR26,
VAR33,
VAR22
);
input VAR6;
input VAR31;
input [VAR19-1:0] VAR13;
input VAR37;
input VAR10;
output VAR3;
output [VAR19-1:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.behavioral.v | 1,572 | module MODULE1 (
VAR9 ,
VAR6,
VAR8,
VAR2,
VAR11,
VAR12
);
output VAR9 ;
input VAR6;
input VAR8;
input VAR2;
input VAR11;
input VAR12;
supply1 VAR4;
supply0 VAR15;
supply1 VAR3 ;
supply0 VAR7 ;
wire VAR1 ;
wire VAR10;
and VAR5 (VAR1 , VAR6, VAR8, VAR2, VAR11 );
nor VAR13 (VAR10, VAR12, VAR1 );
buf VAR14 (VAR9 , VAR10 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.behavioral.pp.v | 1,178 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xbar_0/synth/cpu_xbar_0.v | 14,553 | module MODULE1 (
VAR123,
VAR62,
VAR122,
VAR129,
VAR92,
VAR97,
VAR118,
VAR120,
VAR7,
VAR124,
VAR46,
VAR75,
VAR42,
VAR38,
VAR5,
VAR17,
VAR89,
VAR73,
VAR79,
VAR88,
VAR85,
VAR114,
VAR99,
VAR58,
VAR116,
VAR41,
VAR95,
VAR45,
VAR101,
VAR83,
VAR115,
VAR117,
VAR10,
VAR19,
VAR76,
VAR108,
VAR65,
VAR15,
VAR93,
VAR68
);
input wire ... | gpl-3.0 |
jkunkee/spartan3-blinkenlights | DasBlinkenLights.v | 1,042 | module MODULE1(
input clk,
input [3:0] VAR8,
input [7:0] VAR5,
output [7:0] VAR1,
output [3:0] VAR10, output [7:0] VAR2, input VAR3,
output VAR4
);
assign VAR10 = 4'hF;
assign VAR2 = 8'hFF;
assign VAR4 = VAR3;
wire [7:0] VAR7;
assign VAR1 = {
VAR7[6],
VAR7[0],
VAR7[5],
VAR7[3],
VAR7[1],
VAR7[4],
VAR7[2],
VAR7[7]
};
VAR... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/02CAD-JOYSTICK/Version_02/02 verilog/adc/adc.v | 1,081 | module MODULE1( input wire VAR4,
input VAR9,
input reset,
input rd,
output VAR5,
output reg VAR12,
output wire [7:0] VAR7
);
reg [7:0] VAR1;
VAR3 VAR2(.VAR9(VAR9), .VAR5(VAR5), .reset(reset));
VAR11 VAR10(.VAR5(VAR5), .reset(reset), .rd(rd), .wr(VAR12), .VAR6(VAR1), .VAR8(VAR7)); | gpl-3.0 |
rellermeyer/99tsp | verilog/sa/src/distance.v | 2,100 | module MODULE1(
input clk,
input rst,
input [63:0] VAR19,
input [63:0] VAR18,
input VAR8,
output VAR6,
output [31:0] out
);
reg VAR7, VAR15;
reg [31:0] VAR13, VAR2;
wire [15:0] VAR22;
wire VAR5;
VAR4 VAR17 (
.VAR14(clk),
.VAR11(VAR7),
.VAR9(VAR5),
.VAR3(VAR13[23:0]),
.VAR20(VAR22)
);
assign out = {19'b0,VAR22};
assign ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2_2.v | 1,990 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR1,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR4;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7,
VAR2,
VAR3
);
output VAR7;
input VAR2;
input VAR3;
supply1 VAR1;
supply0 VAR4;
VAR5 VAR6 (
.... | apache-2.0 |
trander1/Dual-Core-Processor | FinalProjectV3/Modules/processor.v | 11,666 | (VAR67<=4)?2:\
(VAR67<=8)?3:\
(VAR67<=16)?4:\
(VAR67<=32)?5:\
(VAR67<=64)?6:\
(VAR67<=128)?7:\
(VAR67<=256)?8:\
-1
module MODULE1(
VAR66, VAR34, VAR11, VAR4, VAR35, VAR81,
VAR33, VAR56, VAR17, VAR55, VAR80, clk
);
parameter VAR28 = 4; parameter VAR23 = 4; parameter VAR37 = 8; parameter VAR1 = 4; parameter VAR64 = 2; pa... | gpl-2.0 |
aj-michael/Digital-Systems | Lab6-Part2/MasterDataUnitI2C.v | 1,360 | module MODULE1(VAR17,VAR9,VAR4,VAR24,VAR12,VAR10,VAR22,VAR2,VAR1,VAR7,VAR15,VAR5,VAR23,VAR13);
input [19:0] VAR17; input [29:0] VAR9; input [VAR16-1:0] VAR4;
input VAR24;
input VAR12;
input VAR10;
input VAR22;
input VAR2;
input VAR1;
input VAR7;
input VAR15;
output [VAR16-1:0] VAR5;
output VAR23;
inout VAR13;
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.pp.blackbox.v | 1,320 | module MODULE1 (
VAR1,
VAR5 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR4
);
input VAR1;
input VAR5 ;
input VAR6 ;
output VAR3 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.pp.blackbox.v | 1,228 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR5 ,
VAR1,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.pp.blackbox.v | 1,570 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR12 ,
VAR6 ,
VAR8 ,
VAR10 ,
VAR11,
VAR2 ,
VAR1 ,
VAR4 ,
VAR5
);
output VAR9 ;
output VAR3 ;
input VAR7 ;
input VAR12 ;
input VAR6 ;
input VAR8 ;
input VAR10 ;
input VAR11;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.behavioral.pp.v | 2,221 | module MODULE1 (
VAR15 ,
VAR14 ,
VAR10 ,
VAR20 ,
VAR11 ,
VAR7 ,
VAR8,
VAR19,
VAR16 ,
VAR2
);
output VAR15 ;
input VAR14 ;
input VAR10 ;
input VAR20 ;
input VAR11 ;
input VAR7 ;
input VAR8;
input VAR19;
input VAR16 ;
input VAR2 ;
wire VAR9 ;
wire VAR18 ;
wire VAR5 ;
wire VAR12;
or VAR13 (VAR9 , VAR11, VAR20 );
or VAR6 (... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.v | 14,753 | module MODULE1
(
VAR55,
VAR67,
VAR35,
VAR75,
VAR21,
VAR44,
VAR111,
VAR78,
VAR12,
VAR95,
VAR93,
VAR30,
VAR63,
VAR3,
VAR60,
VAR50,
VAR37,
VAR105,
VAR73,
VAR90,
VAR11,
VAR15,
VAR77,
VAR72,
VAR10,
VAR89,
VAR79,
VAR97,
VAR1,
VAR36,
VAR61,
VAR87,
VAR103,
VAR5,
VAR110,
VAR52,
VAR8,
VAR41
);
parameter VAR39 = 32'h00000000;
par... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/byte_group_io.v | 22,133 | module MODULE1 #(
parameter VAR61 = 12'b111111111111,
parameter VAR80 = 12'b000000000000,
parameter VAR95 = "VAR150",
parameter VAR40 = "VAR127",
parameter VAR156 = "VAR52",
parameter VAR42 = 00,
parameter VAR168 = "VAR86",
parameter VAR141 = 12
)
(
inout [VAR141-1:0] VAR33,
input [9:0] VAR112,
output [VAR141-1:0] VAR1... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/ACA_I_N16_Q4.v | 1,397 | module MODULE1(
input [15:0] VAR13,
input [15:0] VAR9,
output [16:0] VAR2
);
wire [4:0] VAR4,VAR16,VAR6,VAR10,VAR1,VAR15,VAR12,VAR5,VAR7,VAR14,VAR3,VAR8,VAR11;
assign VAR4[4:0] = VAR13[3:0] + VAR9[3:0];
assign VAR16[4:0] = VAR13[4:1] + VAR9[4:1];
assign VAR6[4:0] = VAR13[5:2] + VAR9[5:2];
assign VAR10[4:0] = VAR13[6:3]... | gpl-3.0 |
kyzhai/NUNY | src/hardware/fail_new.v | 6,400 | module MODULE1 (
address,
VAR5,
VAR36);
input [11:0] address;
input VAR5;
output [11:0] VAR36;
tri1 VAR5;
wire [11:0] VAR38;
wire [11:0] VAR36 = VAR38[11:0];
VAR16 VAR30 (
.VAR34 (address),
.VAR15 (VAR5),
.VAR32 (VAR38),
.VAR25 (1'b0),
.VAR43 (1'b0),
.VAR31 (1'b1),
.VAR40 (1'b0),
.VAR9 (1'b0),
.VAR52 (1'b1),
.VAR24 (1'... | gpl-2.0 |
danbone/core | rtl/riscv_wb.v | 2,526 | module MODULE1 (
input clk,
input VAR10,
input VAR14,
output VAR21,
input [31:0] VAR18,
input VAR20,
input [VAR17-1:0] VAR12,
input [31:0] VAR1,
input [4:0] VAR5,
output [31:0] VAR9,
output [4:0] VAR19,
output VAR2
);
reg [31:0] VAR9;
reg [4:0] VAR19;
reg VAR2;
wire [31:0] VAR7;
wire [23:0] VAR16;
wire [15:0] VAR8;
wir... | mit |
omicronns/studies-sys-rek | lab4/abc/src/mul/mul.v | 33,724 | module MODULE1 (
clk, VAR84, VAR135, VAR93, VAR10
);
input clk;
input VAR84;
input [11 : 0] VAR135;
input [12 : 0] VAR93;
output [24 : 0] VAR10;
wire \VAR22/VAR35 ;
wire \VAR22/VAR33 ;
wire \VAR2/VAR128 ;
wire \VAR2/VAR29 ;
wire \VAR2/VAR61 ;
wire \VAR2/VAR62 ;
wire \VAR2/VAR86 ;
wire \VAR2/VAR119 ;
wire \VAR2/VAR99 ;
... | mit |
m-labs/milkymist | cores/tmu2/rtl/tmu2_ctlif.v | 4,339 | module MODULE1 #(
parameter VAR28 = 4'h0,
parameter VAR29 = 26
) (
input VAR7,
input VAR2,
input [13:0] VAR17,
input VAR5,
input [31:0] VAR6,
output reg [31:0] VAR19,
output reg irq,
output reg VAR18,
input VAR24,
output reg [6:0] VAR27,
output reg [6:0] VAR8,
output reg [5:0] VAR31,
output reg VAR21,
output reg VAR26,... | lgpl-3.0 |
eecsninja/duinocube-core | altera/vram_8Kx16.v | 11,421 | module MODULE1 (
VAR17,
VAR48,
VAR5,
VAR42,
VAR35,
VAR46,
VAR44,
VAR39,
VAR20,
VAR36,
VAR7,
VAR40,
VAR53);
input [12:0] VAR17;
input [12:0] VAR48;
input [1:0] VAR5;
input VAR42;
input VAR35;
input [15:0] VAR46;
input [15:0] VAR44;
input VAR39;
input VAR20;
input VAR36;
input VAR7;
output [15:0] VAR40;
output [15:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.blackbox.v | 1,522 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR4,
VAR3
);
output VAR9 ;
input VAR12 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR4;
input VAR3;
supply1 VAR11;
supply1 VAR5 ;
supply0 VAR10 ;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/next_hop_ram.v | 1,204 | module MODULE1(clk, addr, VAR2, VAR5, VAR12, en, reset);
input clk;
input [12:2] addr;
input [31:0] VAR2;
output [31:0] VAR5;
input [3:0] VAR12;
input en;
input reset;
wire [3:0] VAR4;
VAR11 VAR14 (
.address ( addr[12:2] ),
.VAR8 ( clk ),
.VAR6 ( VAR2[7:0] ),
.VAR1 ( en ),
.VAR10 ( VAR12[0] ),
.VAR13 ( VAR5[7:0] )
);
... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_xbar_0/system_xbar_0_stub.v | 5,742 | module MODULE1(VAR33, VAR16, VAR12, VAR52,
VAR56, VAR51, VAR23, VAR43, VAR45, VAR67,
VAR41, VAR75, VAR34, VAR26, VAR5, VAR46,
VAR73, VAR61, VAR49, VAR19, VAR76, VAR3, VAR35,
VAR36, VAR62, VAR39, VAR60, VAR21, VAR30,
VAR17, VAR42, VAR10, VAR69, VAR77, VAR20, VAR40,
VAR11, VAR55, VAR31, VAR78, VAR64, VAR74, VAR7,
VAR48, ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.functional.pp.v | 3,028 | module MODULE1( VAR19, VAR35, VAR16, VAR20, VAR32, VAR2, VAR37, VAR31, VAR22 );
input VAR2, VAR37, VAR32, VAR20, VAR16, VAR35;
inout VAR31, VAR22;
output VAR19;
wire VAR7;
not VAR1( VAR7, VAR2 );
wire VAR11;
not VAR25( VAR11, VAR32 );
wire VAR10;
not VAR29( VAR10, VAR16 );
wire VAR36;
and VAR12( VAR36, VAR7, VAR11, VAR... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/hls_saturation_encud.v | 4,433 | module MODULE2
VAR9 = 32,
VAR25 = 32,
VAR22 = 32
)
(
input clk,
input reset,
input VAR31,
input [VAR9-1:0] VAR10,
input [VAR25-1:0] VAR21,
output wire [VAR22-1:0] VAR14,
output wire [VAR22-1:0] VAR15
);
localparam VAR23 = (VAR9 > VAR25)? VAR9 : VAR25;
reg [VAR9-1:0] VAR16[0:VAR9];
reg [VAR25-1:0] VAR6[0:VAR9];
reg [VAR... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/ip_dram/controller/mig_7series_v2_3_rank_cntrl.v | 22,688 | module MODULE1 #
(
parameter VAR97 = 100, parameter VAR81 = "8", parameter VAR43 = 2, parameter VAR71 = 5, parameter VAR89 = 5, parameter VAR31 = 0, parameter VAR83 = 4, parameter VAR9 = 2, parameter VAR109 = 30, parameter VAR16 = 8, parameter VAR80 = 4, parameter VAR35 = 4, parameter VAR103 = 20, parameter VAR48 = 16,... | mit |
kkiningh/cs231n-project | src/rtl/MatrixInputQueue/GrayCounter.v | 1,183 | module MODULE1
(output reg [VAR7-1:0] VAR1,
input wire VAR2, input wire VAR5,
input wire VAR4);
reg [VAR7-1:0] VAR3;
always @ (posedge VAR4)
if (VAR5) begin
VAR3 <= {VAR7{1'VAR6 0}} + 1; VAR1 <= {VAR7{1'VAR6 0}}; end
else if (VAR2) begin
VAR3 <= VAR3 + 1;
VAR1 <= {VAR3[VAR7-1],
VAR3[VAR7-2:0] ^ VAR3[VAR7-1:1]};
end
end... | mit |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/lab4part2phase2.v | 1,667 | module MODULE1(VAR16, VAR24, VAR1, VAR22, VAR3, VAR14, VAR26, VAR27);
input [5:0] VAR16;
input VAR24, VAR1, VAR22;
output [5:0] VAR3;
output VAR14, VAR26, VAR27;
wire VAR12;
wire VAR15;
wire VAR8;
wire VAR2;
wire VAR25;
wire VAR23;
wire [6:0] dout;
wire VAR10;
parameter VAR20 = 20'd38400;
parameter VAR29 = 30'd70000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a_1.v | 2,444 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR1 ,
VAR12 ,
VAR3 ,
VAR8 ,
VAR5,
VAR6,
VAR2 ,
VAR9
);
output VAR11 ;
input VAR7 ;
input VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR8 ;
input VAR5;
input VAR6;
input VAR2 ;
input VAR9 ;
VAR4 VAR10 (
.VAR11(VAR11),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(... | apache-2.0 |
parallella/oh | mio/hdl/mio_regs.v | 7,854 | module MODULE1 #(parameter VAR43 = 8, parameter VAR58 = 32, parameter VAR31 = 104, parameter VAR29 = 18'h1070, parameter VAR12 = 7 )
(
input clk,
input VAR27,
input VAR7, input [VAR31-1:0] VAR30, output VAR34,
output VAR42, output [VAR31-1:0] VAR66, input VAR45,
output VAR55, output VAR25, output VAR38, output VAR49, o... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/mmio_if/synthesis/submodules/hps_sdram_p0_altdqdqs.v | 6,969 | module MODULE1 (
VAR74,
VAR7,
VAR4,
VAR61,
VAR6,
VAR53,
VAR54,
VAR84,
VAR28,
VAR93,
VAR24,
VAR13,
VAR30,
VAR67,
VAR89,
VAR65,
VAR87,
VAR35,
VAR79,
VAR91,
VAR46,
VAR16,
VAR58,
VAR44,
VAR63,
VAR69,
VAR15,
VAR40,
VAR31,
VAR45,
VAR81,
VAR66,
VAR42,
VAR71,
VAR68,
VAR49,
VAR11,
VAR62
);
input [7-1:0] VAR62;
input VAR74;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.symbol.v | 1,532 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR8 ,
input VAR6 ,
input VAR2 ,
input VAR5 ,
input VAR9,
input VAR7 ,
input VAR1
);
endmodule | apache-2.0 |
olofk/oh | elink/hdl/etx_protocol.v | 5,095 | module MODULE1 (
VAR48, VAR44, VAR21, VAR26, VAR32,
reset, clk, VAR18, VAR17, VAR10, VAR8,
VAR29, VAR15, VAR31, VAR5
);
parameter VAR34 = 104;
parameter VAR1 = 32;
parameter VAR35 = 32;
parameter VAR41 = 12'h000;
input reset;
input clk;
input VAR18;
input [VAR34-1:0] VAR17;
output VAR48;
output VAR44;
input VAR10; inpu... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_gt_common_1.v | 4,874 | module MODULE1 (
rst,
VAR9,
VAR5,
VAR58,
VAR57,
VAR68,
VAR24,
VAR46,
VAR67,
VAR30,
VAR66,
VAR1);
parameter VAR51 = 2;
parameter VAR18 = 27'h06801C1;
parameter VAR61 = 1'b1;
parameter VAR49 = 10'b0000110000;
input rst;
input VAR9;
output VAR5;
output VAR58;
output VAR57;
input VAR68;
input VAR24;
input [11:0] VAR46;
inp... | mit |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v | 6,954 | module MODULE1(VAR53,
VAR29,
VAR74,
VAR40,
VAR64,
VAR14,
VAR39,
VAR68,
VAR56,
VAR5,
VAR8,
VAR54,
VAR73,
VAR57,
VAR46);
input VAR53;
input VAR29;
input VAR74;
output VAR40;
input VAR64;
output VAR14;
input [4 : 0] VAR39;
output [31 : 0] VAR68;
input [4 : 0] VAR56;
output [31 : 0] VAR5;
input [4 : 0] VAR8;
output [31 : 0... | apache-2.0 |
jrward/qdbreakout | rtl/ball_logic.v | 4,181 | module MODULE1( input VAR17,
input VAR11,
input VAR2,
input VAR15,
input VAR4,
input VAR18,
output reg [9:0] VAR8,
output reg [9:0] VAR14 );
parameter VAR20 = 3'b000;
parameter VAR6 = 3'b001;
parameter VAR3 = 3'b010;
parameter VAR16 = 3'b011;
parameter VAR10 = 3'b100;
reg VAR21;
reg [2:0] VAR7;
reg [2:0] VAR1;
always @... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.blackbox.v | 1,288 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
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