repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
vad-rulezz/megabot | minsoc/bench/verilog/minsoc_memory_model.v | 5,866 | module MODULE1 (
VAR26, VAR21,
VAR20, VAR16, VAR25, VAR9, VAR13, VAR7,
VAR19, VAR17, VAR1
);
parameter VAR11 = 2;
input VAR26;
input VAR21;
input [31:0] VAR20;
output [31:0] VAR16;
input [31:0] VAR25;
input [3:0] VAR9;
input VAR13;
input VAR7;
input VAR19;
output VAR17;
output VAR1;
wire VAR12;
wire [3:0] VAR22;
wire [... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba fifo/fifo.v | 3,248 | module MODULE1 # (parameter VAR15 = 7, VAR24 = 1)(
input reset, VAR14,
input rd, wr,
input [VAR24-1:0] din,
output [VAR24-1:0] dout,
output VAR23,
output VAR10,
output reg VAR19
);
wire VAR8, VAR2;
reg VAR12, VAR20, VAR9, VAR13;
reg [VAR24-1:0] out;
always @ (posedge VAR14) VAR12 <= wr;
always @ (posedge VAR14) VAR20 <... | gpl-3.0 |
aap/pdp6 | verilog/iobus_3_connect.v | 3,315 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR7,
input wire VAR58,
input wire VAR60,
input wire VAR59,
input wire VAR2,
input wire VAR39,
input wire VAR33,
input wire VAR21,
input wire VAR25,
input wire [3:9] VAR17,
input wire [0:35] VAR55,
output wire [1:7] VAR5,
output wire [0:35] VAR43,
output wire... | mit |
jacgoudsmit/P8X32A_Emulation | Altera/top.v | 2,629 | module MODULE1
(
input VAR21, input VAR4,
inout [31:0] VAR14,
output [7:0] VAR32 );
reg VAR12;
wire [7:0] VAR25;
wire [31:0] VAR27, VAR5;
wire VAR11, VAR19, clk;
reg [23:0] VAR7;
reg VAR35;
wire VAR24;
wire VAR2;
wire [31:0] VAR33 = VAR14;
wire [4:0] VAR18;
VAR10 #( .VAR28("VAR15"),
.VAR23("VAR31"),
.VAR8(20000), .VAR1... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_csr.v | 52,455 | module MODULE1 #
( parameter
VAR134 = 2,
VAR47 = 1,
VAR187 = 1,
VAR17 = 0,
VAR150 = 0,
VAR136 = 8,
VAR45 = 32,
VAR113 = 1,
VAR131 = 72,
VAR46 = 1, VAR73 = 13, VAR108 = 10, VAR89 = 3,
VAR5 = 1,
VAR124 = 1,
VAR129 = 0,
VAR42 = 4, VAR43 = 3, VAR161 = 4, VAR77 = 5, VAR166 = 4, VAR66 = 6, VAR191 = 8, VAR137 = 13, VAR58 = 4,... | lgpl-3.0 |
PeterMagnusson/modexp | src/rtl/blockmem2r1w.v | 2,973 | module MODULE1(
input wire clk,
input wire [07 : 0] VAR5,
output wire [31 : 0] VAR6,
input wire [07 : 0] VAR8,
output wire [31 : 0] VAR4,
input wire wr,
input wire [07 : 0] VAR10,
input wire [31 : 0] VAR1
);
reg [31 : 0] VAR9 [0 : 255];
reg [31 : 0] VAR3;
reg [31 : 0] VAR7;
assign VAR6 = VAR3;
assign VAR4 = VAR7;
alway... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.functional.v | 1,374 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
wire VAR4;
buf VAR5 (VAR4, VAR2 );
buf VAR1 (VAR3 , VAR4 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_ecc.v | 7,264 | module MODULE1 (
VAR27, VAR11, VAR13, VAR58,
VAR72, VAR56, VAR16,
VAR70, VAR42,
VAR64, VAR73, VAR3, VAR22, VAR68,
VAR2, VAR40, VAR7,
VAR28, VAR71, VAR10,
VAR69, VAR9, VAR33,
VAR52, VAR20, VAR78,
VAR50
) ;
input VAR64;
input VAR73;
input VAR3;
input [63:0] VAR22;
input VAR68;
input [7:0] VAR2;
input [63:0] VAR40;
input ... | gpl-2.0 |
MarcoVogt/basil | firmware/modules/utils/cdc_pulse_sync.v | 1,162 | module MODULE1 (
input wire VAR6,
input wire VAR2,
input wire VAR7,
output wire VAR3
);
wire VAR5;
reg [1:0] VAR4;
always@(posedge VAR6) begin
VAR4[0] <= VAR2;
VAR4[1] <= VAR4[0];
end
reg VAR10;
VAR1 VAR10 = 0; always@(posedge VAR6) begin
if (VAR5)
VAR10 <= 0;
end
else if (!VAR4[1] && VAR4[0])
VAR10 <= 1;
end
reg [2:0]... | bsd-3-clause |
kylemsguy/FPGA-Litecoin-Miner | ICARUS-LX150/serial.v | 4,421 | module MODULE2 # (
parameter VAR24 = 115200,
parameter VAR7 = 100000000 )
( clk, VAR29, VAR3, VAR20, VAR34, VAR31, VAR21 );
input clk;
input VAR29;
wire VAR27;
wire [7:0] VAR32;
parameter VAR23 = VAR8;
parameter VAR23 = 24'h800000;
VAR33 #(.VAR7(VAR7), .VAR24(VAR24)) VAR1 (.clk(clk), .VAR30(VAR29), .VAR13(VAR27), .VAR2... | gpl-3.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/pipeWrap.v | 1,159 | module MODULE1(
input clk,
input VAR4,
input VAR19,
input [31:0] VAR20,
input [31:0] VAR15,
input [31:0] VAR9,
input [31:0] VAR3,
input VAR12,
output VAR16,
input [63:0] VAR2,
output VAR11,
input VAR6,
output [63:0] VAR21
);
reg VAR5;
VAR18(clk, VAR5, 1, VAR19 ? 0 : VAR5)
wire [64:0] VAR22;
VAR14 #(.VAR10("VAR17")) VAR... | mit |
manu3193/TextEditor | hvsync_generator.v | 1,288 | module MODULE1(clk, reset,VAR3, VAR6, VAR1, VAR4, VAR7);
input clk;
input reset;
output VAR3, VAR6;
output VAR1;
output [9:0] VAR4;
output [9:0] VAR7;
reg [9:0] VAR4;
reg [9:0] VAR7;
reg VAR5, VAR2;
reg VAR1;
always @(posedge clk)
begin
if(reset)
VAR4 <= 0;
end
else if(VAR4==10'h320) VAR4 <= 0;
else
VAR4 <= VAR4 + 1'b1... | mit |
gbraad/minimig-de1 | rtl/ctrl/qmem_bridge.v | 3,454 | module MODULE1 #(
parameter VAR8 = 22,
parameter VAR12 = 4,
parameter VAR37 = 32,
parameter VAR3 = 22,
parameter VAR5 = 2,
parameter VAR13 = 16
)(
input wire VAR11,
input wire [VAR8-1:0] VAR34,
input wire VAR15,
input wire VAR9,
input wire [VAR12-1:0] VAR16,
input wire [VAR37-1:0] VAR30,
output reg [VAR37-1:0] VAR38,
o... | gpl-3.0 |
defano/digital-design | uart/rtl/rx.v | 2,598 | module MODULE1(
clk,
reset,
VAR8,
MODULE1,
VAR2,
VAR3);
input clk;
input reset;
input VAR8; input MODULE1; output VAR2; output [7:0] VAR3;
wire VAR9;
wire VAR2;
reg [2:0] state;
reg [3:0] VAR12;
reg [3:0] VAR1;
reg [7:0] VAR3;
assign VAR2 = state == VAR4 && VAR9;
assign VAR9 = VAR12 == 4'hf || (!MODULE1 && VAR12 > 4'h8... | mit |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/crypt_cycle_salt.v | 3,014 | module MODULE1(
input [31:0] VAR18,
input [31:0] VAR19,
input [67:0] VAR27,
output [67:0] VAR16,
input VAR11,
output [31:0] VAR9,
output [31:0] VAR8
);
wire [31:0] VAR2 [14:0];
wire [31:0] VAR14 [14:0];
wire [67:0] VAR20 [14:0];
VAR3 VAR23 (VAR18, VAR19, VAR27, VAR20[0], VAR11, VAR2[0], VAR14[0]);
VAR3 VAR24 (VAR2[0], ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai_2.v | 2,461 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR1 ,
VAR9 ,
VAR12 ,
VAR3 ,
VAR11,
VAR4,
VAR6 ,
VAR5
);
output VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR9 ;
input VAR12 ;
input VAR3 ;
input VAR11;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR2 VAR8 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.functional.pp.v | 1,230 | module MODULE1 (
VAR4,
VAR1,
VAR2 ,
VAR3
);
input VAR4;
input VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Inverse_Clarke_Transform.v | 3,811 | module MODULE1
(
VAR17,
VAR2,
VAR3,
VAR7,
VAR15
);
input signed [17:0] VAR17; input signed [17:0] VAR2; output signed [17:0] VAR3; output signed [17:0] VAR7; output signed [17:0] VAR15;
wire signed [35:0] VAR1; wire signed [35:0] VAR10; wire signed [35:0] VAR11; wire signed [35:0] VAR16; wire signed [37:0] VAR18; wire ... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/typeb.v | 1,985 | module MODULE1
(
input VAR7,
input VAR4,
input VAR8,
input VAR3,
output VAR1,
input VAR2,
input VAR5
);
reg VAR6;
always @ (negedge VAR7 or negedge VAR4)
begin
if (VAR4== 1'b0)
VAR6 <= 1'b0;
end
else if (VAR7 == 1'b0)
if (VAR8==1'b1)
if (VAR5==1'b0)
VAR6 <= VAR3;
else
VAR6 <= VAR2;
end
assign VAR1 = VAR6;
endmodule | lgpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp4_1.v | 30,432 | module MODULE1(
clk,
VAR184,
VAR147,
VAR162,
VAR175,
VAR47,
VAR84,
VAR9,
VAR166,
VAR113
);
parameter VAR96 = 0; parameter VAR50 = 0; parameter VAR190 = 1;
input clk; input[47:0] VAR184; input[15:0] VAR147;
output[6:0] VAR162;
output[6:0] VAR175;
output[6:0] VAR47;
output[31:0] VAR84;
output[3:0] VAR9;
output[3:0] VAR16... | mit |
cr88192/bgbtech_bjx1core | srvcore/FpuFp64FromInt.v | 3,030 | module MODULE1(
clk,
enable,
VAR12,
VAR1,
VAR13
);
input clk;
input enable;
input VAR12;
input[63:0] VAR1;
output[63:0] VAR13;
reg VAR18;
reg VAR21;
reg[12:0] VAR27;
reg[12:0] VAR10;
reg[12:0] VAR4;
reg[12:0] VAR8;
reg[63:0] VAR20;
reg[63:0] VAR16;
reg[63:0] VAR2;
reg[63:0] VAR9;
reg[63:0] VAR15;
reg[63:0] VAR25;
reg[6... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/db/reconfig_pll_altpll.v | 4,366 | module MODULE1
(
clk,
VAR7,
VAR17) ;
output [9:0] clk;
input [1:0] VAR7;
output VAR17;
tri0 [1:0] VAR7;
wire [9:0] VAR12;
wire VAR35;
wire VAR18;
VAR28 VAR32
(
.VAR1(),
.clk(VAR12),
.VAR41(),
.VAR27(VAR35),
.VAR19(VAR35),
.VAR7(VAR7),
.VAR17(VAR18),
.VAR37(),
.VAR29(),
.VAR15(),
.VAR16(),
.VAR25()
,
.VAR2(1'b0),
.VAR20... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/spiral_4.v | 1,633 | module MODULE1(
VAR2,
VAR3,
VAR15,
VAR10,
VAR8
);
input signed [18:0] VAR2;
output signed [18+7:0] VAR3;
output signed [18+7:0] VAR15;
output signed [18+7:0] VAR10;
output signed [18+7:0] VAR8;
wire signed [25:0]
VAR7,
VAR13,
VAR1,
VAR9,
VAR17,
VAR5,
VAR14,
VAR12,
VAR4,
VAR6,
VAR11,
VAR16;
assign VAR7 = VAR2;
assign VA... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_vga_double.v | 1,941 | module MODULE1(
input wire clk,
input wire VAR3,
input wire VAR2,
input wire [ 5:0] VAR9,
input wire VAR6,
output reg [ 5:0] VAR5
);
reg [9:0] VAR11; reg [9:0] VAR8;
reg VAR4;
reg VAR16;
wire [ 7:0] VAR10;
always @(posedge clk) if( VAR3 )
VAR4 <= ~VAR4;
always @(posedge clk)
begin
if( VAR2 )
begin
VAR11[9:8] <= 2'b00;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.functional.v | 1,067 | module MODULE1 ();
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/ik_swift_hps_0.v | 28,530 | module MODULE1 #(
parameter VAR159 = 2,
parameter VAR180 = 2
) (
output wire VAR41, input wire VAR173, input wire [7:0] VAR122, input wire [31:0] VAR148, input wire [3:0] VAR96, input wire [2:0] VAR165, input wire [1:0] VAR157, input wire [1:0] VAR70, input wire [3:0] VAR86, input wire [2:0] VAR5, input wire VAR10, out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.behavioral.v | 2,996 | module MODULE1 (
VAR6 ,
VAR27 ,
VAR28 ,
VAR21 ,
VAR8 ,
VAR15 ,
VAR17
);
output VAR6 ;
output VAR27 ;
input VAR28 ;
input VAR21 ;
input VAR8 ;
input VAR15 ;
input VAR17;
supply1 VAR22;
supply0 VAR2;
supply1 VAR10 ;
supply0 VAR9 ;
wire VAR19 ;
wire VAR3 ;
wire VAR26 ;
reg VAR24 ;
wire VAR13 ;
wire VAR23 ;
wire VAR7 ;
wir... | apache-2.0 |
briburrell/amica | device/scrypt_mono_pll/ztex_ufm1_15y1.v | 10,892 | module MODULE1 (VAR66, reset, select, VAR37, VAR32, VAR52, VAR51, VAR47, VAR77, VAR15, VAR17, read, write);
input VAR66, select, reset, VAR37, VAR32, VAR52, VAR51, VAR47, VAR77, VAR15, VAR17;
input [7:0] read;
output [7:0] write;
function integer VAR91; input integer VAR18;
begin
VAR18 = VAR18-1;
for (VAR91=0; VAR18>0;... | gpl-3.0 |
csail-csg/riscy-OOO | procs/verilog/Register.v | 1,727 | module MODULE1 (
VAR2, reset,
enable,
VAR4, VAR1
);
parameter
VAR6 = 32,
VAR3 = {VAR6{1'b0}},
VAR5 = {VAR6{1'b0}};
input VAR2;
input reset;
input enable;
input [VAR6-1:0] VAR4;
output [VAR6-1:0] VAR1;
reg [VAR6-1:0] VAR7;
assign VAR1 = VAR7; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3_2.v | 2,175 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR8 ,
VAR7 ,
VAR5,
VAR6,
VAR9 ,
VAR10
);
output VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR5;
input VAR6;
input VAR9 ;
input VAR10 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
fzyz999/5-stage-MIPS | timer.v | 2,925 | module MODULE1 (VAR9,VAR12,VAR10,VAR3,VAR7,VAR13,irq);
input [3:2] VAR10;
input VAR9,VAR12,VAR3;
input [31:0] VAR7;
output [31:0] VAR13;
output irq;
reg [31:0] VAR2;
reg [31:0] VAR15;
reg [31:0] VAR16;
reg irq;
reg [1:0] VAR1,VAR11;
assign VAR13=(VAR10==2'b00)?VAR16:
(VAR10==2'b01)?VAR15:
(VAR10==2'b10)?VAR2:
32'h12345... | mit |
yipenghuang0302/csee4840_14 | software/peripheral/SoCKit_top.v | 30,815 | module MODULE1(
VAR94,
VAR238,
VAR240,
VAR220,
VAR213,
VAR223,
VAR34,
VAR184,
VAR193,
VAR13,
VAR9,
VAR157,
VAR180,
VAR62,
VAR53,
VAR145,
VAR236,
VAR198,
VAR170,
VAR178,
VAR107,
VAR210,
VAR30,
VAR206,
VAR113,
VAR21,
VAR124,
VAR177,
VAR95,
VAR202,
VAR105,
VAR100,
VAR104,
VAR181,
VAR134,
VAR58,
VAR68,
VAR209,
VAR3,
VAR131... | mit |
jas0n1ee/THU-DSD | FB/pio_red.v | 2,069 | module MODULE1 (
address,
VAR3,
clk,
VAR8,
VAR1,
VAR9,
VAR5,
VAR7
)
;
output [ 17: 0] VAR5;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR8;
input VAR1;
input [ 31: 0] VAR9;
wire VAR2;
reg [ 17: 0] VAR4;
wire [ 17: 0] VAR5;
wire [ 17: 0] VAR6;
wire [ 31: 0] VAR7;
assign VAR2 = 1;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb.functional.v | 1,881 | module MODULE1 (
VAR10,
VAR11,
VAR5 ,
VAR2 ,
VAR13 ,
VAR14 ,
VAR15
);
input VAR10;
input VAR11;
output VAR5 ;
input VAR2 ;
input VAR13 ;
input VAR14 ;
input VAR15 ;
wire VAR15 VAR6 ;
wire VAR3 ;
wire VAR1;
nand VAR9 (VAR6 , VAR15, VAR14 );
or VAR8 (VAR3 , VAR13, VAR2, VAR6 );
VAR4 VAR12 (VAR1, VAR3, VAR10, VAR11);
buf ... | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/message/message_stream_combiner.v | 4,649 | module MODULE1
parameter VAR6 = 4,
parameter VAR15 = 2,
parameter VAR34 = 32,
parameter VAR14 = 64,
parameter VAR21 = 6,
parameter VAR16 = 1024,
parameter VAR17 = 10
)
(
input clk,
input VAR28,
input wire [VAR34*VAR6-1:0] VAR2,
input wire [VAR6-1:0] VAR29,
output reg [VAR34-1:0] VAR19,
output reg VAR22,
output wire VAR... | mit |
Cognoscan/BoostDSP | verilog/src/sigmaDelta/sigmaDeltaFast.v | 1,512 | module MODULE1 #(
parameter VAR8 = 4,
parameter VAR4 = (1 << VAR8)
)
(
input clk, input rst, input en, input signed [VAR8-1:0] in, output reg [VAR4-1:0] VAR1 );
localparam VAR9 = 2**(2*VAR8);
reg signed [VAR8-1:0] VAR2;
reg [VAR8-1:0] VAR5 [VAR9-1:0];
reg [VAR4-1:0] VAR3 [VAR9-1:0];
integer VAR11;
integer VAR12;
intege... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mux.v | 12,907 | module MODULE1 #
(
parameter VAR64 = 4,
parameter VAR34 = 8,
parameter VAR60 = (VAR34>8),
parameter VAR44 = (VAR34/8),
parameter VAR20 = 0,
parameter VAR10 = 8,
parameter VAR55 = 0,
parameter VAR72 = 8,
parameter VAR90 = 1,
parameter VAR42 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR64-1:0] VAR58,
output wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.functional.v | 1,344 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
wire VAR3;
not VAR5 (VAR3, VAR1 );
buf VAR2 (VAR4 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.symbol.v | 1,570 | module MODULE1 (
input VAR1 ,
output VAR12 ,
output VAR10 ,
input VAR3,
input VAR4 ,
input VAR9 ,
input VAR5 ,
input VAR8
);
supply1 VAR7;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR11 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_8/synth/bd_350b_slot_2_w_0.v | 4,588 | module MODULE1 (
VAR32,
VAR47,
VAR12,
dout
);
input wire [0 : 0] VAR32;
input wire [0 : 0] VAR47;
input wire [0 : 0] VAR12;
output wire [2 : 0] dout;
VAR49 #(
.VAR21(1),
.VAR59(1),
.VAR38(1),
.VAR58(1),
.VAR50(1),
.VAR69(1),
.VAR62(1),
.VAR7(1),
.VAR22(1),
.VAR37(1),
.VAR42(1),
.VAR41(1),
.VAR3(1),
.VAR44(1),
.VAR33(1)... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_axis_dma_tx.v | 6,669 | module MODULE1 (
VAR34,
VAR5,
VAR28,
VAR17,
VAR31,
VAR1,
VAR20,
VAR25,
VAR9,
VAR43,
VAR7,
VAR32,
VAR44,
VAR2,
VAR41,
VAR33,
VAR11);
localparam VAR4 = 32'h00050062;
parameter VAR36 = 0;
input VAR34;
output VAR5;
input VAR28;
output VAR17;
output [31:0] VAR31;
input VAR1;
input VAR20;
input VAR25;
input VAR9;
input VAR43... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/AU280/fpga_10g/rtl/fpga.v | 25,463 | module MODULE1 (
input wire reset,
output wire VAR279,
output wire VAR141,
output wire VAR186,
input wire VAR111,
input wire VAR378,
output wire VAR250,
output wire VAR401,
input wire VAR97,
input wire VAR377,
output wire VAR420,
output wire VAR16,
input wire VAR239,
input wire VAR424,
output wire VAR180,
output wire V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat1_8.v | 2,376 | module MODULE1(
enable,
VAR5,
VAR4,
VAR9,
VAR6,
VAR8,
VAR7,
VAR3,
VAR2,
VAR1,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7
);
input enable;
input VAR5;
input signed [15:0] VAR4;
input signed [15:0] VAR9;
input signed [15:0] VAR6;
input signed [15:0] VAR8;
input signed [15:0] VAR7;
input signed [15:0] VAR3;
input signed [15:0] VAR2;
... | gpl-3.0 |
finnball/igloo | infra/hdl/multiplier.v | 2,567 | module MODULE1(
input clk,
input [VAR12 - 1 : 0] VAR8,
input [VAR12 - 1 : 0] VAR13,
output [VAR12 * 2 - 1 : 0] VAR5
);
parameter VAR12 = 2;
wire [VAR12 : 0] VAR8;
wire [VAR12 : 0] VAR13;
wire [2 * VAR12 - 1 : 0] VAR5;
assign VAR8 = { {VAR8[VAR12 - 1]}, {VAR8[VAR12 - 1 : 0]} };
assign VAR13 = { {VAR13[VAR12 - 1]}, {VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.functional.v | 1,566 | module MODULE1 (
VAR1 ,
VAR13,
VAR8,
VAR10,
VAR12,
VAR11
);
output VAR1 ;
input VAR13;
input VAR8;
input VAR10;
input VAR12;
input VAR11;
wire VAR9 ;
wire VAR4 ;
wire VAR3;
or VAR5 (VAR9 , VAR12, VAR10 );
or VAR7 (VAR4 , VAR8, VAR13 );
and VAR6 (VAR3, VAR9, VAR4, VAR11);
buf VAR2 (VAR1 , VAR3 );
endmodule | apache-2.0 |
lightstor/ssd-controller | ONFI/verilog/mkNandFlashController.v | 115,183 | module MODULE1(VAR168,
VAR195,
VAR254,
VAR213,
VAR201,
VAR39,
VAR234,
VAR398,
VAR205,
VAR209,
VAR142,
VAR351,
VAR305,
VAR220,
VAR418,
VAR164,
VAR338,
VAR314,
VAR361,
VAR347,
VAR268,
VAR311,
VAR6,
VAR118,
VAR207,
VAR48,
VAR273,
VAR231,
VAR159,
VAR334,
VAR318,
VAR92,
VAR193,
VAR71,
VAR246,
VAR146,
VAR323,
VAR438,
VAR387,... | bsd-3-clause |
krucios/Echo_module | src/servo_driver.v | 2,929 | module MODULE1 #(parameter VAR6 = 50000000) (
input wire clk,
input wire VAR8,
input wire[7:0] VAR15,
output reg VAR4 = 0,
output reg VAR3 = 0
);
parameter VAR10 = VAR6 / 1000;
parameter VAR5 = (VAR10 * 2) / 8'hFF;
parameter VAR1 = VAR10 * 21 + VAR10 / 3;
parameter VAR9 = VAR10 * 22;
reg[7:0] VAR12 = 0; reg[31:0] count... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.v | 2,331 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR11 ,
VAR4,
VAR7,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR11 ;
input VAR4;
input VAR7;
input VAR3 ;
input VAR8 ;
VAR5 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR... | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_200_400/example_design/clk_200_400_exdes.v | 4,956 | module MODULE1
parameter VAR16 = 100
)
( input VAR2,
input VAR19,
output VAR8,
input VAR6,
output VAR14
);
localparam VAR1 = 16;
wire VAR18 = !VAR14 || VAR6 || VAR19;
reg VAR12;
reg VAR17;
reg VAR3;
reg VAR20;
wire VAR15;
wire clk;
reg [VAR1-1:0] counter;
VAR10 VAR9
(.VAR5 (VAR9),
.VAR11 (VAR2));
VAR4 VAR7
( .VAR2 (VAR... | gpl-2.0 |
sheiksadique/USB-Uart | UART-IP.v | 1,618 | module MODULE1(
input VAR9, output VAR14, input VAR19, output VAR20, input VAR21,
output [7:0] VAR17,
output VAR4,
input [7:0] VAR16,
input VAR8
);
wire VAR22;
wire VAR18;
assign VAR14 = ~VAR1;
VAR2 VAR13(
.VAR9(VAR9),
.VAR22(VAR22)
);
VAR3 VAR7(
.VAR9(VAR9),
.VAR18(VAR18)
);
VAR10 VAR6(
.VAR16(VAR16), .VAR8(VAR8), .VA... | gpl-2.0 |
asicguy/gplgpu | hdl/de3d/de3d_top.v | 19,793 | module MODULE1
(
parameter VAR39 = 9,
parameter VAR95 = 4
)
(
input VAR2,
input VAR34,
input [31:0] VAR163,
input [8:2] VAR13,
input [8:2] VAR193,
input VAR229,
input [3:0] VAR3,
input VAR42,
output [31:0] VAR71,
input VAR63, input VAR191, input [31:0] VAR214,
input [31:0] VAR233,
input VAR153,
input [1:0] VAR215,
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai_1.v | 2,335 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR11 ,
VAR1 ,
VAR6,
VAR8,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR11 ;
input VAR1 ;
input VAR6;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR10 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_base/bsx.v | 11,075 | module MODULE1(
input VAR5,
input VAR51,
input VAR25,
input VAR41,
input [23:0] VAR30,
input [7:0] VAR75,
output [7:0] VAR48,
input [7:0] VAR12,
input [7:0] VAR40,
output [14:0] VAR16,
input VAR4,
input VAR8,
output VAR60,
output VAR28,
input [59:0] VAR47,
output [9:0] VAR49, output VAR20,
output [8:0] VAR18,
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.functional.v | 1,299 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
buf VAR3 (VAR2 , VAR1 );
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/axis_xgmii_tx_32.v | 18,569 | module MODULE1 #
(
parameter VAR12 = 32,
parameter VAR1 = (VAR12/8),
parameter VAR17 = (VAR12/8),
parameter VAR9 = 1,
parameter VAR26 = 1,
parameter VAR7 = 64,
parameter VAR23 = 0,
parameter VAR25 = 96,
parameter VAR22 = VAR23,
parameter VAR11 = 16,
parameter VAR20 = (VAR22 ? VAR11 : 0) + 1
)
(
input wire clk,
input wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.pp.blackbox.v | 1,244 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR4,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR1;
endmodule | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/bless/brouter_4x4.v | 17,881 | module MODULE1(
input VAR131 VAR162,
input VAR131 VAR82,
input VAR131 VAR185,
input VAR131 VAR119,
input VAR131 VAR14,
input VAR131 VAR137,
input VAR131 VAR4,
input VAR131 VAR126,
input VAR131 VAR96,
input VAR131 VAR179,
input VAR131 VAR69,
input VAR131 VAR60,
input VAR131 VAR239,
input VAR131 VAR3,
input VAR131 VAR59,... | mit |
csturton/wirepatch | system/hardware/cores/uart16550/rtl/verilog-backup/uart_wb.v | 5,698 | module MODULE1 (clk,
VAR4,
VAR6, VAR1, VAR2, VAR5,
VAR3, VAR7
);
input clk;
input VAR4;
input VAR6;
input VAR1;
input VAR2;
output VAR5;
output VAR3;
output VAR7;
wire VAR3;
reg VAR5;
always @(posedge clk or posedge VAR4)
begin
if (VAR4)
begin
VAR5 <= 1'b0;
end
else
begin
VAR5 <= VAR1 & VAR2 & ~VAR5; end
end
assign VAR... | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/manage_md/manage_tx.v | 7,483 | module MODULE1(
clk,
VAR56,
VAR45, VAR35,
VAR47,
VAR20,
VAR10,
VAR18,
VAR39,
VAR33,
VAR40,
VAR48,
VAR1,
VAR57,
VAR25,
VAR3,
VAR24
);
input clk;
input VAR56;
input [35:0]VAR45; input VAR35;
output VAR47;
input VAR20;
output VAR10;
input[138:0]VAR18;
input VAR39;
output [7:0]VAR33;
input VAR40;
input VAR48;
output [138:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv_8.v | 2,036 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR6,
VAR5 ,
VAR7
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR7 ;
VAR4 VAR3 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2,
VAR8
);
output VAR2;
input VAR8;
supply1 VAR1;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.symbol.v | 1,454 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR6 ,
input VAR9,
input VAR1
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit4.v | 6,119 | module MODULE1 (output reg VAR22, VAR23, VAR3, VAR1, VAR4, VAR10, VAR15, VAR18,VAR5,VAR6,VAR9,VAR24,VAR11,output reg[4:0] VAR16, output reg[3:0] VAR17, input VAR19, VAR8,VAR7, input [31:0] VAR14,input [3:0] VAR13);
reg [4:0] VAR12, VAR21;
task VAR20;
input [17:0] VAR2;
fork
{VAR17,VAR22, VAR23, VAR3, VAR1,VAR16, VAR4, ... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v | 4,089 | module MODULE1
(
input VAR3,
output VAR5,
output VAR1,
input reset,
output VAR2
);
VAR6 VAR4
(
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.reset(reset),
.VAR2(VAR2)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.functional.pp.v | 2,027 | module MODULE1 (
VAR16 ,
VAR12 ,
VAR14 ,
VAR6 ,
VAR5 ,
VAR4,
VAR10,
VAR15 ,
VAR9
);
output VAR16 ;
input VAR12 ;
input VAR14 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR10;
input VAR15 ;
input VAR9 ;
wire VAR17 ;
wire VAR2 ;
wire VAR8;
or VAR11 (VAR17 , VAR14, VAR12, VAR6 );
nand VAR13 (VAR2 , VAR5, VAR17 );
VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.v | 2,353 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR3 ,
VAR11 ,
VAR1 ,
VAR8,
VAR6,
VAR2 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR8;
input VAR6;
input VAR2 ;
input VAR9 ;
VAR10 VAR7 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR... | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/button_painter.v | 2,485 | module MODULE1(
input wire [1:0] VAR16,
input wire [2:0] VAR28,
input wire [3:0] VAR33,
output reg [11:0] VAR18
);
wire [4:0] VAR24, VAR41, VAR44, VAR27, VAR56, VAR32, VAR39, VAR29, VAR47, VAR22, VAR45, VAR8, VAR36, VAR6, VAR49, VAR57, VAR15;
reg [4:0] VAR12;
reg [4:0] VAR50;
VAR43 VAR11 (
.VAR33({VAR33-2'b11}[2:0]),
.... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.blackbox.v | 1,396 | module MODULE1 (
VAR10 ,
VAR7,
VAR3,
VAR8,
VAR6,
VAR4
);
output VAR10 ;
input VAR7;
input VAR3;
input VAR8;
input VAR6;
input VAR4;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp.symbol.v | 1,456 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR2 ,
input VAR6,
input VAR7
);
supply1 VAR3;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_poc_tap_base.v | 10,344 | module MODULE1 #
(parameter VAR32 = 10,
parameter VAR44 = "VAR49",
parameter VAR23 = 100,
parameter VAR8 = 8,
parameter VAR27 = 7,
parameter VAR14 = 112)
(
VAR6, VAR3, VAR50, VAR24, VAR16, VAR48, VAR51,
VAR41, clk, VAR7, VAR38, VAR10, rst,
VAR35
);
function integer VAR40 (input integer VAR1); begin
VAR1 = VAR1 - 1;
for... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_drp.v | 38,880 | module MODULE1 #
(
parameter VAR194 = "VAR86", parameter VAR131 = "3.0", parameter VAR195 = "VAR43", parameter VAR139 = "VAR22", parameter VAR48 = "VAR118", parameter VAR9 = "VAR43", parameter VAR16 = "VAR118", parameter VAR36 = 0, parameter VAR88 = 0, parameter VAR42 = 2'd1, parameter VAR126 = 5'd21
)
(
input VAR45,
i... | lgpl-3.0 |
freecores/zet86 | soc/vga/rtl/char_rom_b16.v | 16,672 | module MODULE1 (clk, rst, VAR61, VAR22, addr, VAR64, VAR6);
input clk;
input rst;
input VAR61;
input VAR22;
input [11:0] addr;
output [7:0] VAR64;
input [7:0] VAR6;
wire VAR79, VAR83;
wire [7:0] VAR26, VAR47;
VAR62 VAR63 (.VAR46(VAR47),
.VAR74 (VAR79),
.VAR7 (addr[10:0]),
.VAR71 (clk),
.VAR67 (VAR6),
.VAR69 (VAR79),
.V... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/sram_8192.v | 9,605 | module MODULE1 (
VAR4,
VAR56,
VAR14,
VAR19,
VAR28,
VAR38,
VAR43);
input VAR4;
input [71:0] VAR56;
input [12:0] VAR14;
input VAR19;
input [12:0] VAR28;
input VAR38;
output [71:0] VAR43;
tri1 VAR4;
tri1 VAR19;
tri0 VAR38;
wire [71:0] VAR55;
wire [71:0] VAR43 = VAR55[71:0];
VAR3 VAR2 (
.VAR34 (VAR28),
.VAR20 (VAR4),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.pp.blackbox.v | 1,342 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4,
VAR1,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/CPC2.v | 1,269 | module MODULE1(
input VAR1,
input VAR13,
input VAR5,
inout VAR3,
inout VAR2,
inout VAR18,
inout VAR4,
inout VAR6,
inout VAR16,
output VAR12,
output VAR9,
output [23:0] VAR10,
output VAR7,
input VAR8,
output VAR15,
input [1:0] VAR11,
output [7:0] VAR14,
input [3:0] VAR17
);
endmodule | gpl-3.0 |
samyk/proxmark3 | fpga/hi_iso14443a.v | 21,997 | module MODULE1(
VAR39,
VAR1, VAR21, VAR59, VAR61, VAR3, VAR28,
VAR8, VAR22,
VAR19, VAR45, VAR52, VAR5,
VAR38,
VAR43
);
input VAR39;
output VAR1, VAR21, VAR59, VAR61, VAR3, VAR28;
input [7:0] VAR8;
output VAR22;
input VAR52;
output VAR19, VAR45, VAR5;
output VAR38;
input [3:0] VAR43;
wire VAR22 = VAR39;
reg VAR15;
reg [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4.pp.symbol.v | 1,330 | module MODULE1 (
input VAR4 ,
input VAR8 ,
input VAR3 ,
input VAR5 ,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR9,
input VAR7
);
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_pro.v | 41,349 | module MODULE1 (
VAR174,
VAR70,
VAR229,
VAR21,
VAR2,
VAR86,
VAR113,
VAR182,
VAR195,
VAR103,
VAR196,
VAR35,
VAR118,
VAR192,
VAR30,
VAR125,
VAR141,
VAR111,
VAR9,
VAR1,
VAR140,
VAR4,
VAR215,
VAR23,
VAR40,
VAR100,
VAR92,
VAR94,
VAR144,
VAR55,
VAR206,
VAR155,
VAR175,
VAR65
);
parameter VAR176 = 5'd1;
parameter VAR36 = 5'd2;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.symbol.v | 1,294 | module MODULE1 (
input VAR8,
input VAR1,
input VAR5,
input VAR2,
output VAR9
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_afi_block.v | 18,426 | module MODULE1
VAR28 = 2,
VAR27 = 8,
VAR44 = 1,
VAR36 = 1,
VAR50 = 0,
VAR9 = 0,
VAR19 = "VAR6",
VAR17 = 5
)
(
VAR40,
VAR24,
VAR13,
VAR47,
VAR3,
VAR25,
VAR45,
VAR7,
VAR48,
VAR4,
VAR37,
VAR51,
VAR41,
VAR29,
VAR16,
VAR15
);
input VAR40;
input VAR24;
input [VAR17-1:0] VAR13;
localparam VAR31 = 2**VAR17;
localparam VAR21 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_m.v | 2,094 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR2 ,
VAR6,
VAR7,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR6;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR4 VAR8 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR9,
VAR2
);
output VAR1;
... | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/flow/buffer_AA.v | 2,340 | module MODULE1
parameter VAR7 = 32,
parameter VAR10 = 64,
parameter VAR9 = 6
)
(
input wire clk,
input wire VAR12,
input wire VAR15,
input wire [VAR7-1: 0] VAR13,
input wire VAR1,
output reg VAR5,
output reg [VAR7-1: 0] VAR8,
output reg VAR3,
output reg VAR2
);
reg [VAR10-1:0] VAR14;
reg [VAR7-1: 0] VAR11[VAR10-1:0];
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.blackbox.v | 1,356 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR9 ,
VAR4 ,
VAR5
);
output VAR3 ;
output VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR5;
supply1 VAR7;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
sharebrained/medusa | hdl/medusa_cape/strip_ws2812.v | 1,940 | module MODULE1 (
input VAR30,
input VAR6,
input [7:0] VAR26,
input [7:0] VAR8,
input [7:0] VAR14,
input [8:0] VAR12,
input VAR33,
input VAR16,
output VAR20
);
parameter VAR4;
parameter VAR5 = 0;
wire VAR27 = VAR6;
wire [8:0] VAR24 = VAR12;
wire [23:0] VAR21 = { VAR26, VAR8, VAR14 };
wire VAR3 = VAR33;
wire VAR11 = VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_1.v | 2,424 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR6,
VAR5,
VAR11 ,
VAR12
);
output VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR6;
input VAR5;
input VAR11 ;
input VAR12 ;
VAR8 VAR7 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.symbol.v | 1,433 | module MODULE1 (
input VAR9,
input VAR6,
input VAR7,
input VAR8,
input VAR5,
output VAR10
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.pp.blackbox.v | 1,420 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR6 ,
VAR9 ,
VAR4 ,
VAR3 ,
VAR5,
VAR8,
VAR7 ,
VAR2
);
output VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR5;
input VAR8;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.functional.pp.v | 1,069 | module MODULE1( VAR12, VAR7, VAR4, VAR15, VAR9, VAR3 );
input VAR15, VAR7, VAR4;
inout VAR9, VAR3;
output VAR12;
wire VAR6;
and VAR13( VAR6, VAR15, VAR7 );
wire VAR14;
not VAR5( VAR14, VAR4 );
wire VAR1;
and VAR8( VAR1, VAR14, VAR15 );
wire VAR10;
and VAR2( VAR10, VAR7, VAR4 );
or VAR11( VAR12, VAR6, VAR1, VAR10 );
end... | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/PmodOLED_Source/PmodOLEDCtrl.v | 4,014 | module MODULE1(
VAR24,
VAR34,
VAR17,
VAR23,
VAR1,
VAR7,
VAR5,
VAR8,
VAR6,
VAR9,
VAR18,
VAR25
);
input VAR24;
input VAR34;
input VAR17;
output VAR23;
output VAR1;
output VAR7;
output VAR5;
output VAR8;
output VAR6;
output VAR9;
input [9:0] VAR18;
input [9:0] VAR25;
wire VAR23, VAR1, VAR7, VAR5;
wire VAR9, VAR6, VAR8;
wi... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/dpram_32_32x16_be/dpram_32_32x16_be_bb.v | 7,635 | module MODULE1 (
VAR4,
VAR7,
VAR1,
VAR8,
VAR2,
VAR6,
VAR3,
VAR5);
input [31:0] VAR4;
input VAR7;
input [3:0] VAR1;
input [3:0] VAR8;
input [3:0] VAR2;
input VAR6;
input VAR3;
output [31:0] VAR5;
endmodule | gpl-3.0 |
lucasrangit/Multicycle_MIPS | mipsmulti.v | 8,487 | module MODULE4(input clk, reset,
output [31:0] VAR38, VAR77,
output VAR11,
input [31:0] VAR37);
wire VAR79, VAR41, VAR58, VAR25,
VAR54, VAR20, VAR22, VAR66;
wire [1:0] VAR43;
wire [1:0] VAR23;
wire [2:0] VAR29;
wire [5:0] VAR62, VAR18;
MODULE1 MODULE3(clk, reset, VAR62, VAR18, VAR79,
VAR41, VAR11, VAR58, VAR25,
VAR54, ... | apache-2.0 |
CospanDesign/nysa-sata | rtl/link/sata_link_layer.v | 11,216 | module MODULE1 (
input rst, input clk,
output VAR24,
input VAR67,
output VAR63,
input VAR13,
input VAR27,
output VAR74,
input VAR91,
output [31:0] VAR20,
output VAR66,
input [31:0] VAR25,
input [3:0] VAR94,
input VAR54,
output VAR69,
input [31:0] VAR33,
input [23:0] VAR29,
input VAR30,
output VAR7,
input VAR37,
output ... | mit |
kevintownsend/linked_list_fifo | linked_list_fifo_gold.v | 1,566 | module MODULE1(rst, clk, VAR14, VAR11, VAR4, VAR15, VAR2, VAR18, VAR6, VAR3, VAR1);
parameter VAR10 = 8;
parameter VAR13 = 32;
parameter VAR5 = 8;
parameter VAR16 = VAR7(VAR5-1);
parameter VAR9 = VAR7(VAR13-1);
input rst, clk, VAR14;
input [VAR16-1:0] VAR11;
input VAR4;
input [VAR16-1:0] VAR15;
input [VAR10-1:0] VAR2;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.symbol.v | 1,217 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd_1.v | 1,928 | module MODULE1 (
VAR1,
VAR6,
VAR2 ,
VAR4
);
input VAR1;
input VAR6;
input VAR2 ;
input VAR4 ;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
VAR3 VAR5 ();
endmodule | apache-2.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | freqmeter.v | 3,620 | module MODULE1
( input rst , input VAR3 , input VAR4 , output [15:0] VAR7);
reg VAR5;
reg [6:0] VAR2;
always @(posedge VAR4)
if (VAR2==7'd99) {VAR2,VAR5} <= {7'd0,!VAR5};
else VAR2 <= VAR2+1'b1;
localparam VAR6 = 16;
reg [VAR6-1:0] VAR1,VAR8,VAR1,VAR8;
always @(posedge VAR3)
if (!VAR5) VAR1 <= 12'd0;
else VAR1 <= VAR1+... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.behavioral.v | 1,694 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR9
);
output VAR7 ;
input VAR13 ;
input VAR9;
supply1 VAR4;
supply1 VAR10 ;
supply0 VAR6 ;
supply1 VAR5;
supply1 VAR1 ;
supply0 VAR2 ;
wire VAR12;
or VAR3 (VAR12, VAR13, VAR9 );
VAR8 VAR11 (VAR7 , VAR12, VAR4, VAR6);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.behavioral.v | 1,495 | module MODULE1( VAR5, VAR2, VAR6, VAR7 );
input VAR7, VAR6, VAR5;
output VAR2;
VAR3 VAR1(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR7(VAR7));
VAR3 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR7(VAR7)); | apache-2.0 |
Mahdi89/eTeak | SELF_files/flipflop.v | 1,346 | module MODULE1(
VAR1 , VAR2,
clk , reset );
input VAR1, clk, reset ;
output VAR2;
reg VAR2;
always @ ( posedge clk or posedge reset)
if (reset) begin
VAR2 <= 1'b0;
end else begin
VAR2 <= VAR1;
end
endmodule | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_64.behavioral.v | 1,027 | module MODULE1( );
VAR3 VAR2();
VAR3 VAR1(); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.functional.pp.v | 30,865 | module MODULE1 (VAR106, VAR113,VAR24,VAR134,
VAR20, VAR131, VAR130, VAR44, VAR31, VAR42, VAR65, VAR110, VAR94, VAR17,
VAR120, VAR129, VAR102, VAR51, VAR48, VAR40, VAR93, VAR19, VAR66,
VAR62, VAR71, VAR95, VAR69
,VAR7, VAR73, VAR101, VAR13, VAR107, VAR5, VAR64, VAR34,
VAR127, VAR112
);
input VAR71;
input VAR17;
input VA... | apache-2.0 |
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