repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
housq/lc3 | LC3_datapath.v | 8,872 | module MODULE1(
input clk,
input reset,
input [15:0] VAR40,
input [1:0] VAR71,
input [1:0] VAR33,
input [1:0] VAR55,
input VAR77,
input [1:0] VAR27,
input [1:0] VAR20,
input VAR48,
input VAR54,
input VAR35,
input [7:0] VAR45,
input [1:0] VAR44,
input [1:0] VAR74,
input [2:0] VAR15,
input VAR36,
input VAR17,
input VAR53... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_g/sky130_fd_sc_hd__udp_pwrgood_pp_g.blackbox.v | 1,251 | module MODULE1 (
VAR1,
VAR2 ,
VAR3
);
output VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/nic/des_nic/rtl/des_nic_input_block.v | 4,450 | module MODULE1
(
input wire clk,
input wire reset,
input wire [VAR13-1:0] VAR6,
input wire VAR11,
input wire VAR10,
output wire [(2 * VAR13)-1:0] VAR16,
output wire [(2 * VAR13)-1:0] VAR4,
output wire [VAR13-3:0] VAR20,
output wire VAR18
);
wire [VAR2:0] VAR19;
wire VAR7;
VAR17 VAR15
(
.clk (clk),
.reset (reset),
.VAR1... | gpl-3.0 |
open-fpga-nvm/open-nvm-source | fpga/MRAM/Top_MRAM.v | 20,117 | module MODULE1(
input VAR58,
input rst,
input VAR54,
output VAR90,
output VAR40,
output VAR57,
output VAR25,
output VAR46,
output VAR42,
output VAR77,
output [17:0] VAR21,
inout [7:0] VAR1,
inout [7:0] VAR61,
output [7:0] VAR35,
output [7:0] VAR7,
output [3:0] VAR44
);
parameter
VAR67 = 00,
VAR33= 01, VAR73= 02, VAR63=... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_f_v1_00_a/hdl/verilog/cf_ddsx.v | 11,409 | module MODULE1 (
VAR18,
VAR21,
VAR81,
VAR69,
VAR82,
VAR66,
VAR64,
VAR44,
VAR57,
VAR12,
VAR67,
VAR5,
VAR58,
VAR28,
VAR84);
input VAR18;
output [13:0] VAR21;
output [13:0] VAR81;
output [13:0] VAR69;
output [13:0] VAR82;
output [13:0] VAR66;
output [13:0] VAR64;
output [13:0] VAR44;
output [13:0] VAR57;
output [13:0] VAR... | mit |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/SyncResetA.v | 2,756 | module MODULE1 (
VAR5,
VAR2,
VAR1
);
parameter VAR3 = 1 ;
input VAR2 ;
input VAR5 ;
output VAR1 ;
reg [VAR3:0] VAR4 ;
wire [VAR3+1:0] VAR6 = {VAR4, ~ VAR7} ;
assign VAR1 = VAR4[VAR3] ;
always @( posedge VAR2 or VAR8 VAR5 )
begin
if (VAR5 == VAR7)
begin
VAR4 <= VAR9 {VAR3+1 {VAR7}} ;
end
else
begin
VAR4 <= VAR9 VAR6[VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.behavioral.v | 2,996 | module MODULE1 (
VAR23 ,
VAR33 ,
VAR11 ,
VAR20 ,
VAR13 ,
VAR15 ,
VAR31
);
output VAR23 ;
output VAR33 ;
input VAR11 ;
input VAR20 ;
input VAR13 ;
input VAR15 ;
input VAR31;
supply1 VAR4;
supply0 VAR7;
supply1 VAR14 ;
supply0 VAR25 ;
wire VAR30 ;
wire VAR27 ;
wire VAR9 ;
reg VAR16 ;
wire VAR21 ;
wire VAR32 ;
wire VAR12 ... | apache-2.0 |
walkthetalk/fsref | ip/axis_generator/src/axis_generator.v | 7,576 | module MODULE1 #
(
parameter integer VAR93 = 2,
parameter integer VAR67 = 8,
parameter integer VAR96 = 0,
parameter integer VAR19 = 12,
parameter integer VAR43 = 12,
parameter integer VAR7 = 0
)
(
input wire clk,
input wire VAR58,
input wire VAR22,
input wire [VAR19-1:0] VAR72,
input wire [VAR43-1:0] VAR91,
input wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp.behavioral.pp.v | 3,037 | module MODULE1 (
VAR11 ,
VAR23 ,
VAR2 ,
VAR17 ,
VAR18 ,
VAR7 ,
VAR9,
VAR3 ,
VAR8 ,
VAR29 ,
VAR15
);
output VAR11 ;
output VAR23 ;
input VAR2 ;
input VAR17 ;
input VAR18 ;
input VAR7 ;
input VAR9;
input VAR3 ;
input VAR8 ;
input VAR29 ;
input VAR15 ;
wire VAR31 ;
wire VAR6 ;
wire VAR12 ;
reg VAR27 ;
wire VAR30 ;
wire VA... | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkDM_Mem_Tap.v | 35,493 | module MODULE1(VAR93,
VAR119,
VAR81,
VAR57,
VAR16,
VAR158,
VAR214,
VAR100,
VAR59,
VAR15,
VAR101,
VAR69,
VAR188,
VAR82,
VAR118,
VAR154,
VAR28,
VAR29,
VAR192,
VAR46,
VAR196,
VAR107,
VAR37,
VAR121,
VAR105,
VAR42,
VAR205,
VAR13,
VAR143,
VAR184,
VAR103,
VAR182,
VAR97,
VAR24,
VAR142,
VAR173,
VAR138,
VAR50,
VAR134,
VAR8,
VAR6... | apache-2.0 |
jeremysalwen/combinatorial_aes | rtl/aes_192.v | 5,662 | module MODULE1 (state, VAR45, out);
input [127:0] state;
input [191:0] VAR45;
output [127:0] out;
reg [127:0] VAR32;
reg [191:0] VAR12;
wire [127:0] VAR37, VAR6, VAR54, VAR5, VAR39, VAR8, VAR42, VAR27, VAR38, VAR20, VAR16;
wire [191:0] VAR47, VAR26, VAR50, VAR11, VAR25, VAR36, VAR24, VAR17, VAR31, VAR3, VAR51;
wire [12... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_0/RAT_Mux4x1_8_0_0_stub.v | 1,339 | module MODULE1(VAR6, VAR4, VAR5, VAR3, VAR1, VAR2)
;
input [7:0]VAR6;
input [7:0]VAR4;
input [7:0]VAR5;
input [7:0]VAR3;
input [1:0]VAR1;
output [7:0]VAR2;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.behavioral.pp.v | 5,425 | module MODULE1( VAR1, VAR9, VAR3, VAR5, VAR2, VAR10, VAR6, VAR7, VAR8 );
input VAR2, VAR10, VAR6, VAR3, VAR1, VAR9;
inout VAR7, VAR8;
output VAR5;
VAR11 VAR4(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR10(VAR10),.VAR6(VAR6),.VAR7(VAR7),.VAR8(VAR8));
VAR11 VAR12(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.V... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/First_Phase_M.v | 1,288 | module MODULE1
(
input wire clk, input wire rst, input wire VAR1, input wire [VAR2-1:0] VAR8, input wire [VAR2-1:0] VAR5,
output wire [VAR2-1:0] VAR7, output wire [VAR2-1:0] VAR4
);
VAR3 #(.VAR2(VAR2)) VAR9 ( .clk(clk),
.rst(rst),
.VAR1(VAR1),
.VAR11(VAR8),
.VAR10(VAR7)
);
VAR3 #(.VAR2(VAR2)) VAR6 ( .clk(clk),
.rst(rst... | gpl-3.0 |
dawsonjon/Chips-2.0 | static/chips_lib.v | 56,845 | module MODULE9(
VAR43,
VAR10,
VAR25,
VAR23,
VAR55,
clk,
rst,
VAR34,
VAR59,
VAR15,
VAR29);
input clk;
input rst;
input [31:0] VAR43;
input VAR25;
output VAR15;
input [31:0] VAR10;
input VAR23;
output VAR29;
output [31:0] VAR34;
output VAR59;
input VAR55;
reg VAR9;
reg [31:0] VAR49;
reg VAR42;
reg VAR35;
reg [3:0] state;... | mit |
perillamint/humbleverilogcalc | sixbitfactorial.v | 2,351 | module MODULE1(VAR12, out, VAR16);
input[5:0] VAR12;
output[5:0] out;
output VAR16;
wire[15:0] VAR32;
wire[15:0] VAR15;
wire[5:0] VAR36;
wire[5:0] VAR33;
wire[5:0] VAR22;
wire[5:0] VAR1;
wire[5:0] VAR25;
wire[5:0] VAR7;
wire[5:0] VAR34;
wire[5:0] VAR31;
wire[5:0] VAR35;
wire[5:0] VAR37;
wire[5:0] VAR6;
wire[5:0] VAR38;... | gpl-3.0 |
peteasa/oh | src/mio/hdl/mio_if.v | 5,280 | module MODULE1 (
VAR5, VAR38, VAR33, VAR11, VAR9,
VAR2,
clk, VAR15, VAR17, VAR21, VAR7, VAR37, VAR1, VAR40,
VAR29, VAR32, VAR18, VAR19, VAR27,
VAR4
);
parameter VAR14 = 32; parameter VAR8 = 104; parameter VAR6 = 128;
input clk; input VAR15; input VAR17; input VAR21; input VAR7; input [7:0] VAR37; input [4:0] VAR1; inpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.functional.pp.v | 1,168 | module MODULE1( VAR11, VAR14, VAR3, VAR6, VAR4 );
input VAR14, VAR11;
inout VAR6, VAR4;
output VAR3;
wire VAR2;
not VAR13( VAR2, VAR11 );
wire VAR10;
and VAR12( VAR10, VAR2, VAR14 );
wire VAR7;
not VAR8( VAR7, VAR14 );
wire VAR5;
and VAR1( VAR5, VAR7, VAR11 );
or VAR9( VAR3, VAR10, VAR5 );
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/bram_fifo/bram_fifo.v | 2,887 | module MODULE1
parameter VAR29 = 32'h0000,
parameter VAR14 = 32'h0000,
parameter VAR16 = 32,
parameter VAR35 = 32'h0000,
parameter VAR20 = 32'h0000,
parameter VAR21 = 32'h8000*8,
parameter VAR5 = 95, parameter VAR42 = 5 ) (
input wire VAR17,
input wire VAR24,
input wire [VAR16-1:0] VAR26,
inout wire [31:0] VAR6,
input ... | bsd-3-clause |
chiragsakhuja/gpu | fb_block_bb.v | 5,645 | module MODULE1 (
address,
VAR1,
VAR3,
VAR4,
VAR2);
input [7:0] address;
input VAR1;
input [7:0] VAR3;
input VAR4;
output [7:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/hps_sdram_p0_reset.v | 4,389 | module MODULE1(
VAR36,
VAR15,
VAR33,
VAR4,
VAR21,
VAR32,
VAR23,
VAR24,
VAR7,
VAR39,
VAR20,
VAR18,
VAR14,
VAR11,
VAR38,
VAR8,
VAR37,
VAR35,
VAR29,
VAR3
);
parameter VAR6 = "";
parameter VAR31 = 1;
input VAR36;
input VAR15;
input VAR33;
input VAR4;
input VAR21;
input VAR32;
input VAR23;
output VAR24;
output VAR7;
input [... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo_1.v | 2,334 | module MODULE2 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR2,
VAR9,
VAR3,
VAR5 ,
VAR4
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR2;
input VAR9;
input VAR3;
input VAR5 ;
input VAR4 ;
VAR6 VAR8 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 ... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/synth/design_1_auto_pc_0.v | 14,655 | module MODULE1 (
VAR87,
VAR41,
VAR38,
VAR42,
VAR84,
VAR81,
VAR7,
VAR73,
VAR102,
VAR54,
VAR79,
VAR71,
VAR105,
VAR11,
VAR12,
VAR27,
VAR57,
VAR4,
VAR1,
VAR74,
VAR40,
VAR18,
VAR3,
VAR77,
VAR39,
VAR106,
VAR52,
VAR66,
VAR61,
VAR101,
VAR96,
VAR55,
VAR108,
VAR112,
VAR19,
VAR26,
VAR14,
VAR31,
VAR21,
VAR28,
VAR13,
VAR100,
VAR90,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.pp.blackbox.v | 1,412 | module MODULE1 (
VAR4 ,
VAR1,
VAR7,
VAR6 ,
VAR2 ,
VAR3,
VAR5
);
output VAR4 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR2 ;
input VAR3;
input VAR5;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,027 | module MODULE1(
VAR33,
VAR1,
VAR30,
VAR25,
VAR7,
VAR11,
VAR10,
VAR18,
VAR8,
VAR23
);
parameter VAR17 = 1;
parameter VAR26 = 8;
parameter VAR15 = 2;
parameter VAR9 = 2;
parameter VAR3 = 1;
localparam VAR28 = VAR17 * VAR26;
input VAR33;
input VAR1;
output VAR30;
input VAR25;
input [VAR28-1:0] VAR7;
input VAR11;
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.blackbox.v | 1,192 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold/sky130_fd_sc_lp__bushold.pp.symbol.v | 1,385 | module MODULE1 (
inout VAR2 ,
input VAR1,
input VAR4 ,
input VAR3 ,
input VAR6 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.functional.v | 1,870 | module MODULE1 (
VAR14 ,
VAR5,
VAR11,
VAR6 ,
VAR12
);
output VAR14 ;
output VAR5;
input VAR11;
input VAR6 ;
input VAR12 ;
wire VAR1 ;
wire VAR3;
VAR9 VAR10 (VAR3, VAR1, VAR6, VAR12 );
VAR4 VAR13 VAR8 (VAR1 , VAR3, VAR11 );
buf VAR2 (VAR14 , VAR1 );
not VAR7 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.behavioral.v | 3,306 | module MODULE1( VAR3, VAR6, VAR8, VAR4, VAR1, VAR9 );
input VAR9, VAR1, VAR6, VAR3, VAR4;
output VAR8;
VAR7 VAR5(.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR4(VAR4),.VAR1(VAR1),.VAR9(VAR9));
VAR7 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR4(VAR4),.VAR1(VAR1),.VAR9(VAR9)); | apache-2.0 |
marmolejo/zet | cores/zet/rtl/zet_opcode_deco.v | 28,563 | module MODULE1 (
input [7:0] VAR7,
input [7:0] VAR101,
input VAR213,
input [2:0] VAR73,
output reg [VAR49-1:0] VAR143,
output reg VAR104,
output reg VAR195,
output reg VAR87,
output VAR133,
output reg VAR137,
output reg [3:0] VAR22,
output reg [3:0] VAR201,
output [3:0] VAR171,
output [3:0] VAR36,
output [1:0] VAR4
);
... | gpl-3.0 |
Jside/nova1 | nova_cpu.v | 10,470 | module MODULE1(
VAR90, VAR7,
VAR73, VAR42, VAR13, VAR52, VAR59, VAR54,
VAR79, VAR23, VAR31, VAR28, VAR72, VAR63);
input VAR90;
input VAR7;
output reg VAR73;
input VAR42;
output reg [0:15] VAR13;
output reg VAR52;
input [0:15] VAR59;
output reg [0:15] VAR54;
output VAR79;
output VAR23;
output VAR31;
output [0:7] VAR28;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.blackbox.v | 1,295 | module MODULE1 (
VAR2 ,
VAR7,
VAR3,
VAR4
);
output VAR2 ;
output VAR7;
input VAR3;
input VAR4 ;
supply1 VAR6;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
jairov4/accel-oil | solution_spartan6/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_samples_generic_hw.v | 72,612 | module MODULE1 (
VAR308,
VAR11,
VAR239,
VAR260,
VAR116,
VAR290,
VAR91,
VAR69,
VAR159,
VAR262,
VAR55,
VAR241,
VAR106,
VAR71,
VAR89,
VAR5,
VAR154,
VAR189,
VAR285,
VAR200,
VAR181,
VAR192,
VAR222,
VAR305,
VAR185,
VAR107,
VAR33,
VAR130,
VAR187,
VAR32,
VAR276,
VAR201,
VAR60,
VAR135,
VAR77,
VAR22,
VAR31,
VAR231,
VAR20,
VAR110... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3_1.v | 2,191 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR10 ,
VAR3,
VAR7,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR3;
input VAR7;
input VAR1 ;
input VAR4 ;
VAR8 VAR9 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/Loop_loop_height_pro.v | 56,798 | module MODULE1 (
VAR280,
VAR54,
VAR143,
VAR246,
VAR142,
VAR232,
VAR194,
VAR154,
VAR263,
VAR5,
VAR197,
VAR183,
VAR100,
VAR69,
VAR65,
VAR148,
VAR110,
VAR44,
VAR29,
VAR117,
VAR123,
VAR97,
VAR139,
VAR175,
VAR3,
VAR196,
VAR82,
VAR186,
VAR178,
VAR127,
VAR38,
VAR215,
VAR176,
VAR4,
VAR282,
VAR172,
VAR105,
VAR272,
VAR95,
VAR25
... | mit |
asicguy/gplgpu | hdl/mc_graph/mc_datmsk.v | 5,071 | module MODULE1
(
parameter VAR2 = 4
)
(
input VAR7,
input VAR14,
input VAR17,
input [3:0] VAR1,
input [VAR2-1:0] VAR13,
input [VAR2-1:0] VAR3,
input [VAR2-1:0] VAR10,
input [VAR2-1:0] VAR8,
input [VAR2-1:0] VAR9,
input [3:0] VAR11,
input VAR12, input VAR6,
input VAR5,
output reg [VAR2-1:0] VAR16 );
reg [VAR2-1:0] VAR15... | gpl-3.0 |
hakehuang/pycpld | ips/ip/i2c_slave/i2c_slave_op.v | 16,569 | module MODULE1(
VAR17,
VAR5,
VAR60,
VAR40,
VAR29,
VAR62,
);
input VAR5;
input VAR17;
input VAR40;
input VAR29;
output VAR62;
reg VAR62;
output VAR60;
reg VAR49;
reg VAR36;
reg VAR13;
reg VAR39;
reg VAR18;
reg VAR34;
reg VAR47;
reg VAR19;
reg [7:0] VAR1;
reg [7:0] VAR59;
reg [7:0] VAR3;
reg [7:0] VAR25;
reg [6:0] VAR9;
... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/mig_7series_v1_1.v | 42,690 | module MODULE1 #
(
parameter VAR184 = 3,
parameter VAR235 = 1,
parameter VAR6 = 10,
parameter VAR103 = 1,
parameter VAR23 = 1,
parameter VAR105 = 1,
parameter VAR54 = 8,
parameter VAR41 = 6,
parameter VAR222 = 8,
parameter VAR61 = 8,
parameter VAR233 = 64,
parameter VAR178 = 8,
parameter VAR162 = 3,
parameter VAR246 = ... | lgpl-3.0 |
iDoka/GOST-28147-89 | rtl/counter_rollover.v | 2,045 | module MODULE1
input wire VAR8,
input wire VAR5,
input wire [VAR13-1:0] VAR9,
output wire [VAR13-1:0] VAR10
);
reg [(VAR13/VAR2)-1:0] VAR6 [VAR2-1:0];
wire [VAR2-1:0] VAR4; wire [VAR2-1:0] VAR11;
genvar VAR3;
generate
for (VAR3=0;VAR3<VAR2;VAR3=VAR3+1) begin: VAR1
assign VAR4[VAR3] = (VAR3==0) ? 1'b1 : (VAR4[VAR3-1] &&... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.functional.v | 1,558 | module MODULE1 (
VAR2 ,
VAR8,
VAR6,
VAR1
);
output VAR2 ;
input VAR8;
input VAR6;
input VAR1 ;
wire VAR7;
VAR5 VAR4 (VAR7, VAR8, VAR6, VAR1 );
buf VAR3 (VAR2 , VAR7);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.symbol.v | 1,277 | module MODULE1 (
input VAR5,
output VAR4
);
supply0 VAR1;
supply0 VAR3 ;
supply1 VAR2 ;
supply1 VAR6;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_4.behavioral.v | 3,306 | module MODULE1( VAR7, VAR8, VAR9, VAR4, VAR3, VAR2 );
input VAR3, VAR2, VAR8, VAR9, VAR4;
output VAR7;
VAR6 VAR5(.VAR7(VAR7),.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2));
VAR6 VAR1(.VAR7(VAR7),.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
alonso193/proyecto1 | Pruebas/DMA_SD/probador_dma.v | 2,499 | module MODULE1(output reg reset,
output reg clk, output reg VAR5, output reg VAR9, output reg VAR2, output reg VAR14, output reg VAR12, output reg VAR10, output reg VAR11, output reg VAR7, output reg [63:0] VAR6, output reg [15:0] VAR13, output reg [5:0] VAR8, output reg VAR4, output reg VAR1, output reg VAR15, output ... | gpl-3.0 |
8l/soc | backends/small1/hw/soc/logipi/top.v | 33,891 | module MODULE2 (input clk,
input reset,
input [31:0] VAR143,
input VAR51,
input VAR86,
output reg VAR174,
input [31:0] VAR235,
output [31:0] VAR79,
output reg VAR209);
wire [31:0] none;
VAR72 #(.VAR123(VAR105))
VAR38
(.clk(clk),
.VAR237({2'b0,VAR143[31:2]}),
.VAR251(VAR235),
.VAR223(VAR51),
.VAR180(VAR79),
.VAR40(none)... | mit |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/pint_int.v | 3,883 | module MODULE1(
input clk,
input reset,
output VAR21,
input VAR25,
input VAR2,
input [7:0] VAR3,
input VAR27,
output reg VAR35,
output reg VAR17,
output reg [7:0] VAR10,
output reg VAR37,
output VAR14,
output VAR31,
output VAR20,
output reg VAR26,
input VAR24,
input VAR23,
output [7:0] VAR6
);
parameter VAR9 = 100;
wir... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way/src/vivado_ip_dram/ip_top/mig_7series_v2_3_mem_intfc.v | 42,978 | module MODULE1 #
(
parameter VAR277 = 100,
parameter VAR51 = "135", parameter VAR149 = 64,
parameter VAR337 = "1T",
parameter VAR2 = "0", parameter VAR286 = 3, parameter VAR175 = 2, parameter VAR22 = "8", parameter VAR80 = "VAR119", parameter VAR124 = "VAR237", parameter VAR324 = 1, parameter VAR1 = 4'hc,
parameter VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a.functional.v | 1,453 | module MODULE1 (
VAR5 ,
VAR2,
VAR9,
VAR8,
VAR4,
VAR7
);
output VAR5 ;
input VAR2;
input VAR9;
input VAR8;
input VAR4;
input VAR7;
wire VAR6 ;
wire VAR11;
or VAR1 (VAR6 , VAR4, VAR8, VAR9, VAR2 );
and VAR3 (VAR11, VAR6, VAR7 );
buf VAR10 (VAR5 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.functional.pp.v | 1,870 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1,
VAR6,
VAR7,
VAR12 ,
VAR11
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR7;
input VAR12 ;
input VAR11 ;
wire VAR13 ;
wire VAR9;
VAR5 VAR10 (VAR13 , VAR4, VAR6, VAR7 );
VAR5 VAR8 (VAR9, VAR1, VAR6, VAR7 );
bufif0 VAR2 (VAR3 , VAR13, VAR9);
endmodule | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/megacells/fifo_2k_bb.v | 5,956 | module MODULE1 (
VAR7,
VAR9,
VAR3,
VAR6,
VAR4,
VAR8,
VAR10,
VAR2,
VAR5,
VAR11,
VAR1);
input [15:0] VAR7;
input VAR9;
input VAR3;
input VAR6;
input VAR4;
input VAR8;
output [15:0] VAR10;
output VAR2;
output [10:0] VAR5;
output VAR11;
output [10:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.v | 2,156 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR4 ,
VAR7,
VAR9 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR4 ;
input VAR7;
input VAR9 ;
input VAR5 ;
VAR1 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR6
);
output VAR2;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
input VAR9 ,
input VAR6 ,
input VAR7 ,
output VAR8 ,
input VAR3 ,
input VAR2,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.pp.symbol.v | 1,238 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR6 ,
input VAR5,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SoC_NIOS_jtag_debug_module_tck.v | 7,942 | module MODULE1 (
VAR11,
VAR37,
VAR19,
VAR14,
VAR30,
VAR6,
VAR40,
VAR27,
VAR1,
VAR26,
VAR23,
VAR18,
VAR29,
VAR39,
VAR25,
VAR10,
VAR7,
VAR33,
VAR3,
VAR28,
VAR31,
VAR21,
VAR4,
VAR12,
VAR34,
VAR36,
VAR17,
VAR2,
VAR5,
VAR9,
VAR15
)
;
output [ 1: 0] VAR17;
output VAR2;
output [ 37: 0] VAR5;
output VAR9;
output VAR15;
input [... | gpl-2.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/gfx_bench.v | 16,187 | module MODULE1();
parameter VAR29 = 16;
parameter VAR50 = 16;
parameter VAR15 = 10;
parameter VAR26 = 0; parameter VAR7 = 1 << VAR63; parameter VAR59 = 2 << VAR63; parameter VAR66 = 3 << VAR63; parameter VAR39 = 3 << VAR63; parameter VAR69 = 1 << VAR31; parameter VAR37 = 1 << VAR3; parameter VAR27 = 1 << VAR4; paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.v | 2,154 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR6,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR6;
input VAR8 ;
input VAR4 ;
VAR9 VAR5 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR2,
VAR7
);
output VAR2;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.pp.symbol.v | 1,417 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR8 ,
input VAR6 ,
input VAR7 ,
input VAR4 ,
input VAR9,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/crtc6845.v | 8,867 | module MODULE1(
VAR89,
VAR80,
VAR71,
VAR17,
VAR74,
VAR38,
VAR5,
VAR10,
VAR91,
VAR20,
VAR66,
VAR70,
VAR41
);
input VAR89;
input [7:0]VAR80;
input VAR71;
input VAR17;
input VAR74;
input VAR38;
input VAR5;
output [4:0]VAR10;
output [13:0]VAR91;
output VAR20;
output VAR66;
output VAR70;
output [15:0] VAR41;
wire [7:0]VAR15... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/fifo_240x128/fifo_240x128_bb.v | 6,096 | module MODULE1 (
VAR1,
VAR5,
VAR8,
VAR9,
VAR6,
VAR7,
VAR3,
VAR2,
VAR4,
VAR10);
input [239:0] VAR1;
input VAR5;
input VAR8;
input VAR9;
input VAR6;
output [239:0] VAR7;
output VAR3;
output VAR2;
output VAR4;
output [6:0] VAR10;
endmodule | gpl-3.0 |
lvd2/zxevo | fpga/current/top.v | 21,079 | module MODULE1(
input VAR45,
output VAR269,
input VAR152,
input VAR281,
input VAR146,
input VAR223,
input VAR202,
input VAR282,
input VAR273,
output VAR258,
output VAR20,
output VAR271,
output VAR189,
inout [7:0] VAR47,
input [15:0] VAR304,
output VAR274,
output VAR239,
output VAR249,
output VAR94,
output VAR279, outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.behavioral.v | 2,153 | module MODULE1 (
VAR16 ,
VAR8,
VAR20 ,
VAR6
);
output VAR16 ;
input VAR8;
input VAR20 ;
input VAR6 ;
supply1 VAR14;
supply0 VAR12;
supply1 VAR3 ;
supply0 VAR1 ;
wire VAR5 ;
reg VAR11 ;
wire VAR10 ;
wire VAR19 ;
wire VAR7;
wire VAR4 ;
wire VAR13 ;
wire VAR21 ;
VAR2 VAR9 (VAR4, VAR5, VAR10, VAR19 );
VAR15 VAR18 (VAR5 , V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.behavioral.v | 1,750 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR10 ;
input VAR6;
supply1 VAR8 ;
supply0 VAR4 ;
supply1 VAR11;
supply1 VAR12 ;
supply0 VAR5 ;
wire VAR7 ;
wire VAR13;
not VAR2 (VAR7 , VAR6 );
and VAR3 (VAR13, VAR6, VAR10 );
buf VAR1 (VAR9 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.pp.symbol.v | 1,258 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR1 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.pp.symbol.v | 1,410 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3,
input VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR5
);
endmodule | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/toplevel/mrfm/mrfm.v | 6,867 | module MODULE1
(output VAR67,
input VAR134,
input VAR14,
input VAR100,
inout VAR27,
input VAR122,
input VAR121,
output VAR47,
output VAR123,
input wire [11:0] VAR92,
input wire [11:0] VAR127,
input wire [11:0] VAR88,
input wire [11:0] VAR141,
output wire [13:0] VAR22,
output wire [13:0] VAR53,
output wire VAR101,
outpu... | gpl-3.0 |
google/CFU-Playground | proj/dse_template/cfu.v | 2,275 | module MODULE1 (
input VAR9,
output VAR4,
input [9:0] VAR6,
input [31:0] VAR11,
input [31:0] VAR12,
output reg VAR2,
input VAR8,
output reg [31:0] VAR14,
input reset,
input clk
);
localparam VAR10 = (9'd128);
wire signed [15:0] VAR3, VAR7, VAR5, VAR1;
assign VAR3 = ((VAR11[7 : 0]) + VAR10)
* (VAR12[7 : 0]);
assign VAR7... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/complex_mult.v | 53,425 | module MODULE2
(
VAR192,
VAR35,
VAR138,
VAR86,
VAR15,
VAR130,
VAR349,
VAR251,
VAR343) ;
input VAR192;
input VAR35;
input [63:0] VAR138;
input [19:0] VAR86;
input VAR15;
input VAR130;
input VAR349;
input VAR251;
output [41:0] VAR343;
tri0 VAR192;
tri1 VAR35;
tri0 [63:0] VAR138;
tri0 [19:0] VAR86;
tri1 VAR15;
tri1 VAR130... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_alu_out.v | 1,885 | module MODULE1 (
address,
clk,
VAR5,
VAR6,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR5;
input VAR6;
wire VAR4;
wire [ 31: 0] VAR3;
wire [ 31: 0] VAR2;
reg [ 31: 0] VAR1;
assign VAR4 = 1;
assign VAR2 = {32 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR6)
begin
if (... | gpl-3.0 |
firemark/katp91 | src/byte_to_rgb.v | 10,151 | module MODULE1(VAR2, VAR4, VAR3, VAR1);
input [7:0] VAR2;
output reg[2:0] VAR4, VAR3, VAR1;
always @(VAR2) begin
case(VAR2)
8'b00000000: {VAR4, VAR3, VAR1} = 9'b101000000;
8'b00000001: {VAR4, VAR3, VAR1} = 9'b100011000;
8'b00000010: {VAR4, VAR3, VAR1} = 9'b110000000;
8'b00000011: {VAR4, VAR3, VAR1} = 9'b010110000;
8'b0... | mit |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/fifo_ctr.v | 4,370 | module MODULE1 (
input wire clk,
input wire VAR2,
input wire VAR21,
input wire VAR15,
output reg VAR6,
output reg VAR22,
output reg VAR13,
output reg VAR8,
output reg VAR26,
output reg VAR12,
output reg VAR1,
output reg VAR19,
output reg [4:0] addr
);
parameter VAR14 = 32;
parameter delay = 1.5;
parameter VAR7 = 2'b00;... | mit |
martinmiranda14/Digitales | Lab_6/new/mostrar_numeros_pantalla.v | 4,374 | module MODULE1(
input VAR17,
input reset,
input VAR8,
input [2:0] VAR36,
input [1:0] VAR16,
input VAR26,
input VAR39,
input VAR15,
input [4:0] VAR45,
output [63:0] VAR29,
output [7:0] VAR42
);
localparam VAR11=1'b0;
localparam VAR43=1'b1;
wire [4:0] VAR6;
wire VAR3;
wire [7:0] VAR37;
wire [4:0] VAR19;
wire [2:0] VAR24;... | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/hw3_t.v | 2,610 | module MODULE1 ;
reg [57:0] VAR8 [VAR17-1:0];
reg [291:0] VAR18 [VAR17-1:0];
reg [25:0] VAR9;
reg [15:0] VAR13;
reg [15:0] VAR23;
reg clk, VAR32;
reg VAR35, VAR36, VAR31, VAR34;
wire [15:0] VAR20;
wire [15:0] VAR37;
wire [15:0] VAR28;
wire [15:0] VAR5;
wire [15:0] VAR2;
wire [15:0] VAR11;
wire [15:0] VAR25;
wire [15:0]... | mit |
chadharrington/all_spark_cube | fpga/usb_sequencer.v | 6,457 | module MODULE1
(
input clk,
input VAR12,
input VAR9,
input VAR10,
input VAR5,
input [15:0] VAR7,
output reg [7:0] VAR21,
output VAR3,
output VAR2,
output VAR6,
output VAR20,
output VAR17,
output [4:0] VAR1
);
reg [4:0] state, VAR14, VAR22;
assign VAR1 = state;
assign VAR3 = VAR22[4];
assign VAR2 = VAR22[3];
assign VAR6... | mit |
lee-dohm/atom-linguist | samples/Verilog/t_div_pipelined.v | 1,914 | module MODULE1();
reg clk, VAR1, VAR7;
reg [7:0] VAR10, VAR4;
wire VAR2, VAR8;
wire [7:0] VAR3, VAR6;
parameter
VAR5 = 8;
VAR9
.VAR5(VAR5)
)
VAR9
(
.clk(clk),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2)
); | mit |
dawsonjon/fpu | adder/adder.v | 7,049 | module MODULE1(
VAR31,
VAR33,
VAR22,
VAR7,
VAR27,
clk,
rst,
VAR19,
VAR25,
VAR28,
VAR40);
input clk;
input rst;
input [31:0] VAR31;
input VAR22;
output VAR28;
input [31:0] VAR33;
input VAR7;
output VAR40;
output [31:0] VAR19;
output VAR25;
input VAR27;
reg VAR21;
reg [31:0] VAR29;
reg VAR13;
reg VAR32;
reg [3:0] state;
... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Booth_Multipliers-master/Src/Booth_Multiplier_4x.v | 12,357 | module MODULE1 #(
parameter VAR16 = 16 )(
input VAR12, input VAR2,
input VAR6, input [(VAR16 - 1):0] VAR15, input [(VAR16 - 1):0] VAR14, output reg VAR1, output reg [((2*VAR16) - 1):0] VAR4 );
localparam VAR3 = ((VAR16 + 1)/4);
reg [4:0] VAR9; reg [4:0] VAR8; reg VAR10;
reg [(VAR16 + 3):0] VAR13; reg [(VAR16 + 3):0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.v | 2,198 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR9 ,
VAR4,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR9 ;
input VAR4;
input VAR6;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR5,
VAR9
... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_dpram_32x32.v | 13,863 | module MODULE1(
VAR82, VAR30, VAR108, VAR69, VAR130, VAR37,
VAR126, VAR86, VAR90, VAR16, VAR10, VAR50
);
parameter VAR61 = 5;
parameter VAR121 = 32;
input VAR82; input VAR30; input VAR108; input VAR69; input [VAR61-1:0] VAR130; output [VAR121-1:0] VAR37; input VAR126; input VAR86; input VAR90; input VAR16; input [VAR61... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_sideband.v | 56,523 | module MODULE1
VAR156 = 3,
VAR55 = 2, VAR17 = 1,
VAR83 = 4,
VAR131 = 1,
VAR150 = 1, VAR95 = 3,
VAR67 = 4,
VAR160 = 2,
VAR54 = 0,
VAR143 = 10,
VAR22 = 13,
VAR124 = 10,
VAR42 = 10,
VAR138 = 10,
VAR92 = 6,
VAR120 = 2, VAR36 = 16, VAR31 = 6
)
(
VAR18,
VAR87,
VAR107,
VAR141,
VAR155,
VAR29,
VAR56,
VAR97,
VAR91,
VAR45,
VAR88,... | gpl-3.0 |
lab1-ufba/Genius | vga.v | 25,615 | module MODULE1(
input clk, input rst, input VAR18, input VAR22, input VAR14, input VAR16, input [6:0] VAR25, input [6:0] VAR36, input [6:0] VAR39, input [6:0] VAR40, input [20:0] VAR15, input [5:0] VAR35, output reg [6:0] addr, output reg VAR13, output reg VAR38, output VAR32, output VAR24, output reg [7:0] VAR8, outpu... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_fake_master.v | 4,760 | module MODULE1(
input clk,
input reset,
output [8:0] VAR10,
output VAR2,
input [31:0] VAR12,
output VAR7,
output reg [31:0] VAR6,
input VAR4,
input VAR8
);
reg [1:0] state;
reg [1:0] VAR11;
reg VAR5, VAR13;
reg VAR3;
localparam VAR9 = 2'b0 ;
localparam VAR1 = 2'b1;
always @ (posedge clk or posedge reset)
begin
if (rese... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.blackbox.v | 1,280 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR7;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_axi_basic_rx.v | 8,309 | module MODULE1 #(
parameter VAR33 = 128, parameter VAR32 = "VAR22", parameter VAR5 = "VAR14", parameter VAR16 = "VAR14", parameter VAR34 = 1,
parameter VAR31 = (VAR33 == 128) ? 2 : 1, parameter VAR20 = VAR33 / 8 ) (
output [VAR33-1:0] VAR6, output VAR21, input VAR9, output [VAR20-1:0] VAR17, output VAR3, output [21:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai_1.v | 2,335 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR11,
VAR2,
VAR9 ,
VAR1
);
output VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR11;
input VAR2;
input VAR9 ;
input VAR1 ;
VAR4 VAR5 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/agnus_spritedma.v | 13,599 | module MODULE1 (
input clk, input VAR2,
input reset,
input VAR23,
input VAR18, output reg VAR5, input VAR21, input [8:0] VAR28, input [10:0] VAR33, input VAR17, input VAR3, input [8:1] VAR34, output reg [8:1] VAR31, input [15:0] VAR8, output [20:1] VAR9 );
parameter VAR19 = 9'h120; parameter VAR32 = 9'h140; parameter V... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_trace.v | 9,013 | module MODULE1(
VAR11,
VAR55,
VAR44,
VAR40,
VAR26,
VAR13,
VAR15,
VAR52,
VAR20,
VAR2,
VAR33,
VAR9,
VAR37,
VAR49,
VAR35);
input VAR11;
input VAR55;
input VAR44;
input VAR40;
input [3:0] VAR26;
input [VAR23] VAR13;
input [VAR23] VAR15;
input [VAR16] VAR52;
input [VAR30] VAR20;
input VAR2;
input VAR33;
input VAR9;
input VA... | lgpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/axis_inf.v | 6,425 | module MODULE1 (
clk,
rst,
valid,
VAR25,
VAR20,
VAR19,
VAR13,
VAR2,
VAR26);
parameter VAR22 = 16;
localparam VAR14 = VAR22 - 1;
input clk;
input rst;
input valid;
input VAR25;
input [VAR14:0] VAR20;
output VAR19;
output VAR13;
output [VAR14:0] VAR2;
input VAR26;
reg [ 2:0] VAR21 = 'd0;
reg VAR18 = 'd0;
reg [VAR14:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill_1.v | 1,840 | module MODULE1 (
VAR4,
VAR1,
VAR5 ,
VAR2
);
input VAR4;
input VAR1;
input VAR5 ;
input VAR2 ;
VAR3 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
VAR3 VAR6 ();
endmodule | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_wb_if.v | 7,237 | module MODULE1(clk, rst,
VAR30, VAR31, VAR18, VAR46, VAR42, VAR3,
VAR35, VAR47, VAR43, VAR16,
VAR28, VAR48, VAR33, VAR21, VAR9, VAR17,
VAR38, VAR4, VAR23, VAR20,
VAR34, VAR37, VAR26, VAR25, VAR39, VAR40, VAR2,
VAR11, VAR24, VAR22, VAR5, VAR7,
VAR8, VAR41, VAR6, VAR36, VAR27,
VAR45, VAR29, VAR19
);
parameter VAR10 = 0;
... | apache-2.0 |
google/bbcpu | uart-tx.v | 4,196 | module MODULE1(
input rst,
input clk,
input VAR27,
input [7 : 0] VAR21,
output VAR11, output VAR28);
localparam VAR10 = 0;
localparam VAR4 = 1;
localparam VAR15 = 2;
localparam VAR16 = 3;
localparam VAR14 = 4;
localparam VAR13 = 5;
localparam VAR22 = 6;
localparam VAR18 = 7;
localparam VAR2 = 8;
localparam VAR3 = 9;
lo... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.functional.v | 2,043 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR17 ,
VAR18 ,
VAR3 ,
VAR6
);
output VAR10 ;
output VAR9 ;
input VAR17 ;
input VAR18 ;
input VAR3 ;
input VAR6;
wire VAR14;
wire VAR7 ;
wire VAR4 ;
wire VAR8;
not VAR13 (VAR14 , VAR6 );
not VAR1 (VAR7 , VAR3 );
not VAR16 (VAR4 , VAR18 );
VAR11 VAR5 VAR2 (VAR8 , VAR7, VAR14, VAR4, VAR17)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.blackbox.v | 1,427 | module MODULE1 (
VAR8 ,
VAR1,
VAR2,
VAR6,
VAR4,
VAR9,
VAR5
);
output VAR8 ;
input VAR1;
input VAR2;
input VAR6;
input VAR4;
input VAR9;
input VAR5;
supply1 VAR3;
supply0 VAR11;
supply1 VAR10 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/xilinx/ff_map.v | 4,941 | module \VAR36 (input VAR35, VAR22, VAR25, VAR43, output VAR42);
parameter VAR27 = 1'VAR10;
VAR16 #(.VAR2(VAR27)) VAR8 (.VAR35(VAR35), .VAR42(VAR42), .VAR22(VAR22), .VAR7(VAR25), .VAR26(VAR43));
wire VAR37 = 1;
endmodule
module \VAR3 (input VAR35, VAR22, VAR25, VAR43, output VAR42);
parameter VAR27 = 1'VAR10;
VAR6 #(.VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2_1.v | 2,187 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR4,
VAR9,
VAR10 ,
VAR6
);
output VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR4;
input VAR9;
input VAR10 ;
input VAR6 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.functional.v | 1,617 | module MODULE1 (
VAR3 ,
VAR1,
VAR12,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR1;
input VAR12;
input VAR8 ;
input VAR6 ;
wire VAR2 ;
wire VAR9 ;
wire VAR11;
and VAR5 (VAR2 , VAR8, VAR6 );
nor VAR4 (VAR9 , VAR1, VAR12 );
or VAR7 (VAR11, VAR9, VAR2);
buf VAR10 (VAR3 , VAR11 );
endmodule | apache-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/TF_EECS301_Lab4_TopLevel.v | 2,629 | module MODULE1();
localparam VAR2 = 50000000; localparam VAR3 = ((1.0 / VAR2) * 1000000000.0) / 2.0;
reg VAR1;
begin
begin | mit |
everskar2013/PentiumX | Hardware/Code/seven_seg_dev.v | 3,649 | module MODULE1 (
clk,
VAR2,
VAR7,
VAR9,
VAR1,
VAR10,
VAR3
);
input wire clk, VAR2;
input wire [ 1: 0] VAR9;
input wire [ 1: 0] VAR1;
input wire [31: 0] VAR7;
output reg [ 3: 0] VAR10;
output wire [ 7: 0] VAR3;
reg [ 3: 0] VAR5 = 4'h0;
reg [ 7: 0] VAR4 = 8'h0,
VAR8 = 8'h0;
wire [15: 0] VAR6;
assign VAR3 = VAR1[0] ? VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.pp.blackbox.v | 1,289 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR4,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR4;
input VAR2;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v | 9,065 | module MODULE1 (
VAR42, VAR15, VAR78, VAR31, VAR16, VAR46, VAR56, VAR8,
VAR30, VAR5,
VAR63, VAR18, VAR32, VAR24, VAR85, VAR12, VAR71, VAR4, VAR22, VAR84, VAR48,
VAR72, VAR20, VAR73, VAR75, VAR54, VAR55
);
output [1:0] VAR42;
output [1:0] VAR15, VAR78, VAR31;
output [2:0] VAR16;
output [4:0] VAR46;
input VAR63;
input [1... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_eclbyplog.v | 6,398 | module MODULE1 (
VAR49, VAR31, VAR19, VAR14,
VAR23, VAR32, VAR28,
VAR15, VAR2, VAR18,
VAR7,
VAR50, VAR55, VAR11, VAR4, VAR25, VAR6, VAR41,
VAR24, VAR13, VAR16, VAR38,
VAR1, VAR40, VAR54, VAR45,
VAR39, VAR42, VAR51, VAR34,
VAR21, VAR8, VAR17, VAR53,
VAR5
) ;
input VAR50;
input VAR55;
input [4:0] VAR11; input [4:0] VAR4;... | gpl-2.0 |
ShepardSiegel/ocpi | rtl/mkTLPClientNode.v | 5,180 | module MODULE1(VAR1,
VAR50,
VAR55,
VAR27,
VAR16,
VAR30,
VAR43,
VAR22,
VAR28,
VAR52,
VAR31,
VAR53,
VAR57,
VAR13,
VAR46);
input [13 : 0] VAR1;
input VAR50;
input VAR55;
input [152 : 0] VAR27;
input VAR16;
output VAR30;
input VAR43;
output [152 : 0] VAR22;
output VAR28;
input [152 : 0] VAR52;
input VAR31;
output VAR53;
in... | lgpl-3.0 |
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