repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.symbol.v | 1,298 | module MODULE1 (
input VAR8,
output VAR7
);
supply1 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
supply1 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/rx_queue.v | 17,061 | module MODULE1
parameter VAR50 = VAR96/8,
parameter VAR18 = 1,
parameter VAR98 = 'hff,
parameter VAR69 = 0,
parameter VAR13 = 32,
parameter VAR7 = VAR13/8
)
(output reg [VAR96-1:0] VAR42,
output reg [VAR50-1:0] VAR71,
output reg VAR70,
input VAR64,
input VAR4,
input [VAR13 - 1:0] VAR48,
input [VAR7 - 1:0] VAR52,
input ... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.behavioral.pp.v | 2,194 | module MODULE1 (
VAR9,
VAR8 ,
VAR17 ,
VAR19 ,
VAR1,
VAR2,
VAR12 ,
VAR7
);
output VAR9;
output VAR8 ;
input VAR17 ;
input VAR19 ;
input VAR1;
input VAR2;
input VAR12 ;
input VAR7 ;
wire VAR6 ;
wire VAR4;
wire VAR18 ;
wire VAR15 ;
and VAR3 (VAR6 , VAR17, VAR19 );
VAR13 VAR5 (VAR4, VAR6, VAR1, VAR2);
buf VAR11 (VAR9 , VAR... | apache-2.0 |
rqou/openfpga | hdl/xc2c-model/XC2CAndArray.v | 3,617 | module MODULE1(VAR7, VAR6, VAR1);
input wire[39:0] VAR7;
input wire[80*56 - 1 : 0] VAR6;
output reg[55:0] VAR1;
integer VAR3;
integer VAR2;
integer VAR4;
reg[79:0] VAR5[55:0];
always @ begin
for(VAR3=0; VAR3<56; VAR3 = VAR3+1) begin
VAR1[VAR3] = 1;
for(VAR2=0; VAR2<40; VAR2=VAR2+1) begin
if(!VAR5[VAR3][VAR2*2])
VAR1[VA... | lgpl-2.1 |
LSaldyt/qnp | output/vs/var12_multi.v | 1,083 | module MODULE1 (VAR15, VAR6, VAR2, VAR1, VAR3, VAR9, VAR17, VAR11, VAR14, VAR16, VAR18, VAR10, valid);
input VAR15, VAR6, VAR2, VAR1, VAR3, VAR9, VAR17, VAR11, VAR14, VAR16, VAR18, VAR10;
output valid;
wire [7:0] VAR7 = 8'd107;
wire [7:0] VAR8 = 8'd60;
wire [7:0] VAR13 = 8'd60;
wire [7:0] VAR12 =
VAR15 * 8'd4
+ VAR6 * ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a_1.v | 2,422 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR12 ,
VAR11 ,
VAR4 ,
VAR9 ,
VAR1,
VAR5,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR12 ;
input VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR2 ;
VAR10 VAR8 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(... | apache-2.0 |
jacgoudsmit/P8X32A_Emulation | Altera/hub_mem.v | 5,774 | module MODULE1
(
input clk,
input enable,
input VAR14,
input VAR3,
input [13:0] VAR9,
input [7:0] VAR13,
output [7:0] VAR1
);
parameter VAR4;
reg [7:0] VAR5[VAR4 - 1:0];
always @(posedge clk)
begin
if (enable && VAR14 && VAR3)
begin
VAR5[VAR9] <= VAR13;
end
VAR1 <= VAR5[VAR9];
end
endmodule
module MODULE2
(
input clk,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b_1.v | 2,173 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR8 ,
VAR1 ,
VAR7,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR7;
input VAR4;
VAR3 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR2,
VAR9 ,
VAR8 ,
VAR1
... | apache-2.0 |
ZiCog/xoro | rtl/busInterface.v | 1,950 | module MODULE1 (
input wire [31:0] VAR4,
input wire [31:0] VAR10,
input wire [31:0] VAR15,
input wire [31:0] VAR8,
input wire [31:0] VAR2,
input wire [31:0] VAR9,
input wire [31:0] VAR5,
input wire VAR7,
input wire VAR16,
input wire VAR1,
input wire VAR13,
input wire VAR6,
input wire VAR12,
output wire VAR11,
output wi... | mit |
rfotino/consolite-hardware | src/seg_display.v | 2,029 | module MODULE1
(
input wire clk,
input wire [11:0] VAR4,
output reg [7:0] VAR6,
output reg [2:0] VAR3
);
reg [17:0] counter = 0;
wire VAR7 = counter[17];
always @ (posedge clk) begin
counter <= counter + 1;
end
reg [1:0] VAR2 = 0;
always @ (posedge VAR7) begin
if (VAR2 == 2) begin
VAR2 <= 0;
end else begin
VAR2 <= VAR2... | mit |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/LX150_makomk_dualcore/hdl/fpgaminer_top.v | 4,648 | module MODULE1 (
input VAR62
);
localparam VAR45 = 100;
localparam VAR32 = 50;
localparam VAR54 = 50;
localparam VAR7 = 100;
wire VAR20;
VAR21 VAR35 ( .VAR42 (VAR62), .VAR44 (VAR20));
reg [255:0] VAR12 = 0;
reg [95:0] VAR50 = 0;
reg [30:0] VAR24 = 31'd254, VAR57 = 31'd0;
wire VAR53;
wire VAR6, VAR39, VAR60;
VAR58 # (
.... | gpl-3.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/pcores/xillybus_v1_00_a/hdl/verilog/xillybus.v | 6,979 | module MODULE1 #(
parameter VAR43 = 32,
parameter VAR74 = 32,
parameter VAR11 = 32,
parameter VAR41 = 32,
parameter VAR3 = 32'h000001ff,
parameter VAR84 = 1,
parameter VAR57 = 8,
parameter VAR52 = 32'h79c00000,
parameter VAR103 = 32'h79c0ffff,
parameter VAR76 = 32,
parameter VAR82 = 32,
parameter VAR93 = 256,
parameter... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.functional.v | 1,223 | module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
wire VAR3;
buf VAR2 (VAR3, VAR5 );
buf VAR4 (VAR1 , VAR3 );
endmodule | apache-2.0 |
olofk/oh | elink/hdl/ecfg_if.v | 5,329 | module MODULE1 (
VAR36, VAR19, VAR3, VAR25, VAR52, VAR17,
VAR34, VAR42,
clk, VAR37, VAR5, VAR29, VAR12, VAR33, VAR55,
VAR48
);
parameter VAR38 = 0; parameter VAR13 = 104;
parameter VAR14 = 32;
parameter VAR51 = 32;
parameter VAR31 = 12'h810;
input clk;
input VAR37;
input [VAR13-1:0] VAR5;
output VAR36;
output VAR19;
ou... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/block_DSP.v | 7,888 | module MODULE1
parameter VAR80 = 24, parameter VAR7 = VAR80-1,
parameter VAR70 = 120'h0,
parameter VAR6 = 120'h0,
parameter VAR84 = 120'h0,
parameter VAR63 = 120'h0,
parameter VAR9 = VAR20*2, parameter VAR81 = VAR9-1,
parameter VAR3 = VAR9*4, parameter VAR17 = VAR3-1,
parameter VAR44 = 12, parameter VAR16 = 4, paramete... | lgpl-3.0 |
jairov4/accel-oil | solution_spartan3/syn/verilog/nfa_accept_samples_generic_hw.v | 70,370 | module MODULE1 (
VAR200,
VAR208,
VAR64,
VAR116,
VAR12,
VAR88,
VAR107,
VAR273,
VAR175,
VAR255,
VAR216,
VAR137,
VAR163,
VAR197,
VAR23,
VAR161,
VAR133,
VAR241,
VAR272,
VAR261,
VAR222,
VAR283,
VAR144,
VAR24,
VAR165,
VAR252,
VAR276,
VAR266,
VAR43,
VAR304,
VAR247,
VAR140,
VAR152,
VAR9,
VAR299,
VAR270,
VAR85,
VAR103,
VAR256,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.functional.v | 1,615 | module MODULE1 (
VAR12 ,
VAR13,
VAR10,
VAR9,
VAR4,
VAR11
);
output VAR12 ;
input VAR13;
input VAR10;
input VAR9;
input VAR4;
input VAR11;
wire VAR6 ;
wire VAR8 ;
wire VAR3;
nand VAR2 (VAR6 , VAR10, VAR13, VAR9 );
nand VAR7 (VAR8 , VAR11, VAR4 );
and VAR1 (VAR3, VAR6, VAR8);
buf VAR5 (VAR12 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.blackbox.v | 1,402 | module MODULE1 (
VAR7 ,
VAR4,
VAR9,
VAR3,
VAR2,
VAR10
);
output VAR7 ;
input VAR4;
input VAR9;
input VAR3;
input VAR2;
input VAR10;
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.functional.v | 1,838 | module MODULE1( VAR19, VAR20, VAR22, VAR24, VAR21, VAR10, VAR1 );
input VAR1, VAR10, VAR21, VAR22, VAR20, VAR19;
output VAR24;
wire VAR3;
not VAR8( VAR3, VAR1 );
wire VAR5;
not VAR9( VAR5, VAR10 );
wire VAR16;
not VAR4( VAR16, VAR21 );
wire VAR6;
and VAR7( VAR6, VAR3, VAR5, VAR16 );
wire VAR15;
not VAR11( VAR15, VAR22 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/filltie/gf180mcu_fd_sc_mcu7t5v0__filltie.behavioral.pp.v | 1,074 | module MODULE1( VAR3, VAR2 );
inout VAR3, VAR2;
VAR4 VAR5(.VAR3(VAR3),.VAR2(VAR2));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o_m.v | 2,336 | module MODULE2 (
VAR11 ,
VAR9 ,
VAR7 ,
VAR10 ,
VAR2 ,
VAR4,
VAR5,
VAR6 ,
VAR1
);
output VAR11 ;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR2 ;
input VAR4;
input VAR5;
input VAR6 ;
input VAR1 ;
VAR3 VAR8 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.symbol.v | 1,364 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR7 ,
input VAR8
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ipshared/7e3a/hdl/axi_infrastructure_v1_1_vl_rfs.v | 29,851 | module MODULE1 #
(
parameter integer VAR20 = 0,
parameter integer VAR107 = 4,
parameter integer VAR142 = 32,
parameter integer VAR1 = 32,
parameter integer VAR53 = 0,
parameter integer VAR116 = 0,
parameter integer VAR33 = 1,
parameter integer VAR3 = 1,
parameter integer VAR74 = 1,
parameter integer VAR99 = 1,
paramete... | mit |
ZiCog/P8X32A_Emulation | P8X32A_DE0_Nano/hub_mem.v | 3,072 | module MODULE1
(
input VAR6,
input VAR17,
input VAR14,
input [3:0] VAR15,
input [13:0] VAR7,
input [31:0] VAR12,
output [31:0] VAR4
);
reg [7:0] VAR13 [8191:0];
reg [7:0] VAR18 [8191:0];
reg [7:0] VAR9 [8191:0];
reg [7:0] VAR16 [8191:0];
reg [7:0] VAR8;
reg [7:0] VAR19;
reg [7:0] VAR11;
reg [7:0] VAR2;
always @(posedge... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v1_00_a/hdl/verilog/axi_ad9122_core.v | 11,025 | module MODULE1 (
VAR63,
VAR87,
VAR29,
VAR24,
VAR56,
VAR78,
VAR44,
VAR98,
VAR90,
VAR12,
VAR25,
VAR68,
VAR88,
VAR104,
VAR57,
VAR21,
VAR60,
VAR83,
VAR18,
VAR75,
VAR46,
VAR100,
VAR69,
VAR8,
VAR30,
VAR13,
VAR50,
VAR67,
VAR7,
VAR53,
VAR49,
VAR62,
VAR38,
VAR72,
VAR79,
VAR33,
VAR84,
VAR93,
VAR73,
VAR76,
VAR31,
VAR48);
paramete... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.behavioral.v | 1,381 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR7 ;
and VAR4 (VAR3 , VAR6, VAR2 );
endmodule | apache-2.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/comm_pll_altpll1.v | 4,170 | module MODULE1
(
clk,
VAR1) ;
output [4:0] clk;
input [1:0] VAR1;
tri0 [1:0] VAR1;
wire [4:0] VAR25;
wire VAR21;
VAR7 VAR40
(
.VAR33(),
.clk(VAR25),
.VAR29(),
.VAR2(VAR21),
.VAR41(VAR21),
.VAR1(VAR1),
.VAR23(),
.VAR37(),
.VAR35(),
.VAR34(),
.VAR22(),
.VAR13()
,
.VAR39(1'b0),
.VAR24(1'b0),
.VAR6(1'b0),
.VAR16(1'b1),
.VA... | gpl-3.0 |
curtiszimmerman/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_aes/rtl/verilog/aes_sbox.v | 8,456 | module MODULE1 (
input [7:0] VAR100,
input VAR153,
output reg [7:0] VAR137
);
always @*
begin : VAR56
reg VAR160, VAR30, VAR12, VAR61, VAR176, VAR167, VAR145, VAR106;
reg VAR132, VAR144, VAR80, VAR172, VAR149, VAR54, VAR171, VAR29;
reg VAR69;
reg VAR107, VAR130, VAR157, VAR155, VAR154, VAR91, VAR156, VAR11, VAR73, VAR8... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_drp.v | 38,897 | module MODULE1 #
(
parameter VAR139 = "VAR56", parameter VAR121 = "3.0", parameter VAR175 = "VAR75", parameter VAR113 = "VAR84", parameter VAR65 = "VAR32", parameter VAR42 = "VAR75", parameter VAR20 = "VAR32", parameter VAR164 = 0, parameter VAR59 = 0, parameter VAR174 = 2'd1, parameter VAR149 = 5'd21
)
(
input VAR172,... | gpl-3.0 |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_samples_generic_hw_top.v | 42,164 | module MODULE1 (
VAR6,
VAR342,
VAR12,
VAR355,
VAR101,
VAR75,
VAR204,
VAR136,
VAR120,
VAR295,
VAR336,
VAR124,
VAR354,
VAR273,
VAR343,
VAR313,
VAR428,
VAR396,
VAR433,
VAR178,
VAR107,
VAR380,
VAR225,
VAR135,
VAR409,
VAR274,
VAR109,
VAR460,
VAR290,
VAR305,
VAR123,
VAR450,
VAR239,
VAR384,
VAR278,
VAR71,
VAR39,
VAR1,
VAR67,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a_4.v | 2,428 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR2,
VAR3,
VAR9 ,
VAR4
);
output VAR7 ;
input VAR12 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR3;
input VAR9 ;
input VAR4 ;
VAR11 VAR10 (
.VAR7(VAR7),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.functional.v | 1,218 | module MODULE1( VAR3, VAR6, VAR9, VAR4 );
input VAR4, VAR9, VAR6;
output VAR3;
wire VAR10;
not VAR2( VAR10, VAR4 );
wire VAR5;
not VAR11( VAR5, VAR9 );
wire VAR8;
not VAR7( VAR8, VAR6 );
or VAR1( VAR3, VAR10, VAR5, VAR8 );
endmodule | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/bless/arbitor.v | 11,125 | module MODULE1 (
input VAR35 VAR9,
input VAR35 VAR55,
input VAR35 VAR10,
input VAR35 VAR27,
input VAR35 VAR1,
input VAR39 VAR61,
input VAR39 VAR3,
input VAR39 VAR32,
input VAR39 VAR25,
input VAR39 VAR46,
input clk,
input rst,
output reg VAR39 VAR45,
output reg VAR39 VAR6,
output reg VAR39 VAR47,
output reg VAR39 VAR22,... | mit |
olajep/oh | src/xilibs/dv/CLKDIV.v | 1,877 | module MODULE1(
VAR1,
VAR2, VAR8, reset
);
input VAR2; input [3:0] VAR8; input reset; output VAR1;
reg VAR5;
reg [7:0] counter;
reg [7:0] VAR4;
reg [3:0] VAR6;
wire VAR3;
wire VAR7;
wire VAR9;
always @ (VAR8[3:0])
casez (VAR8[3:0])
4'b0001 : VAR4[7:0] = 8'b00000010; 4'b0010 : VAR4[7:0] = 8'b00000100; 4'b0011 : VAR4[7:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.functional.v | 2,043 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR6 ,
VAR18 ,
VAR15 ,
VAR11
);
output VAR14 ;
output VAR5 ;
input VAR6 ;
input VAR18 ;
input VAR15 ;
input VAR11;
wire VAR13;
wire VAR16 ;
wire VAR12 ;
wire VAR8;
not VAR9 (VAR13 , VAR11 );
not VAR3 (VAR16 , VAR15 );
not VAR7 (VAR12 , VAR18 );
VAR1 VAR4 VAR2 (VAR8 , VAR16, VAR13, VAR12,... | apache-2.0 |
krucios/Echo_module | src/sonar_vip.v | 1,784 | module MODULE1 #(int VAR9 = 50000000) (
input wire clk,
input wire VAR5,
output reg VAR1 = 0,
input wire VAR7
);
parameter VAR11 = 1000000000 / VAR9; parameter VAR6 = 343210; parameter VAR4 = VAR6 * VAR11 / 1000;
reg[31:0] counter = 0;
reg[1:0] state = 0; parameter VAR2 = 2'b00;
parameter VAR3 = 2'b01;
parameter VAR10 ... | gpl-3.0 |
P3Stor/P3Stor | DDR3/ip_top/clk_ibuf.v | 4,308 | module MODULE1 #
(
parameter VAR14 = "VAR4" )
(
input VAR7, input VAR6,
input VAR15,
output VAR2
);
wire VAR19;
generate
if (VAR14 == "VAR4") begin: VAR5
VAR1 #
(
.VAR16 ("VAR10"),
.VAR12 ("VAR9")
)
VAR3
(
.VAR18 (VAR7),
.VAR11 (VAR6),
.VAR13 (VAR19)
);
end else if (VAR14 == "VAR17") begin: VAR8
assign VAR19 = VAR15;
e... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_axi_bridge_0/synth/ghrd_10as066n2_axi_bridge_0.v | 18,183 | module MODULE1 #(
parameter VAR10 = 1,
parameter VAR56 = 1,
parameter VAR127 = 1,
parameter VAR32 = 1,
parameter VAR106 = 1,
parameter VAR58 = 1,
parameter VAR14 = 1,
parameter VAR129 = 1,
parameter VAR77 = 1,
parameter VAR64 = 1,
parameter VAR68 = 1,
parameter VAR130 = 1,
parameter VAR49 = 1,
parameter VAR57 = 1,
para... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9671/axi_ad9671.v | 11,775 | module MODULE1 (
VAR131,
VAR45,
VAR106,
VAR6,
VAR125,
VAR72,
VAR34,
VAR24,
VAR5,
VAR140,
VAR41,
VAR137,
VAR7,
VAR129,
VAR84,
VAR21,
VAR76,
VAR29,
VAR19,
VAR66,
VAR111,
VAR47,
VAR10,
VAR44,
VAR15,
VAR2,
VAR86,
VAR102,
VAR133,
VAR124,
VAR13,
VAR112,
VAR115,
VAR36);
parameter VAR88 = 0;
parameter VAR51 = 0;
parameter VAR1... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/serial_shifter.v | 7,761 | module MODULE1
(
input VAR40,
input VAR28,
input VAR14,
input VAR43,
input [15:0] VAR36,
input [5:0] VAR2,
input VAR7,
input VAR45, input VAR52, input VAR31, input VAR42, input VAR27, input VAR48,
input [36:0] VAR17,
input VAR53, input VAR61,
input VAR30,
input VAR55,
input VAR19,
input VAR1,
input VAR60,
input [15:0] ... | gpl-3.0 |
megari/sd2snes | verilog/sd2sneslite/main.v | 9,650 | module MODULE1(
input VAR88,
input [23:0] VAR24,
input VAR20,
input VAR122,
input VAR92,
inout [7:0] VAR100,
input VAR102,
input VAR33,
output VAR38,
output VAR119,
output VAR18,
input VAR66,
input [7:0] VAR67,
input VAR39,
input VAR14,
inout [15:0] VAR108,
output [22:0] VAR106,
output VAR132,
output VAR127,
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o.pp.blackbox.v | 1,351 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR5,
VAR8,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR5;
input VAR8;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/mult_35x35.v | 5,324 | module MODULE1(input wire clk,
input wire [34:0] VAR4, VAR2,
output wire [69:0] VAR3);
parameter VAR1 = 8; | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/sysid.v | 1,434 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1362514660 : 0;
endmodule | mit |
Anirudh94/Connect4-FPGA | Connect4/redDiskModule_bb.v | 4,942 | module MODULE1 (
address,
VAR1,
VAR2);
input [7:0] address;
input VAR1;
output [2:0] VAR2;
tri1 VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a.behavioral.v | 1,549 | module MODULE1 (
VAR5 ,
VAR6,
VAR13,
VAR3,
VAR9,
VAR7
);
output VAR5 ;
input VAR6;
input VAR13;
input VAR3;
input VAR9;
input VAR7;
supply1 VAR4;
supply0 VAR11;
supply1 VAR15 ;
supply0 VAR10 ;
wire VAR12 ;
wire VAR14;
or VAR8 (VAR12 , VAR9, VAR3, VAR13, VAR6 );
and VAR1 (VAR14, VAR12, VAR7 );
buf VAR2 (VAR5 , VAR14 );
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.behavioral.v | 1,108 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR1 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR1 VAR2(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
Vadman97/ImageAES | des/DES/encrypt (Vadim-Laptop's conflicted copy 2017-04-27).v | 3,075 | module MODULE1(
VAR5,
VAR21,
VAR7,
VAR11,
clk,
reset,
enable,
ack
);
input [7:0][7:0] VAR5;
input [7:0][7:0] VAR21;
output [7:0][7:0] VAR7;
input clk, reset, enable, ack;
output VAR11;
reg [63:0] VAR13, VAR18, VAR15;
reg [5:0] state;
reg [55:0] VAR4;
reg [63:0] VAR3;
integer VAR20[55:0] = {57, 49, 41, 33, 25, 17, 9, 1,... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/wishbone/rtl/wb_reset.v | 3,428 | module MODULE1
parameter VAR13 = VAR14-1,
parameter VAR5 = 4,
parameter VAR1 = VAR5-1,
parameter VAR10 = 3)
(
input VAR19,
input VAR8,
input VAR11,
input VAR18,
input VAR15,
output reg VAR6 = 1'b0,
input [VAR13:0] VAR16,
output [VAR13:0] VAR3,
input VAR17, output reg VAR7 = 1'b0
);
reg reset = 1'b0;
reg [VAR1:0] VAR4 =... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2_2.v | 2,187 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR4 ,
VAR10,
VAR5,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR10;
input VAR5;
input VAR7 ;
input VAR2 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.pp.symbol.v | 1,365 | module MODULE1 (
input VAR2 ,
output VAR7 ,
input VAR5,
input VAR3 ,
input VAR1 ,
input VAR6 ,
input VAR4
);
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog/uart_tfifo.v | 8,813 | module MODULE1 (clk,
VAR20, VAR8, VAR5,
VAR25, VAR4, VAR19,
VAR7,
VAR27,
VAR10
);
parameter VAR24 = VAR2;
parameter VAR12 = VAR17;
parameter VAR15 = VAR14;
parameter VAR23 = VAR21;
input clk;
input VAR20;
input VAR25;
input VAR4;
input [VAR24-1:0] VAR8;
input VAR27;
input VAR10;
output [VAR24-1:0] VAR5;
output VAR19;
o... | mit |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,143 | module MODULE1 (
clk,
VAR4,
VAR29,
VAR22,
VAR5,
VAR26,
VAR24,
VAR6,
VAR1,
VAR7,
VAR3,
VAR17,
VAR8,
VAR14,
VAR13,
VAR20
)
;
output [ 37: 0] VAR26;
output VAR24;
output VAR6;
output VAR1;
output VAR7;
output VAR3;
output VAR17;
output VAR8;
output VAR14;
output VAR13;
output VAR20;
input clk;
input [ 1: 0] VAR4;
input [ ... | gpl-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_altpll_0.v | 10,951 | module MODULE1
(
VAR5,
VAR10,
VAR4,
VAR3) ;
input VAR5;
input VAR10;
input [0:0] VAR4;
output [0:0] VAR3;
tri0 VAR5;
tri1 VAR10;
reg [0:0] VAR1;
reg [0:0] VAR2;
reg [0:0] VAR8;
wire VAR6;
wire VAR9;
wire VAR7; | gpl-2.0 |
liqimai/ZPC | PersonalComputer/pg_to_PG.v | 1,028 | module MODULE1(
input [15:0] VAR1,
input [15:0] VAR4,
output [3:0] VAR2,
output [3:0] VAR3
);
assign VAR3[0]=VAR4[3 ]|VAR1[3 ]&VAR4[2 ]|VAR1[3 ]&VAR1[2 ]&VAR4[1 ]|VAR1[3 ]&VAR1[2 ]&VAR1[1 ]&VAR4[0 ],
VAR3[1]=VAR4[7 ]|VAR1[7 ]&VAR4[6 ]|VAR1[7 ]&VAR1[6 ]&VAR4[5 ]|VAR1[7 ]&VAR1[6 ]&VAR1[5 ]&VAR4[4 ],
VAR3[2]=VAR4[11]|VAR1... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_clock_mon.v | 5,117 | module MODULE1 (
VAR9,
VAR13,
VAR18,
VAR2,
VAR6);
input VAR9;
input VAR13;
output [31:0] VAR18;
input VAR2;
input VAR6;
reg [15:0] VAR7 = 'd0;
reg VAR15 = 'd0;
reg VAR17 = 'd0;
reg VAR10 = 'd0;
reg VAR3 = 'd0;
reg [31:0] VAR18 = 'd0;
reg VAR1 = 'd0;
reg VAR12 = 'd0;
reg VAR14 = 'd0;
reg VAR5 = 'd0;
reg [31:0] VAR11 = '... | gpl-3.0 |
rfotino/consolite-hardware | src/multiplier.v | 1,436 | module MODULE1
(
input clk,
input en,
input [VAR6-1:0] VAR4,
input [VAR6-1:0] VAR10,
output reg [(VAR6*2)-1:0] VAR2,
output VAR3
);
parameter VAR6 = 16;
localparam VAR7 = 0;
localparam VAR1 = 1;
reg state = VAR7;
reg [VAR11(VAR6)-1:0] VAR8 = 0;
reg [VAR6-1:0] VAR5 = 0;
reg [(VAR6*2)-1:0] VAR9 = 0;
assign VAR3 = (VAR7 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2.behavioral.v | 1,340 | module MODULE1 (
VAR10,
VAR2,
VAR3
);
output VAR10;
input VAR2;
input VAR3;
supply1 VAR4;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR8 ;
wire VAR6;
or VAR5 (VAR6, VAR3, VAR2 );
buf VAR7 (VAR10 , VAR6 );
endmodule | apache-2.0 |
jayrandez/Processor | memory_epp.v | 3,314 | module MODULE1(
input wire VAR21,
input wire VAR6,
input wire VAR19,
input wire VAR9,
output reg VAR7,
inout wire[7:0] VAR1,
input wire[7:6] VAR2,
input wire[31:0] address,
output wire[31:0] dout,
input wire[31:0] din,
output reg VAR26,
input wire VAR17
);
wire[7:0] VAR8[0:3];
assign VAR8[0] = address[7:0];
assign VAR8... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/gmii_139_1000.v | 50,953 | module MODULE1(
clk,
reset,
VAR19,
VAR1,
VAR25,
VAR5,
VAR9,
VAR3,
VAR17,
VAR2,
VAR29,
VAR15,
VAR28
);
input reset;
input clk;
input [7:0] VAR19; input VAR1;
input VAR25;
output VAR5; output [138:0] VAR9;
input [7:0]VAR3;
output VAR29;
output VAR15;
output VAR28;
output VAR17; output VAR2;
reg VAR5;
reg [138:0] VAR9;
re... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rxc_engine_128.v | 19,794 | module MODULE1
parameter VAR133=10)
( input VAR68,
input VAR129, input VAR38, output VAR86,
input [VAR85-1:0] VAR131,
input VAR61,
input VAR23,
input [VAR141-1:0] VAR55,
input VAR40,
input [VAR141-1:0] VAR143,
input [VAR46-1:0] VAR33,
output [VAR85-1:0] VAR54,
output VAR4,
output [(VAR85/32)-1:0] VAR5,
output VAR63,
ou... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_sram_cs.v | 1,942 | module MODULE1 (
address,
clk,
VAR1,
VAR5,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input VAR1;
input VAR5;
wire VAR3;
wire VAR4;
wire VAR6;
reg [ 31: 0] VAR2;
assign VAR3 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR4;
always @(posedge clk or negedge VAR5)
begin
if (VAR5 == 0)
VAR2 <= 0;
end
el... | gpl-3.0 |
babykiss4ever/MipsCPU | CPU/sccpu_dataflow.v | 2,853 | module MODULE1(VAR46, VAR55, VAR41, VAR17, VAR33, VAR14, VAR62, VAR2, VAR60, VAR3 );
input [31:0] VAR41, VAR17;
input VAR46, VAR55;
output [31:0] VAR33, VAR62, VAR2;
output VAR14;
input [4:0]VAR60;
output [31:0] VAR3;
wire [1:0] VAR39; wire [3:0] VAR19; wire VAR15; wire VAR14; wire VAR48; wire VAR43; wire VAR6; wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.functional.v | 1,267 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
wire VAR3;
not VAR5 (VAR3, VAR2 );
buf VAR1 (VAR4 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.pp.blackbox.v | 1,392 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR1,
VAR6,
VAR2,
VAR4 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR6;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o_2.v | 2,299 | module MODULE2 (
VAR10 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR7 ,
VAR5,
VAR6
);
output VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR5;
input VAR6;
VAR2 VAR3 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODUL... | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/uart_d.v | 4,807 | module MODULE1 #(
parameter VAR37 = 100000000,
parameter VAR4 = 115200
) (
input [31:0] VAR9,
input [31:0] VAR5,
input VAR49,
input VAR14,
output reg [31:0] VAR23,
output VAR44,
input VAR36,
input VAR17,
output VAR21,
output VAR11,
input VAR27,
output VAR20,
input VAR13
);
reg [15:0] VAR30;
wire [7:0] VAR48;
wire [7:0]... | mit |
eleqian/WiDSO | CPLD/DSO_LA/src/sspi.v | 5,022 | module MODULE3(VAR10, clk, VAR5, VAR27, VAR32);
input VAR10;
input clk;
input [2:0] VAR5;
output VAR27;
output VAR32;
reg VAR6;
wire VAR11;
assign VAR11 = (VAR5 == 3'b111);
always @(posedge clk or negedge VAR10) begin
if (~VAR10) begin
VAR6 <= 1'b0;
end else begin
VAR6 <= VAR11;
end
end
assign VAR32 = ({VAR6, VAR11} ==... | mit |
qiuzou/nysa_saya | rtl/generic/ppfifo.v | 18,880 | module MODULE1
VAR25 = 4
)(
input reset,
input VAR59,
output reg [1:0] VAR36,
input [1:0] VAR69,
output [23:0] VAR8,
input VAR1,
input [VAR58 - 1: 0] VAR45,
output VAR43,
input VAR42,
input VAR68,
output reg VAR40,
input VAR3,
output reg [23:0] VAR13,
output [VAR58 - 1: 0] VAR7,
output VAR62
);
localparam VAR5 = (1 << ... | mit |
Jafet95/proy_3_grupo_2_sem_1_2016 | microcontrolador.v | 1,895 | module MODULE1
(
input wire clk, reset,
input wire interrupt,
input wire [7:0] VAR19,
output wire VAR12, VAR2, VAR5,
output wire VAR4,
output wire [7:0] VAR14,
output wire [7:0] VAR18
);
wire [11:0] address;
wire [17:0] VAR7;
wire VAR17;
wire VAR24;
wire VAR11;
wire VAR1;
assign VAR11 = reset | VAR1;
assign VAR24 = 1'b... | mit |
tommythorn/yari | Icarus/rtl/regfile.v | 1,469 | module MODULE1(input wire VAR3,
input wire enable,
input wire [ 4:0] VAR9,
input wire [ 4:0] VAR6,
input wire VAR8,
input wire [ 4:0] VAR7,
input wire [31:0] VAR5,
output reg [31:0] VAR10, output reg [31:0] VAR1 );
reg [31:0] VAR2 [31:0];
always @(posedge VAR3)
if (enable) begin
if (VAR8)
VAR2[VAR7] <= VAR5;
VAR10 <= V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.behavioral.v | 2,646 | module MODULE1 (
VAR13 ,
VAR26 ,
VAR19 ,
VAR27 ,
VAR1 ,
VAR24 ,
VAR6 ,
VAR18,
VAR4
);
output VAR13 ;
output VAR26 ;
input VAR19 ;
input VAR27 ;
input VAR1 ;
input VAR24 ;
input VAR6 ;
input VAR18;
input VAR4;
wire VAR16 ;
reg VAR22 ;
wire VAR11 ;
wire VAR8 ;
wire VAR28;
wire VAR15;
wire VAR25;
wire VAR2 ;
wire VAR9 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv.symbol.v | 1,264 | module MODULE1 (
input VAR5,
output VAR6
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaWriteDwordReg.v | 1,861 | module MODULE1
(
input wire reset,
output wire [31:0] out,
input wire [11:0] VAR7, inout wire [7:0] VAR8 );
parameter VAR6 = 0;
wire VAR3 = (VAR6 == VAR7[11:4]);
wire write = VAR3 & VAR7[2];
reg [1:0] select;
always @(posedge VAR7[0])
begin
if( reset | ~VAR3)
select <= 2'h0;
end
else if(VAR7[1] & VAR3)
select <= select... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/controller/mig_7series_v2_3_arb_select.v | 26,779 | module MODULE1 #
(
parameter VAR2 = 100,
parameter VAR54 = "VAR7",
parameter VAR59 = "1T",
parameter VAR127 = 11,
parameter VAR124 = 3,
parameter VAR67 = "8",
parameter VAR1 = 4,
parameter VAR22 = 5,
parameter VAR43 = 5,
parameter VAR21 = 31,
parameter VAR62 = 8,
parameter VAR141 = "VAR72",
parameter VAR41 = "VAR7",
pa... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.behavioral.pp.v | 2,375 | module MODULE1( VAR10, VAR3, VAR5, VAR7, VAR4, VAR6, VAR1 );
input VAR7, VAR4, VAR3, VAR10;
inout VAR6, VAR1;
output VAR5;
VAR2 VAR9(.VAR10(VAR10),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR8(.VAR10(VAR10),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.behavioral.pp.v | 1,967 | module MODULE1 (
VAR9,
VAR5,
VAR3 ,
VAR8 ,
VAR13 ,
VAR6
);
input VAR9;
input VAR5;
output VAR3 ;
input VAR8 ;
input VAR13 ;
input VAR6;
wire VAR14 ;
wire VAR12 ;
wire VAR4;
nor VAR10 (VAR14 , VAR8, VAR13 );
nor VAR1 (VAR12 , VAR6, VAR14 );
VAR7 VAR11 (VAR4, VAR12, VAR9, VAR5);
buf VAR2 (VAR3 , VAR4 );
endmodule | apache-2.0 |
iceman1001/proxmark3 | fpga/hi_read_rx_xcorr.v | 6,579 | module MODULE1(
VAR29, VAR25, VAR8,
VAR16, VAR15, VAR10, VAR27, VAR1, VAR18,
VAR30, VAR9,
VAR21, VAR20, VAR4, VAR11,
VAR28, VAR13,
VAR2,
VAR6, VAR14, VAR26
);
input VAR29, VAR25, VAR8;
output VAR16, VAR15, VAR10, VAR27, VAR1, VAR18;
input [7:0] VAR30;
output VAR9;
input VAR4;
output VAR21, VAR20, VAR11;
input VAR28, VA... | gpl-2.0 |
CospanDesign/sdio-device | rtl/generic/crc7.v | 2,417 | module MODULE1 #(
parameter VAR3 = 8'h09,
parameter VAR2 = 8'h00
)(
input clk,
input rst,
input bit,
output reg [6:0] VAR1,
input en
);
wire VAR4;
assign VAR4 = bit ^ VAR1[6];
always @ (posedge clk) begin
if (rst) begin
VAR1 <= VAR2;
end
else begin
if (en) begin
VAR1[6] <= VAR1[5];
VAR1[5] <= VAR1[4];
VAR1[4] <= VAR1[3... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbHost.v | 10,886 | module MODULE1(
VAR52,
VAR15,
VAR19,
VAR114,
VAR134,
VAR98,
VAR107,
VAR23,
VAR113,
VAR90,
VAR7,
VAR43,
VAR119,
VAR112,
VAR37,
VAR64,
VAR106,
VAR44,
VAR85
);
parameter VAR70 = 64; parameter VAR22 = 6;
input VAR52; input VAR15; input [7:0] VAR19; input [7:0] VAR114; output [7:0] VAR134; input VAR98; input VAR107; output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai_4.v | 2,261 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR7 ,
VAR9 ,
VAR5,
VAR8,
VAR4 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR5;
input VAR8;
input VAR4 ;
input VAR6 ;
VAR1 VAR10 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_EP_MEM_ACCESS.v | 12,467 | module MODULE1 (
clk,
VAR81,
VAR50, VAR22, VAR71,
VAR6, VAR87, VAR78, VAR16, VAR26
);
input clk;
input VAR81;
input [10:0] VAR50;
input [3:0] VAR22;
output [31:0] VAR71;
input [10:0] VAR6;
input [7:0] VAR87;
input [31:0] VAR78;
input VAR16;
output VAR26;
wire [31:0] VAR71;
reg [31:0] VAR23;
wire [31:0] VAR14, VAR32, VA... | lgpl-3.0 |
sergachev/spi_mem_programmer | top.v | 4,915 | module MODULE1 (
input VAR18,
output reg [1:0] VAR11,
output VAR29,
input rst,
inout [3:0] VAR40,
output VAR13
);
wire VAR37, clk;
wire VAR35;
assign VAR29 = VAR37;
wire rst = ~VAR35;
wire [7:0] VAR41;
wire VAR10;
wire VAR27;
reg VAR42;
reg VAR31;
reg [7:0] VAR15;
reg [(3+256)*8-1:0] VAR5;
reg [4:0] state;
VAR8 VAR39 (... | mit |
fallen/milkymist-mmu | cores/minimac2/rtl/minimac2_rx.v | 3,387 | module MODULE1(
input VAR16,
input [1:0] VAR17,
output [1:0] VAR6,
output reg [10:0] VAR3,
output reg [10:0] VAR21,
output [7:0] VAR22,
output [10:0] VAR1,
output VAR2,
output [7:0] VAR9,
output [10:0] VAR15,
output VAR19,
input VAR5,
input [3:0] VAR11,
input VAR30
);
reg [1:0] VAR23;
always @(posedge VAR16)
VAR23 <= (... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_lane_init_sm.v | 17,892 | module MODULE1
(
VAR30,
VAR65,
VAR55,
VAR29,
VAR41,
VAR16,
VAR38,
VAR8,
VAR49,
VAR5,
VAR47,
VAR12,
VAR61,
VAR52,
VAR11,
VAR43,
VAR23,
VAR15,
VAR45,
VAR51
);
input [1:0] VAR30; input [1:0] VAR65; input [1:0] VAR55; input VAR29;
output VAR41; output VAR16; output VAR38;
output VAR8;
output VAR49; output [0:1] VAR5; outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.symbol.v | 1,254 | module MODULE1 (
input VAR3,
input VAR6,
output VAR5
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/MultiplyMult.v | 1,577 | module MODULE1(
input [32:0] VAR3,
input [32:0] VAR7,
input [32:0] VAR4,
input VAR15,
input VAR11,
output reg VAR5,
output reg [32:0] VAR16,
output reg [49:0] VAR12
);
parameter VAR8 = 1'b0,
VAR14 = 1'b1;
wire VAR10;
wire [7:0] VAR1;
wire [23:0] VAR13;
wire VAR6;
wire [7:0] VAR2;
wire [23:0] VAR9;
assign VAR10 = VAR3[3... | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_ifid_register.v | 2,450 | module MODULE1 (
input clk, input rst, input [31:0] VAR11, input [31:0] VAR9, input [31:0] VAR5, input VAR4, input VAR6, input VAR10, input VAR2, output reg [31:0] VAR8, output reg [31:0] VAR3, output reg [31:0] VAR1, output reg VAR12, output reg VAR7 );
always @(posedge clk) begin
VAR8 <= (rst) ? 32'b0 : ((VAR2) ? VAR... | mit |
alexforencich/xfcp | lib/eth/rtl/eth_mac_1g_rgmii_fifo.v | 10,576 | module MODULE1 #
(
parameter VAR43 = "VAR53",
parameter VAR25 = "VAR12",
parameter VAR76 = "VAR81",
parameter VAR6 = "VAR98",
parameter VAR52 = 8,
parameter VAR16 = (VAR52>8),
parameter VAR88 = (VAR52/8),
parameter VAR31 = 1,
parameter VAR91 = 64,
parameter VAR103 = 4096,
parameter VAR47 = 2,
parameter VAR101 = 1,
para... | mit |
stevenokm/mor1kx | rtl/verilog/mor1kx_bus_if_avalon.v | 2,333 | module MODULE1
parameter VAR3 = 4
)
(
input clk,
input rst,
output VAR8,
output VAR5,
output [31:0] VAR13,
input [31:0] VAR15,
input [31:0] VAR23,
input VAR11,
input [3:0] VAR19,
input VAR20,
input VAR2,
output [31:0] VAR12,
output [3:0] VAR14,
output VAR9,
input [31:0] VAR6,
output [3:0] VAR22,
output VAR21,
output [3... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.functional.v | 1,226 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR1;
notif0 VAR2 (VAR4 , VAR3, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2_2.v | 1,959 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR3 ,
VAR4,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR5,
VAR3
);
output VAR7;
input VAR5;
input VAR3;
supply1 VAR4;
supply0 VAR6;
VAR2 VAR1 (
.... | apache-2.0 |
Cognoscan/BoostDSP | verilog/src/sigmaDelta/SigmaDelta1stOrder.v | 1,196 | module MODULE1 #(
parameter VAR4 = 0, parameter VAR2 = 16, parameter VAR3 = 1 )
(
input clk,
input rst,
input en,
input signed [VAR2-1:0] in,
output signed [VAR3-1:0] VAR5
);
localparam VAR7 = (VAR4 && (VAR3 != 1)) ? 1 : 0;
localparam VAR6 = VAR7 ? (VAR2-VAR3-1) : (VAR2-VAR3);
reg [VAR6:0] VAR8;
reg signed [VAR3-1:0] V... | apache-2.0 |
antmicro/yosys | techlibs/common/techmap.v | 15,828 | module 90simplemapboolops;
endmodule
module 90simplemapreduceops;
endmodule
module 90simplemaplogicops;
endmodule
module 90simplemapcompareops;
endmodule
module 90simplemapvarious;
endmodule
module 90simplemapregisters;
endmodule
module 90shiftopsshrshlsshlsshr (VAR34, VAR17, VAR26);
parameter VAR47 = 0;
parameter VAR2... | isc |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit5.v | 7,023 | module MODULE1 (output reg VAR21, VAR15, VAR7, VAR11, VAR20, VAR6, VAR10, VAR13,VAR22,VAR19,VAR8,VAR17,VAR1,output reg[4:0] VAR5, output reg[3:0] VAR14, input VAR2, VAR12,VAR4, input [31:0] VAR9,input [3:0] VAR16);
reg [4:0] VAR3, VAR18;
always @ (negedge VAR4, posedge VAR12)
if (VAR12) begin
VAR3 <= 5'b00001;VAR6 = 0 ... | apache-2.0 |
richard42/CoCo3FPGA | 6551tx.v | 5,333 | module MODULE1(
VAR9,
VAR5,
VAR14,
VAR16,
VAR6,
VAR7,
VAR12,
VAR10,
VAR3,
VAR11,
VAR1
);
input VAR9;
input VAR5;
output VAR14;
reg VAR14;
input VAR16;
output VAR6;
reg VAR6;
input VAR7;
input [1:0] VAR12;
input VAR10;
input [1:0] VAR3;
input VAR11;
input [7:0] VAR1;
reg [6:0] VAR4;
reg [2:0] VAR8;
wire VAR15;
reg VAR2;... | bsd-3-clause |
sehugg/8bitworkshop | presets/verilog/digits10.v | 4,959 | module MODULE1(VAR1, VAR7, VAR5);
input [3:0] VAR1; input [2:0] VAR7; output reg [4:0] VAR5;
wire [6:0] VAR2 = {VAR1,VAR7};
always @(*)
case (VAR2)
7'o00: VAR5 = 5'b11111;
7'o01: VAR5 = 5'b10001;
7'o02: VAR5 = 5'b10001;
7'o03: VAR5 = 5'b10001;
7'o04: VAR5 = 5'b11111;
7'o10: VAR5 = 5'b01100;
7'o11: VAR5 = 5'b00100;
7'o1... | gpl-3.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_e/hdl/verilog/tft_if.v | 8,801 | module MODULE1(
clk, rst, VAR27, VAR17, VAR63, VAR21, VAR74, VAR12, VAR2, VAR32, VAR1, VAR75, VAR77, VAR30, VAR35, VAR64, VAR60, VAR31, VAR58, VAR62, VAR18, VAR56, VAR54, VAR13, VAR68, VAR44, VAR79, VAR76, VAR71, VAR55, VAR59, VAR34, VAR6, VAR66, VAR5, VAR16, VAR61, VAR49, VAR40, VAR8, VAR51, VAR39, VAR52, VAR14, VAR33... | gpl-3.0 |
aj-michael/Digital-Systems | Latches/p2hw3latches2015fall.v | 1,045 | module MODULE1(VAR2, VAR6, VAR1, VAR3, VAR5);
input VAR2, VAR1, VAR3;
output reg VAR6;
output reg [1:0] VAR5;
reg [1:0] VAR9;
parameter VAR8 = 0, VAR7 = 1, VAR4 = 2, VAR10 = 3;
always @ (VAR5)
if(VAR5==VAR8) VAR6<=1;
else if (VAR5==VAR10) VAR6<=0;
else VAR6<=0;
always @ (posedge VAR3)
if (VAR1==1) VAR5 <= VAR8; else VA... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Encoder_Peripheral_Hardware_Specification.v | 4,382 | module MODULE1
(
VAR28,
reset,
VAR16,
VAR29,
VAR22,
VAR20,
valid,
VAR18
);
input VAR28;
input reset;
input VAR16;
input VAR29;
input VAR22;
input VAR20;
output valid;
output [15:0] VAR18;
wire VAR11;
wire VAR34;
wire VAR40;
wire VAR6;
wire VAR8;
wire VAR13;
wire VAR24;
wire VAR30;
wire signed [15:0] VAR1; wire signed [... | gpl-3.0 |
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