repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_4.functional.v | 1,787 | module MODULE1( VAR10, VAR21, VAR2, VAR4, VAR6, VAR5, VAR26, VAR13 );
input VAR4, VAR2, VAR5, VAR10, VAR6, VAR21, VAR13;
output VAR26;
not VAR17( VAR24, VAR5 );
not VAR23( VAR8, VAR6 );
wire VAR1;
not VAR15( VAR1, VAR2 );
wire VAR20;
not VAR28( VAR20, VAR10 );
wire VAR22;
and VAR25( VAR22, VAR1, VAR20 );
wire VAR19;
no... | apache-2.0 |
blu006/de0-nano-clock | FPGA/DE0_Nano.v | 4,686 | module MODULE1(
VAR22,
VAR34,
VAR49,
VAR40,
VAR45,
VAR43,
VAR35,
VAR4,
VAR51,
VAR3,
VAR10,
VAR11,
VAR36,
VAR16,
VAR47,
VAR18,
VAR42,
VAR8,
VAR26,
VAR2,
VAR9,
VAR38,
VAR20,
VAR32,
VAR19,
VAR7,
VAR28,
VAR50
);
input VAR22;
output [7:0] VAR34;
input [1:0] VAR49;
input [3:0] VAR40;
output [12:0] VAR45;
output [1:0] VAR43;
... | bsd-2-clause |
trnewman/VT-USRP-daughterboard-drivers | gr-gpio/src/fpga/lib/rx_chain.v | 3,770 | module MODULE1
(input VAR44,
input reset,
input enable,
input wire [7:0] VAR16,
input VAR21,
input VAR12,
output wire VAR27,
input [6:0] VAR22, input [31:0] VAR15, input VAR40,
input wire [15:0] VAR39,
input wire [15:0] VAR26,
output wire [15:0] VAR33,
output wire [15:0] VAR25,
output wire [15:0] VAR42,output wire [15:... | gpl-3.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_dc_ram.v | 4,216 | module MODULE1(
clk, rst,
VAR14, VAR2, VAR7,
addr, en, VAR1, VAR13, VAR18
);
parameter VAR10 = VAR8;
parameter VAR15 = VAR17;
input clk;
input rst;
input [VAR15-1:0] addr;
input en;
input [3:0] VAR1;
input [VAR10-1:0] VAR13;
output [VAR10-1:0] VAR18;
input VAR14;
input [VAR11 - 1:0] VAR7; output VAR2;
assign VAR18 = {V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR3 ,
VAR13 ,
VAR15 ,
VAR17 ,
VAR11 ,
VAR16,
VAR12,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR13 ;
input VAR15 ;
input VAR17 ;
input VAR11 ;
input VAR16;
input VAR12;
input VAR1 ;
input VAR9 ;
wire VAR7 ;
wire VAR4 ;
wire VAR14;
not VAR10 (VAR7 , VAR11 );
nor VAR2 (VAR4 , VAR13, VAR15, VAR17, VAR7 );
VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi_4.v | 2,134 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR5 ,
VAR3 ,
VAR2,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR2;
input VAR6;
VAR7 VAR8 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1 ,
VAR4,
VAR5,
VAR3
);
output VAR1 ;
input VAR4;
input VAR5;
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.behavioral.pp.v | 1,159 | module MODULE1( VAR6, VAR3, VAR1, VAR4 );
input VAR6;
inout VAR1, VAR4;
output VAR3;
VAR2 VAR7(.VAR6(VAR6),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR5(.VAR6(VAR6),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/controller/rank_cntrl.v | 16,480 | module MODULE1 #
(
parameter VAR60 = 100,
parameter VAR82 = "8",
parameter VAR31 = 0,
parameter VAR1 = 4,
parameter VAR77 = 2,
parameter VAR86 = 5,
parameter VAR4 = 30,
parameter VAR37 = 8,
parameter VAR50 = 4,
parameter VAR66 = 4,
parameter VAR81 = 20,
parameter VAR39 = 16,
parameter VAR72 = 2,
parameter VAR11 = 4,
pa... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_prtq_ctl.v | 12,397 | module MODULE1 (
VAR83, VAR42, VAR54, VAR5,
VAR68, VAR93, VAR60, VAR8,
VAR38, VAR31, VAR18, VAR75,
VAR30, VAR59, VAR81, VAR47,
VAR36,
clk, VAR9, VAR17, VAR84, VAR32,
VAR52, VAR61, VAR92, VAR19,
VAR6, VAR73, VAR46, VAR26,
VAR25, VAR33, VAR45, VAR43,
VAR72, VAR55, VAR39, VAR71
);
input clk;
input VAR9;
input VAR17;
input... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_rx_v1_00_a/hdl/verilog/embedded_sync_decoder.v | 4,055 | module MODULE1(
input clk,
input [15:0] VAR7,
output reg VAR9,
output reg VAR5,
output reg [15:0] VAR10
);
reg [15:0] VAR18 = 'd0;
reg VAR19 = 'd0;
reg VAR11 = 'd0;
reg [15:0] VAR6 = 'd0;
reg VAR14 = 'd0;
reg VAR4 = 'd0;
reg [15:0] VAR16 = 'd0;
reg VAR3 = 'd0;
reg VAR15 = 'd0;
reg [15:0] VAR2 = 'd0;
reg VAR13 = 'd0;
re... | mit |
jck/myhdl | example/cookbook/bitonic/Array8Sorter.v | 19,991 | module MODULE1 (
VAR15,
VAR26,
VAR68,
VAR30,
VAR6,
VAR111,
VAR72,
VAR44,
VAR112,
VAR102,
VAR9,
VAR29,
VAR18,
VAR83,
VAR60,
VAR28
);
input [3:0] VAR15;
input [3:0] VAR26;
input [3:0] VAR68;
input [3:0] VAR30;
input [3:0] VAR6;
input [3:0] VAR111;
input [3:0] VAR72;
input [3:0] VAR44;
output [3:0] VAR112;
wire [3:0] VAR1... | lgpl-2.1 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/altera_reset_controller.v | 12,025 | module MODULE1
parameter VAR14 = 6,
parameter VAR26 = 0,
parameter VAR4 = 0,
parameter VAR61 = 0,
parameter VAR10 = 0,
parameter VAR1 = 0,
parameter VAR40 = 0,
parameter VAR52 = 0,
parameter VAR11 = 0,
parameter VAR68 = 0,
parameter VAR37 = 0,
parameter VAR71 = 0,
parameter VAR77 = 0,
parameter VAR23 = 0,
parameter VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai_1.v | 2,329 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR8 ,
VAR4,
VAR5,
VAR1,
VAR7 ,
VAR3
);
output VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR4;
input VAR5;
input VAR1;
input VAR7 ;
input VAR3 ;
VAR10 VAR2 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.functional.v | 1,457 | module MODULE1 (
VAR9 ,
VAR7,
VAR8,
VAR6,
VAR5
);
output VAR9 ;
input VAR7;
input VAR8;
input VAR6;
input VAR5;
wire VAR3 ;
wire VAR2;
and VAR10 (VAR3 , VAR7, VAR8 );
nor VAR4 (VAR2, VAR3, VAR6, VAR5);
buf VAR1 (VAR9 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_2.v | 2,414 | module MODULE1 (
VAR7 ,
VAR9,
VAR2,
VAR6 ,
VAR10 ,
VAR5,
VAR1,
VAR3 ,
VAR8
);
output VAR7 ;
input VAR9;
input VAR2;
input VAR6 ;
input VAR10 ;
input VAR5;
input VAR1;
input VAR3 ;
input VAR8 ;
VAR4 VAR11 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VA... | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/hamdec.v | 3,239 | module MODULE1(
VAR1,
VAR4,
VAR2,
VAR8);
input [VAR6-1:0] VAR1; input [VAR7-1:0] VAR4;
output reg [VAR6-1:0] VAR2; output reg VAR8;
wire [3:0] VAR3;
assign #VAR5 VAR3[0] = VAR4[3] ^ VAR1[7] ^ VAR1[6] ^ VAR1[4] ^ VAR1[3] ^ VAR1[1];
assign #VAR5 VAR3[1] = VAR4[2] ^ VAR1[7] ^ VAR1[5] ^ VAR1[4] ^ VAR1[2] ^ VAR1[1];
assign ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.behavioral.pp.v | 2,064 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR14 ,
VAR4 ,
VAR18 ,
VAR5 ,
VAR7,
VAR8,
VAR15 ,
VAR1
);
output VAR3 ;
input VAR12 ;
input VAR14 ;
input VAR4 ;
input VAR18 ;
input VAR5 ;
input VAR7;
input VAR8;
input VAR15 ;
input VAR1 ;
wire VAR13 ;
wire VAR9 ;
wire VAR2;
and VAR16 (VAR13 , VAR4, VAR12, VAR14 );
or VAR6 (VAR9 , VAR1... | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog-backup/uart_regs.v | 15,401 | module MODULE1 (clk,
VAR35, VAR53, VAR31, VAR40, VAR36, VAR13,
VAR80,
VAR47, VAR42,
enable,
VAR55, VAR37, VAR22
);
input clk;
input VAR35;
input [VAR9-1:0] VAR53;
input [7:0] VAR31;
output [7:0] VAR40;
input VAR36;
input VAR13;
output VAR47;
input VAR42;
input [3:0] VAR80;
output enable;
output VAR55;
output VAR37;
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o_4.v | 2,248 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR9,
VAR3,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR9;
input VAR3;
input VAR5 ;
input VAR8 ;
VAR6 VAR7 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.functional.pp.v | 2,064 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR17 ,
VAR10 ,
VAR2 ,
VAR1,
VAR6,
VAR4 ,
VAR15
);
output VAR9 ;
input VAR12 ;
input VAR17 ;
input VAR10 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR4 ;
input VAR15 ;
wire VAR3 ;
wire VAR8 ;
wire VAR7;
and VAR11 (VAR3 , VAR12, VAR17 );
nor VAR14 (VAR8 , VAR3, VAR10, VAR2 );
VAR13 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.symbol.v | 1,278 | module MODULE1 (
output VAR6,
output VAR1
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
skyfex/svo-raycaster | raycaster2/divider.v | 1,164 | module MODULE1 (
VAR12, VAR8, VAR5, VAR7, clk, VAR6, VAR10, VAR11, VAR4
);
output reg VAR12;
output reg VAR8;
output reg VAR5;
input VAR7;
input clk;
input [3 : 0] VAR6;
output reg [3 : 0] VAR10;
input [31 : 0] VAR11;
output reg [31 : 0] VAR4;
wire signed [63:0] VAR3 = {28'b0, VAR6, 32'b0};
wire signed [63:0] VAR9 = {{... | mit |
SymbiFlow/fpga-tool-perf | src/bram/rom.v | 18,387 | module MODULE1 #
(
parameter VAR5 = 9 )
(
input wire VAR10,
input wire VAR2,
input wire VAR8,
input wire [VAR5-1:0] VAR1,
output wire VAR9,
output wire [31:0] VAR6
);
localparam VAR7 = (1<<VAR5);
reg [31:0] MODULE1 [0:VAR7-1];
reg VAR4;
reg [31:0] VAR3;
always @(posedge VAR10)
VAR3 <= MODULE1[VAR1];
always @(posedge VA... | isc |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/wasca_onchip_memory2_0.v | 2,943 | module MODULE1 (
address,
VAR3,
VAR14,
clk,
VAR5,
reset,
VAR23,
write,
VAR31,
VAR6
)
;
parameter VAR9 = "MODULE1.VAR21";
output [ 31: 0] VAR6;
input [ 11: 0] address;
input [ 3: 0] VAR3;
input VAR14;
input clk;
input VAR5;
input reset;
input VAR23;
input write;
input [ 31: 0] VAR31;
wire VAR11;
wire [ 31: 0] VAR6;
wire... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Maintain_Range.v | 1,084 | module MODULE1
(
VAR3,
VAR1
);
input signed [35:0] VAR3; output signed [17:0] VAR1;
wire signed [17:0] VAR2;
assign VAR2 = VAR3[35:18];
assign VAR1 = VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai_4.v | 2,330 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR10 ,
VAR7,
VAR8
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR7;
input VAR8;
VAR6 VAR9 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODUL... | apache-2.0 |
trun/fpgaboy | src/tv80/rtl/core/tv80n.v | 4,810 | module MODULE1 (
VAR20, VAR12, VAR15, VAR14, VAR2, VAR19, VAR18, VAR31, VAR17, do,
VAR7, clk, VAR23, VAR16, VAR30, VAR6, VAR1
);
parameter VAR29 = 0; parameter VAR24 = 0; parameter VAR26 = 1;
input VAR7;
input clk;
input VAR23;
input VAR16;
input VAR30;
input VAR6;
output VAR20;
output VAR12;
output VAR15;
output VAR14... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.behavioral.pp.v | 1,174 | module MODULE1( VAR4, VAR5, VAR2, VAR3 );
input VAR4;
inout VAR2, VAR3;
output VAR5;
VAR6 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR3(VAR3));
VAR6 VAR7(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_1.v | 2,448 | module MODULE2 (
VAR10 ,
VAR11 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR12 ,
VAR8,
VAR7,
VAR6 ,
VAR9
);
output VAR10 ;
input VAR11 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR12 ;
input VAR8;
input VAR7;
input VAR6 ;
input VAR9 ;
VAR5 VAR4 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR12(VAR12),
.VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.functional.v | 1,443 | module MODULE1( VAR5, VAR14, VAR3, VAR2, VAR8 );
input VAR3, VAR14, VAR2, VAR8;
output VAR5;
wire VAR15;
not VAR16( VAR15, VAR3 );
wire VAR6;
not VAR9( VAR6, VAR14 );
wire VAR7;
and VAR13( VAR7, VAR15, VAR6 );
wire VAR1;
not VAR10( VAR1, VAR2 );
wire VAR4;
not VAR12( VAR4, VAR8 );
or VAR11( VAR5, VAR7, VAR1, VAR4 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_1.v | 2,398 | module MODULE1 (
VAR6 ,
VAR5,
VAR7,
VAR10 ,
VAR3 ,
VAR9,
VAR1,
VAR11 ,
VAR2
);
output VAR6 ;
input VAR5;
input VAR7;
input VAR10 ;
input VAR3 ;
input VAR9;
input VAR1;
input VAR11 ;
input VAR2 ;
VAR4 VAR8 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR2... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_tdd_if.v | 4,484 | module MODULE1(
clk,
rst,
VAR14,
VAR2,
VAR8,
VAR10,
VAR13,
VAR4,
VAR16
);
parameter VAR7 = 0;
localparam VAR6 = 0;
localparam VAR11 = 1;
input clk;
input rst;
input VAR14;
input VAR2;
input VAR8;
input VAR10;
output VAR13;
output VAR4;
output [ 7:0] VAR16;
reg VAR3 = 1'b0;
reg VAR5 = 1'b0;
reg VAR9 = 1'b0;
reg VAR1 = 1... | gpl-3.0 |
Willster419/ELEC3725_vivado_projects | assignment_1/alu32.v | 5,195 | module MODULE1 (VAR10, VAR15, VAR13, VAR17, VAR5, VAR4, VAR2);
output[31:0] VAR10; output VAR15, VAR13; input [31:0] VAR17, VAR5; input VAR4; input [2:0] VAR2;
wire [31:0] VAR14, VAR1, VAR11;
wire VAR7, VAR20;
MODULE6 MODULE5[31:0] (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR17(VAR17),
.VAR5(VAR5),
.VAR14(VAR14),
... | gpl-3.0 |
asicguy/gplgpu | hdl/de3d/des_top.v | 25,383 | module MODULE1
(
input VAR277, input VAR94, input VAR52, input VAR220, input VAR14,
input [1:0] VAR67, input VAR259,
input VAR197,
input VAR256, input VAR102, input VAR180,
input VAR227,
input VAR194,
input VAR31,
input [351:0] VAR36,
input [351:0] VAR158,
input [351:0] VAR254,
input VAR63, input VAR161,
input VAR16, i... | gpl-3.0 |
AleCher/ipstack | implementation/devboard_top.v | 4,120 | module MODULE1 #( parameter VAR58 = 32'd300000000 )(
output wire [7:0] VAR56,
input wire [7:0] VAR28,
input wire [3:0] VAR64,
input wire VAR85,
input wire VAR15,
input wire VAR37,
input wire VAR53,
input wire VAR82,
output wire VAR65,
output wire [7:0] VAR66,
output wire VAR89,
output wire VAR68,
output wire VAR69,
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2_1.v | 2,164 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR1,
VAR7,
VAR2 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR8 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
supply1 VAR1;
supply0 VAR7;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai.blackbox.v | 1,402 | module MODULE1 (
VAR2 ,
VAR10,
VAR7,
VAR6,
VAR8,
VAR3
);
output VAR2 ;
input VAR10;
input VAR7;
input VAR6;
input VAR8;
input VAR3;
supply1 VAR1;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
EliasLuiz/TCC | Leon3/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v | 13,359 | module MODULE1(
input VAR1,
input reset,
input VAR8,
input [7:0] VAR49,
input VAR27,
output reg [7:0] VAR30,
output reg VAR12,
input VAR32,
input VAR20,
output reg VAR2,
output reg VAR22,
input VAR54,
output [3:0] VAR34
);
reg VAR19;
reg VAR10;
reg VAR23;
always @(posedge VAR1, posedge reset)
if (reset) VAR19 <= 0;
els... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/ModTxtMemW.v | 3,788 | module MODULE1(VAR28, reset,
VAR32, VAR26,
VAR14, VAR2,
VAR30, VAR6, VAR27, VAR8, VAR7);
input VAR28;
input reset;
input[13:0] VAR32;
output[127:0] VAR26;
input[15:0] VAR14;
output[63:0] VAR2;
input[31:0] VAR30;
inout[31:0] VAR6;
input VAR27;
input VAR8;
output[1:0] VAR7;
reg[1:0] VAR15; reg[31:0] VAR5; wire VAR21;
ass... | mit |
Lan-Hekary/ARM | DataMem.v | 1,223 | module MODULE1(VAR4,VAR1,VAR2,VAR7,VAR9);
parameter VAR8 = 32,
VAR5 = 128;
input [VAR8-1:0] VAR4;
input [VAR8-1:0] VAR2;
input VAR7,VAR9;
output [VAR8-1:0]VAR1;
reg [VAR8-1:0] VAR3 [0:VAR5-1];
integer VAR6;
begin | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/ddr_core/user_design/rtl/ip_top/mig_7series_v1_9_memc_ui_top_std.v | 36,339 | module MODULE1 #
(
parameter VAR33 = 100,
parameter VAR62 = 64,
parameter VAR30 = "VAR69",
parameter VAR204 = "0", parameter VAR86 = 3, parameter VAR97 = 2, parameter VAR235 = "8", parameter VAR164 = "VAR59", parameter VAR239 = "VAR300", parameter VAR218 = 1, parameter VAR108 = 5,
parameter VAR244 = 12, parameter VAR18... | lgpl-3.0 |
lynxis/lpc_sniffer | ringbuffer.v | 1,331 | module MODULE1 #(parameter VAR10 = 8, VAR7 = 48)
(
input reset,
input VAR8,
input VAR14,
input VAR12,
output [VAR7-1:0] VAR2,
input [VAR7-1:0] VAR5,
output reg VAR15,
output reg VAR9);
reg [VAR10-1:0] VAR4;
reg [VAR10-1:0] VAR13;
reg [VAR10-1:0] VAR3;
wire VAR6;
wire VAR11;
assign VAR15 = VAR13 == VAR3;
assign VAR9 = V... | gpl-3.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_spram_1024x32_bw.v | 11,536 | module MODULE1(
VAR68, VAR65, VAR9,
clk, rst, VAR32, VAR40, VAR11, addr, VAR69, VAR24
);
input VAR68;
input [VAR49 - 1:0] VAR9; output VAR65;
input clk; input rst; input VAR32; input [3:0] VAR40; input VAR11; input [9:0] addr; input [31:0] VAR69; output [31:0] VAR24;
assign VAR65 = VAR68;
VAR15 VAR59(
VAR10 VAR59(
VAR1... | gpl-3.0 |
hcabrera-/lancetfish | RTL/nic/des_nic/rtl/des_network_interface.v | 5,372 | module MODULE1
(
input wire clk,
input wire reset,
output wire VAR28,
input wire [VAR19-1:0] VAR21,
input wire VAR25,
output wire [VAR19-1:0] VAR27,
output wire VAR15,
output wire [(2 * VAR19)-1:0] VAR5,
output wire [(2 * VAR19)-1:0] VAR13,
input wire VAR29,
input wire VAR23,
input wire [(2 * VAR19)-1:0] VAR16
);
wire ... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/phyIniCommand0_and.v | 1,177 | module MODULE1
(
input [(VAR5-1):0] VAR2,
input [(VAR6-1):0] addr,
input VAR4, clk,
output [(VAR5-1):0] VAR7
);
reg [VAR5-1:0] VAR3[2**VAR6-1:0];
reg [VAR6-1:0] VAR1;
begin | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/pc_next.v | 4,174 | module MODULE1 (clk, reset, VAR2, VAR8, VAR4,
VAR9, VAR7, VAR3, VAR1,VAR6);
input clk;
input reset;
input [31:2] VAR2;
input VAR8;
input VAR4;
input [25:0] VAR9;
input [ 1:0] VAR7;
output [31:0] VAR3;
output [31:0] VAR1;
output [31:0] VAR6;
reg[31:2] MODULE1;
reg[31:2] VAR10;
wire [31:2] VAR5 = VAR10 + 1;
wire [31:0] V... | mit |
sigilance/tera-computer | src/mux.v | 1,605 | module MODULE1 (VAR1, VAR8, VAR6, VAR4);
output [7:0] VAR1;
input [7:0] VAR8, VAR6;
input VAR4;
assign VAR1 = (VAR4) ? VAR6 : VAR8;
endmodule
module MODULE3 (VAR1, VAR8, VAR6, VAR4);
output [7:0] VAR1;
input [7:0] VAR8, VAR6;
input VAR4;
assign VAR1 = (VAR4) ? (VAR6 + 1) : VAR8;
endmodule
module MODULE2 (VAR7, VAR5, VA... | mit |
mym987/sha256 | verilog/SHA256/sha256_mem.v | 9,188 | module MODULE1(
input wire clk,
input wire VAR11,
input wire [511 : 0] VAR12,
input wire VAR25,
input wire VAR33,
output wire [31 : 0] VAR28
);
parameter VAR8 = 0;
parameter VAR20 = 1;
reg [31 : 0] VAR3 [0 : 15];
reg [31 : 0] VAR23;
reg [31 : 0] VAR5;
reg [31 : 0] VAR31;
reg [31 : 0] VAR18;
reg [31 : 0] VAR24;
reg [31 ... | mit |
monotone-RK/FACE | MCSoC-15/16-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_byte_group_io.v | 19,285 | module MODULE1 #(
parameter VAR146 = 12'b111111111111,
parameter VAR98 = 12'b000000000000,
parameter VAR113 = "VAR47",
parameter VAR44 = "VAR41",
parameter VAR1 = 4,
parameter VAR77 = "VAR76",
parameter VAR162 = 00,
parameter VAR121 = "VAR80",
parameter VAR83 = 12,
parameter VAR132 = "VAR47"
)
(
input [9:0] VAR145,
out... | mit |
everskar2013/PentiumX | Hardware/Code/uart_transceiver.v | 3,871 | module MODULE1(
input VAR18,
input VAR3,
input VAR7,
output reg VAR10,
input [15:0] VAR17,
output reg [7:0] VAR6,
output reg VAR16,
input [7:0] VAR5,
input VAR4,
output reg VAR20,
output reg VAR21,
output reg VAR22
);
reg [15:0] VAR14;
wire VAR15;
assign VAR15 = (VAR14 == 16'd0);
always @(posedge VAR3) begin
if(VAR18)
... | mit |
fallen/milkymist-mmu | cores/pfpu/rtl/pfpu_fmul.v | 2,819 | module MODULE1(
input VAR32,
input VAR35,
input [31:0] VAR11,
input [31:0] VAR16,
input VAR40,
output reg [31:0] VAR33,
output reg VAR6
);
wire VAR31 = VAR11[31];
wire [7:0] VAR22 = VAR11[30:23];
wire [23:0] VAR1 = {1'b1, VAR11[22:0]};
wire VAR26 = VAR16[31];
wire [7:0] VAR27 = VAR16[30:23];
wire [23:0] VAR24 = {1'b1, ... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M8_P4_syn.v | 2,439 | module MODULE1 ( VAR34, VAR101, VAR42 );
input [7:0] VAR34;
input [7:0] VAR101;
output [8:0] VAR42;
wire VAR51, VAR2, VAR68, VAR99, VAR55, VAR21, VAR79, VAR100, VAR28, VAR98, VAR10, VAR4, VAR49, VAR88,
VAR23, VAR83, VAR76, VAR78, VAR72, VAR86, VAR26, VAR61, VAR56, VAR18, VAR29;
VAR97 VAR82 ( .VAR17(VAR101[7]), .VAR37(V... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/ipcore_dir/gsu_fmult.v | 10,130 | module MODULE1 (
clk, VAR110, VAR120, VAR32
);
input clk;
output [31 : 0] VAR110;
input [15 : 0] VAR120;
input [15 : 0] VAR32;
wire \VAR62/VAR53 ;
wire \VAR62/VAR83 ;
wire \VAR62/VAR64 ;
wire \VAR62/VAR54 ;
wire \VAR62/VAR71 ;
wire \VAR62/VAR19 ;
wire \VAR62/VAR96 ;
wire \VAR62/VAR8 ;
wire \VAR62/VAR6 ;
wire \VAR62/VAR... | gpl-2.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/inverse/array_div/div_43/div_43.v | 2,329 | module MODULE1 (
VAR19,
VAR8,
VAR4,
VAR23,
VAR10,
VAR2);
input VAR19;
input VAR8;
input [26:0] VAR4;
input [42:0] VAR23;
output [42:0] VAR10;
output [26:0] VAR2;
wire [26:0] VAR3;
wire [42:0] VAR6;
wire [26:0] VAR2 = VAR3[26:0];
wire [42:0] VAR10 = VAR6[42:0];
VAR12 VAR1 (
.VAR8 (VAR8),
.VAR19 (VAR19),
.VAR4 (VAR4),
.V... | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_us_2/synth/triangle_intersect_auto_us_2.v | 14,604 | module MODULE1 (
VAR1,
VAR32,
VAR78,
VAR51,
VAR8,
VAR7,
VAR44,
VAR42,
VAR95,
VAR76,
VAR86,
VAR46,
VAR85,
VAR14,
VAR22,
VAR4,
VAR27,
VAR10,
VAR50,
VAR53,
VAR2,
VAR15,
VAR72,
VAR23,
VAR30,
VAR56,
VAR39,
VAR88,
VAR61,
VAR75,
VAR49,
VAR26,
VAR66,
VAR55,
VAR80,
VAR33,
VAR67,
VAR71,
VAR25,
VAR54,
VAR93,
VAR38,
VAR36,
VAR37,
... | mit |
asicguy/gplgpu | hdl/crt_sp/crtaddsl.v | 4,170 | module MODULE1
(
VAR8,
VAR2,
VAR3,
VAR9,
VAR4,
VAR14,
VAR20,
VAR19,
VAR12,
VAR10,
VAR1,
VAR15,
VAR13,
VAR17,
VAR16,
VAR6,
VAR11,
VAR5,
VAR21,
VAR18
);
input [13:0] VAR8,
VAR2,
VAR3,
VAR9;
input [11:0] VAR4,
VAR14,
VAR20,
VAR19;
output [13:0] VAR12,
VAR10,
VAR1,
VAR15,
VAR13,
VAR17,
VAR16,
VAR6;
output [11:0] VAR11,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR4,
VAR12,
VAR11 ,
VAR6
);
output VAR9 ;
input VAR2 ;
input VAR4;
input VAR12;
input VAR11 ;
input VAR6 ;
wire VAR10 ;
wire VAR8;
buf VAR1 (VAR10 , VAR2 );
VAR7 VAR3 (VAR8, VAR10, VAR4, VAR12);
buf VAR5 (VAR9 , VAR8 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/master_calib_skip/bsg_comm_link_master_calib_skip_rom.v | 10,432 | module MODULE1 #(parameter VAR7(VAR1), VAR6))
(input [VAR6-1:0] VAR2
,output logic [VAR1-1:0] VAR4
);
VAR5 case(VAR2)
0: VAR4 = VAR1 ' (20'b00010000000011110101); 1: VAR4 = VAR1 ' (20'b00010100000000000001); 2: VAR4 = VAR1 ' (20'b00011100000000001000); 3: VAR4 = VAR1 ' (20'b00100000000000000000); 4: VAR4 = VAR1 ' (20'b... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.behavioral.pp.v | 2,212 | module MODULE1 (
VAR14 ,
VAR4 ,
VAR1 ,
VAR20 ,
VAR6 ,
VAR8 ,
VAR10,
VAR13,
VAR2 ,
VAR9
);
output VAR14 ;
input VAR4 ;
input VAR1 ;
input VAR20 ;
input VAR6 ;
input VAR8 ;
input VAR10;
input VAR13;
input VAR2 ;
input VAR9 ;
wire VAR3 ;
wire VAR17 ;
wire VAR19 ;
wire VAR18;
or VAR15 (VAR3 , VAR6, VAR20 );
or VAR16 (VAR17... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/ddc.v | 2,745 | module MODULE1(input VAR11,
input reset,
input enable,
input [3:0] VAR30,
input [3:0] VAR32,
output VAR5,
input [31:0] VAR22,
input [15:0] VAR13,
input [15:0] VAR4,
output [15:0] VAR23,
output [15:0] VAR15
);
parameter VAR36 = 16;
parameter VAR1 = 16;
wire [15:0] VAR26, VAR41;
wire [31:0] VAR27;
wire VAR21, VAR2;
reg [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3_1.v | 2,199 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR6,
VAR9,
VAR4 ,
VAR1
);
output VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR6;
input VAR9;
input VAR4 ;
input VAR1 ;
VAR2 VAR8 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
HarmonInstruments/verilog | primitives/sync_pulse.v | 1,252 | module MODULE1(input VAR6, VAR5, VAR2, output reg VAR3=0);
reg VAR9 = 0;
always @ (posedge VAR6)
VAR9 <= VAR5 ^ VAR9;
wire VAR4;
sync VAR8(.VAR7(VAR2), .VAR5(VAR9), .VAR3(VAR4));
reg VAR1 = 0;
always @ (posedge VAR2)
begin
VAR1 <= VAR4;
VAR3 <= VAR4 ^ VAR1;
end
endmodule | gpl-3.0 |
horia141/bachelor-thesis | prj/applications/Auto2/Auto2.v | 1,879 | module MODULE1(VAR33,VAR10,reset,VAR39,VAR18,VAR7,VAR6,VAR21,VAR1);
input wire VAR33;
input wire VAR10;
input wire reset;
output wire [7:0] VAR39;
output wire VAR18;
output wire VAR7;
output wire VAR6;
output wire VAR21;
output wire VAR1;
wire [7:0] VAR5;
wire [11:0] VAR36;
wire [7:0] VAR37;
wire [19:0] VAR15;
wire [40... | mit |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Master_Clock_Divider/Master_Clock_Divider.v | 4,313 | module MODULE1
(
output VAR6,
output VAR3,
output VAR8,
input reset,
output VAR4,
input VAR2,
input VAR7
);
VAR5 VAR1
(
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.reset(reset),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.functional.pp.v | 1,843 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR12,
VAR11 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR14 ;
input VAR12;
input VAR11 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR8 ;
wire VAR10 ;
wire VAR15;
wire VAR3 ;
VAR1 VAR7 VAR13 (VAR10 , VAR14, VAR12, , VAR11, VAR5, VAR9);
buf VAR4 (VAR2 , VAR10 );
endmodule | apache-2.0 |
dingzh/piplined-MIPS-CPU | src/LAB5/Alu.v | 1,411 | module MODULE1(
input [31:0] VAR1,
input [31:0] VAR4,
input [3:0] VAR5,
output reg VAR2,
output reg [31:0] VAR3
);
always @(VAR1 or VAR4 or VAR5)
begin
case(VAR5)
'b0000: begin
VAR3 = VAR1 & VAR4;
VAR2 = 0;
end
'b0001: begin
VAR3 = VAR1 | VAR4;
VAR2 = 0;
end
'b0010: begin
VAR3 = VAR1 + VAR4;
VAR2 = 0;
end
'b0110: begin... | gpl-3.0 |
daphil19/CMSC411-Project | cordic_alog.v | 2,022 | module MODULE1();
reg [31:0] VAR11, VAR1, VAR9;
reg real VAR7 [0:15];
reg real VAR3 [0:16];
reg real VAR4, VAR8, VAR5;
integer VAR6;
reg real VAR10, VAR2; | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_reset_synchronizer.v | 4,426 | module MODULE1
parameter VAR6 = 1,
parameter VAR4 = 2
)
(
input VAR2 ,
input clk,
output VAR5
);
reg [VAR4-1:0] VAR3;
reg VAR1;
generate if (VAR6) begin
always @(posedge clk or posedge VAR2) begin
if (VAR2) begin
VAR3 <= {VAR4{1'b1}};
VAR1 <= 1'b1;
end
else begin
VAR3[VAR4-2:0] <= VAR3[VAR4-1:1];
VAR3[VAR4-1] <= 0;
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.v | 2,469 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR12 ,
VAR9 ,
VAR11 ,
VAR10 ,
VAR2,
VAR7,
VAR1 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR12 ;
input VAR9 ;
input VAR11 ;
input VAR10 ;
input VAR2;
input VAR7;
input VAR1 ;
input VAR4 ;
VAR3 VAR6 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR10(VAR10),
.VA... | apache-2.0 |
ByronPhung/hardware-accelerated-dna-matching-and-variation-detection | Hardware/Verilog/Search_8Comparators_tf.v | 2,438 | module MODULE1;
reg VAR2;
reg reset;
reg [1023:0] VAR3;
reg [63:0] VAR4;
wire VAR6;
VAR5 VAR1 (
.VAR2(VAR2),
.reset(reset),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
); | apache-2.0 |
cliffordwolf/yosys | techlibs/gowin/cells_map.v | 6,100 | module \VAR34 (input VAR64, VAR8, output VAR78);
VAR34 VAR74 (.VAR64(VAR64), .VAR78(VAR78), .VAR15(VAR8));
wire VAR55 = 1;
endmodule
module \VAR33 (input VAR64, VAR8, output VAR78);
VAR10 VAR74 (.VAR64(VAR64), .VAR78(VAR78), .VAR15(VAR8));
wire VAR55 = 1;
endmodule
module \VAR76 (input VAR64, VAR8, VAR20, output VAR78)... | isc |
m13253/riscade | hdl/src/step_id.v | 1,132 | module MODULE1(VAR14, VAR12, VAR8,
VAR3, VAR4, VAR1, VAR6, VAR9, VAR2, VAR10, VAR7, VAR15, VAR16, VAR5);
input[7:0] VAR14;
input VAR12;
input VAR8;
output VAR3, VAR4, VAR1, VAR6, VAR9, VAR2, VAR10, VAR7, VAR15, VAR16, VAR5;
wire VAR11 = VAR14[7] ^ VAR8;
wire[6:0] VAR13 = VAR14[6:0] & {7{~(VAR11 | VAR12)}};
assign VAR3 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR1 ,
input VAR4 ,
input VAR7,
input VAR5 ,
input VAR3
);
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_pcie_bram_top_7x.v | 8,590 | module MODULE1
parameter VAR5 = "VAR23", parameter VAR28 = 0, parameter [3:0] VAR18 = 4'h1, parameter [5:0] VAR12 = 6'h08,
parameter VAR7 = 31, parameter VAR15 = 24, parameter VAR35 = 1, parameter VAR33 = 2, parameter VAR1 = 1,
parameter VAR30 = 'h1FFF, parameter VAR10 = 1, parameter VAR14 = 2, parameter VAR9 = 1 )
(
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf.pp.symbol.v | 1,240 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR4 ,
input VAR6,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp_2.v | 2,695 | module MODULE2 (
VAR8 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR7,
VAR9 ,
VAR13 ,
VAR6 ,
VAR12
);
output VAR8 ;
output VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR7;
input VAR9 ;
input VAR13 ;
input VAR6 ;
input VAR12 ;
VAR4 VAR2 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VA... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/IDDR2.v | 4,605 | module MODULE1 (VAR22, VAR6, VAR21, VAR13, VAR3, VAR7, VAR17, VAR14);
output VAR22;
output VAR6;
input VAR21;
input VAR13;
input VAR3;
input VAR7;
tri0 VAR20 = VAR1.VAR20;
input VAR17;
input VAR14;
parameter VAR23 = "VAR15";
parameter VAR5 = 1'b0;
parameter VAR19 = 1'b0;
parameter VAR18 = "VAR4";
reg VAR9, VAR10;
reg V... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/bin_cam/src/erase_keys.v | 10,186 | module MODULE1 (
reset,
VAR10,
VAR14,
VAR27,
VAR26,
VAR7,
VAR35,
VAR1,
VAR11,
VAR16
);
parameter VAR19 = "VAR38 VAR29";
parameter VAR33 = 8;
parameter VAR31 = 416;
localparam VAR37 = VAR18(VAR31); localparam VAR13 = 2**VAR37;
input reset;
input VAR10, VAR14;
input [VAR33-1:0] VAR27;
input [VAR37-1:0] VAR26;
input VAR7;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.pp.symbol.v | 1,359 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR1 ,
input VAR9 ,
output VAR8 ,
input VAR4 ,
input VAR7,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_1_cycles/integracion_fisica/front_end/source/RecursiveKOA_1c.v | 5,738 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR17,
input wire [VAR35-1:0] VAR5,
input wire [VAR35-1:0] VAR31,
output wire [2*VAR35-1:0] VAR12
);
wire [1:0] VAR18;
wire [3:0] VAR25;
assign VAR18 = 2'b00;
assign VAR25 = 4'b0000;
wire [VAR35/2-1:0] VAR23;
wire [VAR35/2:0] VAR1;
wire [VAR35/2-3:0] VAR21;
wi... | gpl-3.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkGPR_RegFile.v | 7,872 | module MODULE1(VAR13,
VAR39,
VAR35,
VAR29,
VAR28,
VAR32,
VAR5,
VAR73,
VAR59,
VAR63,
VAR54,
VAR74,
VAR44,
VAR64,
VAR51);
input VAR13;
input VAR39;
input VAR35;
output VAR29;
input VAR28;
output VAR32;
input [4 : 0] VAR5;
output [63 : 0] VAR73;
input [4 : 0] VAR59;
output [63 : 0] VAR63;
input [4 : 0] VAR54;
output [63 :... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.behavioral.pp.v | 1,872 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR8,
VAR11,
VAR5,
VAR2 ,
VAR10
);
output VAR9 ;
input VAR7 ;
input VAR8;
input VAR11;
input VAR5;
input VAR2 ;
input VAR10 ;
wire VAR12 ;
wire VAR13;
VAR6 VAR4 (VAR12 , VAR7, VAR11, VAR5 );
VAR6 VAR1 (VAR13, VAR8, VAR11, VAR5 );
notif0 VAR3 (VAR9 , VAR12, VAR13);
endmodule | apache-2.0 |
ElegantLin/My-CPU | Snake/Snake.srcs/sources_1/new/VGA_top.v | 1,041 | module MODULE1(
input clk,
input rst,
input [1:0]VAR9,
input [5:0]VAR11,
input [4:0]VAR7,
output [9:0]VAR4,
output [9:0]VAR5,
output VAR1,
output VAR6,
output [11:0] VAR8
);
wire VAR2;
VAR12 VAR10(
.clk(clk),
.rst(rst),
.VAR2(VAR2)
);
VAR13 VAR3
(
.clk(VAR2),
.rst(rst),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8... | gpl-3.0 |
Tommydag/CAN-Bus-Controller | shift_reg.v | 1,867 | module MODULE1(
input VAR5,
output reg[(VAR7-1):0] VAR11,
output reg VAR2,
input rst,
input VAR6
);
parameter VAR7 = 150;
VAR1 VAR2 = 0;
parameter VAR13 = 2'b00, VAR10 = 2'b01, VAR9 = 2'b10, VAR4 = 2'b11;
reg[1:0] VAR12, VAR8;
reg [(VAR7-1):0] VAR3 = {VAR7{1'b1}};
always @(posedge VAR6 or posedge rst) begin
if(rst) beg... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_p_src_cols_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR25,
VAR23,
VAR10,
VAR20);
parameter VAR1 = 32'd12;
parameter VAR8 = 32'd2;
parameter VAR6 = 32'd3;
input clk;
input [VAR1-1:0] VAR25;
input VAR23;
input [VAR8-1:0] VAR10;
output [VAR1-1:0] VAR20;
reg[VAR1-1:0] VAR17 [0:VAR6-1];
integer VAR22;
always @ (posedge clk)
begin
if (VAR23)
begin
for (V... | gpl-3.0 |
SymbiFlow/yosys | techlibs/ice40/arith_map.v | 2,170 | module MODULE1(
module 80ice40alu (VAR15, VAR17, VAR26, VAR22, VAR19, VAR5, VAR11);
parameter VAR3 = 0;
parameter VAR25 = 0;
parameter VAR30 = 1;
parameter VAR14 = 1;
parameter VAR7 = 1;
input [VAR30-1:0] VAR15;
input [VAR14-1:0] VAR17;
output [VAR7-1:0] VAR19, VAR5;
input VAR26, VAR22;
output [VAR7-1:0] VAR11;
wire VA... | isc |
archlabo/Frix | common/bios_loader.v | 5,406 | module MODULE1 (
input wire clk,
input wire rst,
output reg [27:0] address,
output reg [3:0] VAR6,
output reg write,
output reg [31:0] VAR5,
output reg read,
input wire [31:0] VAR1,
input wire VAR4
);
parameter VAR11 = 32'h00008860;
parameter VAR2 = 32'h00000000;
parameter VAR10 = 72;
parameter VAR7 = (64*1024);
parame... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.symbol.v | 1,333 | module MODULE1 (
input VAR7,
input VAR6,
input VAR3 ,
input VAR2 ,
output VAR9
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ip_top/memc_ui_top.v | 33,295 | module MODULE1 #
(
parameter VAR218 = 200,
parameter VAR128 = "VAR199",
parameter VAR100 = "VAR98",
parameter VAR193 = 2,
parameter VAR117 = "VAR153",
parameter VAR176 = 1,
parameter VAR59 = 6,
parameter VAR62 = 3,
parameter VAR52 = 1,
parameter VAR116 = 3,
parameter VAR112 = 1,
parameter VAR215 = 1,
parameter VAR76 = ... | lgpl-3.0 |
hanw/sonic-lite | p4/bsv/AsymmetricBRAM/AsymmetricBRAM_Altera.v | 7,699 | module MODULE1(
VAR65,
VAR37,
VAR11,
VAR16,
VAR60,
VAR46,
VAR40
);
parameter VAR43 = 'VAR39 0;
parameter VAR58 = 'VAR39 0;
parameter VAR20 = 'VAR39 0;
parameter VAR35 = 'VAR39 0;
parameter VAR64 = 'VAR39 0;
parameter VAR69 = 'VAR39 0;
parameter VAR6 = 'VAR39 1;
parameter VAR12 = (VAR43 == 0) ? "VAR31":"VAR53";
input VA... | mit |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/ffs_map.v | 13,199 | module \VAR15 (VAR54, VAR12, VAR71);
input VAR54;
input VAR12;
output VAR71;
VAR59 VAR3 (.VAR71(VAR71), .VAR54(VAR54), .VAR12(VAR12), .VAR23(1'b1), .VAR50(1'b1), .VAR78(1'b1));
endmodule
module \VAR1 (VAR54, VAR12, VAR50, VAR71);
input VAR54;
input VAR12;
input VAR50;
output VAR71;
VAR59 VAR3 (.VAR71(VAR71), .VAR54(VAR... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_lvds_out.v | 5,200 | module MODULE1 (
VAR45,
VAR36,
VAR5,
VAR38,
VAR15,
VAR49,
VAR67,
VAR22,
VAR21,
VAR28,
VAR19,
VAR46);
parameter VAR16 = 0;
parameter VAR64 = 0;
parameter VAR60 = 0;
parameter VAR50 = "VAR9";
localparam VAR66 = 0;
localparam VAR59 = 1;
input VAR45;
input VAR36;
input VAR5;
output VAR38;
output VAR15;
input VAR49;
input V... | gpl-3.0 |
marmolejo/zet | cores/zet/rtl/zet_addsub.v | 1,975 | module MODULE1 (
input [15:0] VAR9,
input [15:0] VAR16,
output [15:0] out,
input [ 2:0] VAR19,
input VAR7,
input VAR1,
output VAR14,
output VAR10,
output VAR3
);
wire [15:0] VAR17;
wire VAR4;
wire VAR2;
wire VAR8, VAR12, VAR15;
VAR13 VAR5 ( .VAR9 (VAR9), .VAR16 (VAR17),
.VAR4 (VAR4),
.VAR18 (VAR2),
.VAR6 (out),
.VAR11 ... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_sys_description_rom.v | 3,685 | module MODULE1 (
address,
VAR4,
VAR33,
clk,
VAR22,
VAR7,
reset,
VAR18,
write,
VAR36,
VAR35
)
;
parameter VAR19 = "VAR1.VAR29";
output [ 63: 0] VAR35;
input [ 8: 0] address;
input [ 7: 0] VAR4;
input VAR33;
input clk;
input VAR22;
input VAR7;
input reset;
input VAR18;
input write;
input [ 63: 0] VAR36;
wire VAR8;
reg [ ... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v | 23,161 | module MODULE2 (
clk,
reset,
VAR131,
VAR182,
VAR20,
VAR156,
VAR12
);
parameter VAR71 = 18;
parameter VAR195 = 33;
parameter VAR186 = 17;
localparam VAR67 = 34;
input clk;
input reset;
input VAR131;
input VAR182;
input [VAR71-1:0] VAR20; output VAR156;
output [VAR71-1:0] VAR12;
localparam VAR70 = 18; localparam VAR94 = ... | mit |
asicguy/gplgpu | hdl/dlp/dlp_reg.v | 12,669 | module MODULE1
(
input VAR10,
input VAR15,
input VAR14, input [8:2] VAR44,
input VAR13,
input [3:0] VAR31,
input VAR6,
input [31:0] VAR22,
input [8:2] VAR42,
input VAR5,
input [3:0] VAR51,
input VAR39,
input [31:0] VAR36,
input VAR28,
input VAR49,
input VAR41,
input VAR7, input [3:0] VAR4,
output reg [27:0] VAR9,
outpu... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_104.v | 1,466 | module MODULE2 (
VAR5,
VAR9
);
input [31:0] VAR5;
output [31:0]
VAR9;
wire [31:0]
VAR12,
VAR3,
VAR1,
VAR8,
VAR6,
VAR4,
VAR10,
VAR2;
assign VAR12 = VAR5;
assign VAR2 = VAR10 << 3;
assign VAR4 = VAR6 << 5;
assign VAR10 = VAR6 + VAR4;
assign VAR1 = VAR3 - VAR12;
assign VAR3 = VAR12 << 2;
assign VAR8 = VAR1 << 4;
assign VA... | mit |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_fmul_32ns_32ns_32_4_max_dsp.v | 1,909 | module MODULE1
VAR22 = 1,
VAR21 = 4,
VAR13 = 32,
VAR2 = 32,
VAR23 = 32
)(
input wire clk,
input wire reset,
input wire VAR24,
input wire [VAR13-1:0] VAR15,
input wire [VAR2-1:0] VAR6,
output wire [VAR23-1:0] dout
);
wire VAR17;
wire VAR20;
wire VAR25;
wire [31:0] VAR18;
wire VAR4;
wire [31:0] VAR5;
wire VAR10;
wire [31... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_unmanaged.v | 2,204 | module MODULE1
, parameter VAR15(VAR9)
, parameter VAR15(VAR23)
, parameter VAR25 = VAR4(VAR19,1)
)
(input VAR10
, input VAR2
, input [VAR25-1:0] VAR7
, input VAR27
, input [VAR9-1:0] VAR3
, input [VAR23-1:0] VAR22
, output [VAR25-1:0] VAR17
, input VAR5
, input [VAR9-1:0] VAR8
, output logic [VAR23-1:0] VAR11
, output... | bsd-3-clause |
lvd2/ngs | fpga/pgmflash/zxbus/zxbus.v | 4,603 | module MODULE1
(
input wire clk,
input wire VAR15,
inout wire [7:0] VAR26, input wire [7:0] VAR18, input wire VAR28,
input wire VAR37,
input wire VAR6,
input wire VAR33,
output wire VAR36, output reg VAR4, output reg VAR1,
output reg VAR31, input wire VAR27,
output reg VAR16,
output reg VAR38,
output reg VAR12, output ... | gpl-3.0 |
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