repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/LOAGDA_St_N16_M4_P4_syn.v | 3,424 | module MODULE1 ( VAR48, VAR15, VAR30 );
input [15:0] VAR48;
input [15:0] VAR15;
output [16:0] VAR30;
wire VAR49, VAR94, VAR95, VAR104, VAR7,
VAR13, VAR12, VAR42, VAR88, VAR100, VAR60, VAR52, VAR53,
VAR22, VAR91, VAR89, VAR70, VAR41, VAR17, VAR72, VAR67, VAR21, VAR20, VAR19, VAR78, VAR24, VAR92;
VAR96 VAR55 ( .VAR51(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo_4.v | 2,318 | module MODULE2 (
VAR10 ,
VAR1 ,
VAR5 ,
VAR4,
VAR6,
VAR8,
VAR9 ,
VAR3
);
output VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR8;
input VAR9 ;
input VAR3 ;
VAR7 VAR2 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2 ... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_reg_srl_fifo.v | 9,777 | module MODULE1 #
(
parameter VAR45 = "none", parameter integer VAR43 = 1, parameter integer VAR40 = 33, parameter integer VAR12 = 2, parameter VAR19 = 1 )
(
input wire VAR27, input wire VAR18, input wire [VAR43-1:0] VAR22, input wire VAR17, output wire VAR32, output wire [VAR43-1:0] VAR37, output wire VAR16, input wire... | gpl-3.0 |
fpgaminer/fpgaminer-vanitygen | cores/vanitygen-serial/ripemd160.v | 8,492 | module MODULE3 (
input clk,
input VAR38,
input [255:0] VAR32,
output reg VAR24 = 1'b0,
output reg [159:0] VAR45 = 160'd0
);
reg [511:0] VAR9;
reg [31:0] VAR10, VAR30, VAR17, VAR20, VAR50, VAR2, VAR6, VAR46, VAR14, VAR26;
reg [6:0] VAR12;
wire [31:0] VAR21, VAR15;
MODULE4 MODULE1 (
.clk (clk),
.VAR33 (VAR38 ? 7'd0 : VAR... | gpl-3.0 |
dk00/old-stuff | csie/09computer-architecture/project/code/CPU.v | 4,912 | module MODULE1(clk,rst,VAR38,
VAR2,VAR85,VAR97,VAR138,VAR51,VAR23);
input clk,rst,VAR38,VAR85;
input [255:0] VAR2;
output VAR51,VAR23;
output [255:0] VAR97;
output [31:0] VAR138;
wire [31:0] VAR106,VAR77,VAR83,VAR117;
VAR115 VAR110(
.VAR63 (VAR106),
.VAR4 (4),
.VAR109 (VAR83)
);
wire VAR74;
VAR52 VAR52(
.clk (clk),
.rs... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.blackbox.v | 1,226 | module MODULE1 (
VAR5,
VAR1 ,
VAR4
);
input VAR5;
input VAR1 ;
output VAR4 ;
supply1 VAR3;
supply0 VAR2;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/V2DatapathClockConverter32.v | 11,008 | module MODULE1
(
)
(
VAR76 ,
VAR67 ,
VAR74 ,
VAR25 ,
VAR13 ,
VAR29 ,
VAR45 ,
VAR28 ,
VAR92 ,
VAR37 ,
VAR90 ,
VAR77 ,
VAR89 ,
VAR62 ,
VAR49 ,
VAR12 ,
VAR72 ,
VAR55 ,
VAR73 ,
VAR54 ,
VAR65 ,
VAR18 ,
VAR41 ,
VAR9 ,
VAR52 ,
VAR34 ,
VAR6 ,
VAR3 ,
VAR81 ,
VAR44 ,
VAR39 ,
VAR78 ,
VAR19 ,
VAR71 ,
VAR59 ,
VAR91 ,
VAR38 ,
VAR58 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr.pp.symbol.v | 1,264 | module MODULE1 (
input VAR2,
input VAR1 ,
input VAR4 ,
input VAR3 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.pp.symbol.v | 1,394 | module MODULE1 (
input VAR7 ,
output VAR8 ,
input VAR6,
input VAR3 ,
input VAR5 ,
input VAR2 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankP4.v | 5,541 | module MODULE1(VAR20,reset,VAR25,VAR3,VAR15,VAR10,VAR2,VAR29);
input wire VAR20;
input wire reset;
input wire [11:0] VAR25;
input wire VAR3;
output wire [7:0] VAR15;
output wire [7:0] VAR10;
output wire [7:0] VAR2;
output wire [7:0] VAR29;
reg [1:0] VAR19;
reg [7:0] VAR13;
reg [7:0] VAR30;
reg [7:0] VAR6;
reg [7:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.pp.blackbox.v | 1,288 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR4,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR3;
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/uart16550/rtl/verilog/uart_rfifo.v | 11,181 | module MODULE1 (clk,
VAR45, VAR32, VAR33,
VAR38, VAR6, VAR17,
VAR22,
VAR40,
VAR31,
VAR3
);
parameter VAR18 = VAR14;
parameter VAR2 = VAR24;
parameter VAR44 = VAR12;
parameter VAR41 = VAR21;
input clk;
input VAR45;
input VAR38;
input VAR6;
input [VAR18-1:0] VAR32;
input VAR31;
input VAR3;
output [VAR18-1:0] VAR33;
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp.symbol.v | 1,257 | module MODULE1 (
input VAR3,
output VAR6
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/Coprocesador_CORDIC.v | 10,028 | module MODULE1#(parameter VAR24 = 32, parameter VAR21=8, parameter VAR132=23, parameter VAR80=5, parameter VAR10 = 8,
parameter VAR41 = 23, parameter VAR61 = 9) (
input wire [31:0] VAR9,
input wire VAR65, input wire VAR115, input wire VAR120, input wire [1:0] VAR62, input wire VAR45, input wire VAR126, input wire VAR14... | gpl-3.0 |
merckhung/zet | cores/timer/rtl/timer_counter.v | 7,475 | module MODULE1(
input [1:0] VAR6, input [5:0] VAR14, input [15:0] VAR32, input VAR10, input rst, input VAR22, input VAR30, input VAR17, input [7:0] VAR18, output reg [7:0] VAR24, input VAR7, input VAR2, output out );
localparam
VAR34 = 2'd0,
VAR4 = 2'd1,
VAR39 = 2'd2;
reg [15:0] VAR12; reg [15:0] VAR5; reg [5:0] VAR9; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp.functional.v | 1,648 | module MODULE1 (
VAR5,
VAR10,
VAR9 ,
VAR12 ,
VAR11 ,
VAR8
);
input VAR5;
input VAR10;
output VAR9 ;
output VAR12 ;
input VAR11 ;
input VAR8 ;
wire VAR6;
VAR1 VAR4 VAR3 (VAR6 , VAR8, VAR11, VAR5, VAR10);
buf VAR2 (VAR9 , VAR6 );
not VAR7 (VAR12 , VAR6 );
endmodule | apache-2.0 |
SteffenReith/J1Sc | src/main/verilog/arch/Nexys4/Board_Nexys4.v | 3,440 | module MODULE1 (VAR13,
VAR34,
VAR25,
VAR14,
VAR20,
VAR6,
VAR19,
VAR35,
VAR16,
VAR2,
VAR27,
VAR33,
VAR1,
VAR17,
VAR32,
VAR10,
VAR24,
VAR36,
VAR31,
VAR4,
VAR28,
VAR30,
VAR29);
input VAR13;
input VAR34;
input [0:0] VAR25;
input [15:0] VAR10;
input [4:0] VAR24;
input VAR36;
input VAR31;
input VAR4;
input VAR30;
output [15:... | bsd-3-clause |
MeshSr/onetswitch45 | ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/udp/user_data_path.v | 14,174 | module MODULE1
parameter VAR101=VAR15/8,
parameter VAR137 = 2,
parameter VAR102 = 8,
parameter VAR146 = 8
)
(
input [VAR15-1:0] VAR128,
input [VAR101-1:0] VAR21,
input VAR79,
output VAR33,
input [VAR15-1:0] VAR100,
input [VAR101-1:0] VAR116,
input VAR118,
output VAR140,
input [VAR15-1:0] VAR20,
input [VAR101-1:0] VAR13... | lgpl-2.1 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_uart_0.v | 26,742 | module MODULE4 (
VAR53,
VAR71,
clk,
VAR56,
VAR2,
VAR45,
VAR70,
VAR43,
VAR10,
VAR15,
VAR88,
VAR66,
VAR29
)
;
output VAR15;
output VAR88;
output VAR66;
output VAR29;
input [ 9: 0] VAR53;
input VAR71;
input clk;
input VAR56;
input VAR2;
input VAR45;
input VAR70;
input [ 7: 0] VAR43;
input VAR10;
reg VAR64;
reg [ 9: 0] VAR... | gpl-3.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light_rx_ctrl.v | 4,856 | module MODULE1
parameter VAR17 = 3,
parameter VAR16 = 3'b001,
parameter VAR7 = 3'b010,
parameter VAR4 = 3'b100
)(
input wire reset,
input wire VAR9,
input wire VAR8,
output wire VAR20,
output wire VAR23,
input wire VAR18,
input wire VAR6,
input wire VAR10,
input wire VAR1,
output reg VAR13,
output reg VAR2,
output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.symbol.v | 1,517 | module MODULE1 (
input VAR10 ,
output VAR5 ,
output VAR4,
input VAR7 ,
input VAR1,
input VAR8,
input VAR11
);
supply1 VAR9;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_shiftreg.v | 6,850 | module MODULE1(VAR11, VAR13, VAR6, VAR9, VAR12, VAR7, VAR15, VAR2, VAR8,
VAR14, VAR3, VAR1, VAR4);
parameter VAR5=1;
input VAR11; input VAR13; input VAR6; input VAR9; input [4:0] VAR12; input [4:0] VAR7; input [15:0]VAR15; input VAR2; input [3:0] VAR8; input [1:0] VAR14;
output VAR3; output[15:0]VAR1; output VAR4;
reg ... | gpl-2.0 |
jotego/jt12 | hdl/jt12.v | 2,731 | module MODULE1 (
input rst, input clk, input VAR8, input [7:0] din,
input [1:0] addr,
input VAR10,
input VAR7,
output [7:0] dout,
output VAR5,
input VAR20,
output signed [15:0] VAR17,
output signed [15:0] VAR6,
output VAR4
);
VAR19 VAR1(
.rst ( rst ), .clk ( clk ), .VAR8 ( VAR8 ), .din ( din ),
.addr ( addr ),
.VAR10 (... | gpl-3.0 |
aap/pdp6 | verilog/dis340.v | 13,502 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR9,
input wire VAR56,
input wire VAR42,
input wire VAR16,
input wire VAR20,
input wire VAR22,
input wire VAR76,
input wire VAR70,
input wire VAR43, input wire [3:9] VAR30,
input wire [0:35] VAR17,
output wire [1:7] VAR68,
output wire [0:35] VAR5,
output wir... | mit |
marqs85/ossc | rtl/char_array.v | 9,497 | module MODULE1 (
VAR23,
VAR11,
VAR57,
VAR51,
VAR58,
VAR41,
VAR1,
VAR24);
input [3:0] VAR23;
input [31:0] VAR11;
input [9:0] VAR57;
input VAR51;
input [7:0] VAR58;
input VAR41;
input VAR1;
output [7:0] VAR24;
tri1 [3:0] VAR23;
tri1 VAR41;
tri0 VAR1;
wire [7:0] VAR35;
wire [7:0] VAR24 = VAR35[7:0];
VAR49 VAR19 (
.VAR40 (... | gpl-3.0 |
whitef0x0/EECE353-Lab4 | vga_controller.v | 8,213 | module MODULE1( VAR42, VAR26, VAR34, VAR23,
VAR21, VAR2, VAR12,
VAR29, VAR38, VAR27,
VAR36, VAR39);
parameter VAR35 = 1;
parameter VAR6 = "VAR20";
parameter VAR13 = "320x240";
parameter VAR28 = "VAR20";
parameter VAR40 = 11'd480;
parameter VAR4 = 11'd493;
parameter VAR32 = 11'd494; parameter VAR3 = 11'd525;
parameter V... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/localram.v | 52,818 | module MODULE1(clk, addr, VAR73, VAR2, VAR31, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR73;
output [31:0] VAR2;
input [3:0] VAR31;
input en;
input reset;
VAR60 VAR48(
.VAR79 (VAR2[3:0]),
.VAR35 (addr[13:2]),
.VAR14 (clk),
.VAR1 (VAR73[3:0]),
.VAR22 (en),
.VAR17 (reset),
.VAR26 (VAR31[0])
);
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.pp.blackbox.v | 1,344 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR2,
VAR6,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR2;
input VAR6;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp.functional.pp.v | 2,360 | module MODULE1 (
VAR18 ,
VAR7 ,
VAR6 ,
VAR8 ,
VAR4 ,
VAR9 ,
VAR22,
VAR14 ,
VAR5 ,
VAR11 ,
VAR20
);
output VAR18 ;
output VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR4 ;
input VAR9 ;
input VAR22;
input VAR14 ;
input VAR5 ;
input VAR11 ;
input VAR20 ;
wire VAR3 ;
wire VAR13 ;
wire VAR2;
not VAR1 (VAR13 , VAR22 );
VAR15 VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/iodelay_ctrl_eco20100428.v | 7,588 | module MODULE1 #
(
parameter VAR11 = 100, parameter VAR21 = "VAR1", parameter VAR14 = "VAR9", parameter VAR22 = 1 )
(
input VAR20,
input VAR15,
input VAR12,
input VAR13,
output VAR2
);
localparam VAR18 = 15;
wire VAR16;
wire VAR10;
wire VAR23;
reg [VAR18-1:0] VAR6 ;
wire VAR19;
wire VAR4;
assign VAR4 = VAR22 ? ~VAR13: ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.symbol.v | 1,261 | module MODULE1 (
input VAR4,
input VAR2,
output VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/ime/ime_systolic_array.v | 72,484 | module MODULE1 (
clk ,
VAR10 ,
VAR32 ,
VAR3 ,
VAR15 ,
VAR2 ,
VAR24 ,
VAR18 ,
VAR4 ,
VAR16 ,
VAR6 ,
VAR35 ,
VAR34 ,
VAR12 ,
VAR1 ,
VAR30 ,
VAR28 ,
VAR26 ,
VAR29 ,
VAR17
);
input clk ;
input VAR10 ;
input VAR32 ;
input [VAR7*64-1 : 0] VAR3 ;
output [VAR7*64-1 : 0] VAR15 ;
output [VAR7*64-1 : 0] VAR2 ;
output [VAR7*64-1 :... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/utils/ddr_des.v | 1,327 | module MODULE1
parameter VAR13 = 4
)(
input wire VAR1,
input wire VAR15,
input wire VAR6,
input wire VAR10,
output reg [VAR13*4-1:0] VAR11,
output wire [1:0] VAR9
);
wire [1:0] VAR22;
VAR7 VAR2 (
.VAR21(VAR22[1]), .VAR20(VAR22[0]), .VAR4(VAR1), .VAR14(1'b1), .VAR8(VAR10), .VAR3(1'b0), .VAR18(1'b0) );
assign VAR9 = VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.pp.blackbox.v | 1,233 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3,
VAR6,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.pp.blackbox.v | 1,213 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR5;
input VAR3;
endmodule | apache-2.0 |
samyk/proxmark3 | fpga/lf_edge_detect.v | 2,783 | module MODULE1(input clk, input [7:0] VAR6, input [7:0] VAR15,
output [7:0] VAR1, output [7:0] VAR8,
output [7:0] VAR17, output [7:0] VAR13,
output [7:0] VAR10, output [7:0] VAR4,
output VAR16, output VAR14);
VAR2 VAR11(clk, VAR6, VAR15, VAR8, VAR1);
assign VAR17 = (VAR1 + VAR8) / 2 + (VAR1 - VAR8) / 4;
assign VAR13 = ... | gpl-2.0 |
borti4938/n64rgb | generalRGBmod/firmware/rtl/n64rgbv2_top.v | 4,337 | module MODULE1 (
VAR30,
VAR20,
VAR3,
VAR44,
VAR18,
VAR43,
VAR29,
VAR37,
VAR38,
VAR28,
VAR17,
VAR8,
VAR25,
VAR7,
VAR19, VAR11, VAR39,
VAR2,
VAR48,
VAR13,
VAR40
);
input VAR30;
input VAR20;
input [VAR9-1:0] VAR3;
inout VAR44;
input VAR18;
input VAR43;
input VAR29;
input VAR37;
input VAR38;
input VAR28;
output reg VAR17;
... | gpl-3.0 |
bangonkali/quartus-sockit | top/c5sx_soc.v | 27,155 | module MODULE1(
output wire [14:0] VAR116, output wire [2:0] VAR25, output wire VAR84, output wire VAR17, output wire VAR129, output wire VAR59, output wire VAR2, output wire VAR93, output wire VAR127, output wire VAR15, inout wire [31:0] VAR9, inout wire [3:0] VAR170, inout wire [3:0] VAR136, output wire VAR164, outpu... | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_rxcounters.v | 2,307 | module MODULE1
(
VAR18, VAR21, VAR1, VAR5,
VAR8, VAR16, VAR14, VAR11, VAR17,
VAR10, VAR3, VAR6, VAR9, VAR7, VAR2
);
input VAR18;
input VAR21;
input VAR1;
input VAR5;
input VAR8;
input VAR16;
input VAR14;
input [1:0] VAR11;
input VAR17;
input VAR10;
output VAR3; output [15:0] VAR6; output [7: 0] VAR9;
output [3: 0] VAR7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai_4.v | 2,208 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR6,
VAR8
);
output VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR8;
VAR5 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2 ,
VAR3,
VAR7,
VAR1,
VAR4
);... | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_fast_imul.v | 2,309 | module MODULE1(
clk,
VAR9,
VAR8,
VAR1,
VAR10,
VAR7,
ready,
VAR5
);
input wire clk;
input wire VAR9;
input wire [VAR2-1:0] VAR8;
input wire [VAR2-1:0] VAR1;
input wire VAR10;
input wire VAR7;
output wire ready;
output wire [2*VAR2-1:0] VAR5;
assign ready = 1'b1;
assign VAR5 = (VAR7 && (VAR8[VAR2-1] ^ VAR1[VAR2-1])) ?
-V... | bsd-2-clause |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_semaphore.v | 1,706 | module MODULE1
(input VAR1,
input VAR9,
input [VAR10-1:0] VAR3,
input [2:0] VAR5,
input VAR8,
input VAR7,
input VAR14,
output VAR2,
output [VAR10-1:0] VAR12);
reg [VAR6-1:0] VAR13;
always @(posedge VAR11)
if(VAR9)
VAR13 <= {VAR6{1'b0}};
else if(VAR7)
if(VAR14)
VAR13[VAR4] <= 1'b0;
else
VAR13[VAR4] <= 1'b1;
assign VAR12... | gpl-2.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/mult_27/mult_27.v | 2,184 | module MODULE1 (
VAR2,
VAR12,
VAR21,
VAR5,
VAR6);
input VAR2;
input VAR12;
input [26:0] VAR21;
input [26:0] VAR5;
output [53:0] VAR6;
wire [53:0] VAR10;
wire [53:0] VAR6 = VAR10[53:0];
VAR9 VAR17 (
.VAR12 (VAR12),
.VAR5 (VAR5),
.VAR2 (VAR2),
.VAR21 (VAR21),
.VAR6 (VAR10),
.VAR14 (1'b0),
.sum (1'b0));
VAR17.VAR20 = "VA... | mit |
travisg/cpu | rtl/cpu/cpu.v | 12,180 | module MODULE1(
input clk,
input rst,
output VAR117,
output VAR47,
output [29:0] VAR102,
input [31:0] VAR84,
output [31:0] VAR36,
output [31:0] VAR150
);
assign VAR47 = 0;
assign VAR36 = 0;
assign VAR150 = 0;
wire VAR95;
wire [31:0] VAR17;
wire [29:0] VAR79;
wire VAR129;
wire [29:0] VAR104;
VAR91 VAR46(
.VAR35(clk),
.V... | mit |
alan4186/ParCNN | DE2_115_CAMERA/v/sdram_pll.v | 19,941 | module MODULE1 (
VAR28,
VAR30,
VAR62,
VAR17,
VAR32,
VAR118);
input VAR28;
output VAR30;
output VAR62;
output VAR17;
output VAR32;
output VAR118;
wire [4:0] VAR46;
wire [0:0] VAR21 = 1'h0;
wire [4:4] VAR68 = VAR46[4:4];
wire [3:3] VAR35 = VAR46[3:3];
wire [2:2] VAR102 = VAR46[2:2];
wire [1:1] VAR84 = VAR46[1:1];
wire [0... | mit |
osrf/wandrr | firmware/motor_controller/fpga/udp_spi_tx.v | 1,092 | module MODULE1
(input VAR23,
input [7:0] VAR17,
input VAR25,
output VAR10,
output VAR4,
output VAR16,
input VAR20);
wire [7:0] VAR13;
d1 #(8) VAR6(.VAR23(VAR23), .VAR19(VAR17), .VAR1(VAR13));
wire VAR18;
d1 VAR24(.VAR23(VAR23), .VAR19(VAR25), .VAR1(VAR18));
wire [11:0] VAR7;
VAR14 #(12) VAR22(.VAR23(VAR23), .rst(~VAR18... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai.blackbox.v | 1,356 | module MODULE1 (
VAR1 ,
VAR6,
VAR8,
VAR7,
VAR5,
VAR2
);
output VAR1 ;
input VAR6;
input VAR8;
input VAR7;
input VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.pp.symbol.v | 1,206 | module MODULE1 (
input VAR3 ,
input VAR1,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
secworks/sha256 | src/interfaces/stream/rtl/sha256_stream.v | 2,452 | module MODULE1
(input clk,
input rst,
input VAR6,
input [511:0] VAR13,
input VAR15,
input VAR16,
output VAR12,
output [255:0] VAR9,
output VAR11);
reg VAR3;
always @(posedge clk) begin
if (VAR16 & VAR12)
VAR3 <= VAR15;
if (rst) begin
VAR3 <= 1'b1;
end
end
VAR5 VAR2
(.clk (clk),
.VAR7 (~rst),
.VAR4(VAR16 & VAR3),
.VAR10... | bsd-2-clause |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 3,965 | module MODULE1
(
VAR4,
VAR1,
VAR9) ;
input [0:0] VAR4;
output [0:0] VAR1;
output [0:0] VAR9;
wire [0:0] VAR16;
wire [0:0] VAR13;
wire [0:0] VAR14;
wire [0:0] VAR10;
wire [0:0] VAR19;
wire [0:0] VAR7;
wire [0:0] VAR31;
wire [0:0] VAR21;
wire [0:0] VAR27;
wire [0:0] VAR18;
VAR22 VAR2
(
.VAR33(VAR7),
.VAR20(VAR16[0:0]),
.... | gpl-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_top.v | 37,647 | module MODULE1
(
VAR125, VAR95, VAR136, VAR6,
VAR116, VAR193, VAR42, VAR217, VAR258, VAR233, VAR90,
VAR151, VAR85, VAR143,
VAR114, VAR110, VAR49,
VAR248, VAR268, VAR160,
VAR81, VAR13,
VAR7, VAR291, VAR241, VAR185,
VAR68, VAR122, VAR243, VAR112, VAR119, VAR281,
VAR117, VAR166, VAR61, VAR179,
VAR97
,
VAR140, VAR285, VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.pp.symbol.v | 1,213 | module MODULE1 (
input VAR3,
input VAR5 ,
input VAR1 ,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.pp.blackbox.v | 1,204 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
mda-ut/Tempest | fpga/fpga_hw/top_level/DE0_Nano.v | 8,901 | module MODULE1(
VAR67,
VAR78,
VAR87,
VAR40,
VAR65,
VAR30,
VAR54,
VAR72,
VAR93,
VAR94,
VAR34,
VAR58,
VAR49,
VAR4,
VAR86,
VAR68,
VAR28,
VAR81,
VAR9,
VAR71,
VAR57,
VAR45,
VAR62,
VAR70,
VAR53,
VAR38,
VAR43,
VAR42,
VAR5,
VAR18,
VAR69,
VAR59
);
input VAR67;
output [7:0] VAR78;
input [1:0] VAR87;
input [3:0] VAR40;
output [12... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/txr_engine_classic.v | 16,388 | module MODULE1
parameter VAR87 = 128,
parameter VAR52 = 1,
parameter VAR73 = 0,
parameter VAR50 = 64,
parameter VAR109 = 10,
parameter VAR114 = "VAR129"
)
(
input VAR62,
input VAR11,
input [VAR36-1:0] VAR27,
input VAR42,
output [VAR87-1:0] VAR58,
output VAR70,
output VAR79,
output [VAR111(VAR87/32)-1:0] VAR136,
output ... | gpl-3.0 |
alexforencich/verilog-wishbone | rtl/wb_adapter.v | 14,515 | module MODULE1 #
(
parameter VAR5 = 32, parameter VAR18 = 32, parameter VAR12 = (VAR18/8), parameter VAR28 = 32, parameter VAR17 = (VAR28/8) )
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR9, input wire [VAR18-1:0] VAR33, output wire [VAR18-1:0] VAR26, input wire VAR25, input wire [VAR12-1:0] VAR31, input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.v | 2,615 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR13 ,
VAR6 ,
VAR1,
VAR3 ,
VAR7 ,
VAR5 ,
VAR12
);
output VAR11 ;
output VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR13 ;
input VAR6 ;
input VAR1;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR12 ;
VAR9 VAR10 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR13(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.symbol.v | 1,276 | module MODULE1 (
input VAR6,
input VAR8,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.behavioral.v | 1,245 | module MODULE1( VAR5, VAR7, VAR6, VAR2 );
input VAR5, VAR7, VAR6;
output VAR2;
VAR4 VAR1(.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2));
VAR4 VAR3(.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi_4.v | 2,352 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR7 ,
VAR4 ,
VAR1,
VAR11,
VAR3 ,
VAR9
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR11;
input VAR3 ;
input VAR9 ;
VAR8 VAR10 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR... | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R2P2_syn.v | 8,055 | module MODULE1 ( VAR289, VAR265, VAR73, VAR196 );
input [15:0] VAR265;
input [15:0] VAR73;
output [16:0] VAR196;
input VAR289;
wire VAR93, VAR82, VAR295, VAR169, VAR155, VAR234, VAR156, VAR55, VAR161, VAR254, VAR269, VAR177, VAR141, VAR318,
VAR59, VAR200, VAR305, VAR172, VAR138, VAR116, VAR56, VAR167, VAR240, VAR302, V... | apache-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkMMIO_AXI4_Adapter_2.v | 59,435 | module MODULE1(VAR86,
VAR214,
VAR67,
VAR283,
VAR290,
VAR35,
VAR172,
VAR126,
VAR211,
VAR239,
VAR69,
VAR142,
VAR267,
VAR246,
VAR88,
VAR14,
VAR170,
VAR148,
VAR286,
VAR220,
VAR288,
VAR164,
VAR12,
VAR93,
VAR47,
VAR146,
VAR228,
VAR207,
VAR294,
VAR219,
VAR100,
VAR8,
VAR135,
VAR292,
VAR54,
VAR184,
VAR262,
VAR80,
VAR37,
VAR194,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.pp.blackbox.v | 1,273 | module MODULE1 (
VAR1,
VAR7,
VAR2 ,
VAR4,
VAR3,
VAR5 ,
VAR6
);
output VAR1;
input VAR7;
input VAR2 ;
input VAR4;
input VAR3;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/legacy/wb_prefetch_classic.v | 4,620 | module MODULE1
parameter VAR30 = VAR41-1,
parameter VAR24 = 576, parameter VAR14 = 10,
parameter VAR4 = 1 << VAR14,
parameter VAR44 = VAR14-1,
parameter VAR35 = 24,
parameter VAR16 = 5,
parameter VAR34 = (1 << VAR16) - VAR35,
parameter VAR32 = VAR16-1,
parameter VAR2 = VAR14-VAR16,
parameter VAR46 = VAR2-1,
parameter V... | lgpl-3.0 |
juhasch/myhdl | example/cookbook/bitonic/tmp.v | 19,991 | module MODULE1 (
VAR21,
VAR23,
VAR56,
VAR25,
VAR106,
VAR34,
VAR90,
VAR52,
VAR96,
VAR5,
VAR1,
VAR3,
VAR70,
VAR105,
VAR31,
VAR73
);
input [3:0] VAR21;
input [3:0] VAR23;
input [3:0] VAR56;
input [3:0] VAR25;
input [3:0] VAR106;
input [3:0] VAR34;
input [3:0] VAR90;
input [3:0] VAR52;
output [3:0] VAR96;
wire [3:0] VAR96;... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.symbol.v | 1,258 | module MODULE1 (
input VAR2,
input VAR4,
output VAR1
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.behavioral.pp.v | 1,239 | module MODULE1( VAR8, VAR2, VAR3, VAR4, VAR1 );
input VAR8, VAR2;
inout VAR4, VAR1;
output VAR3;
VAR7 VAR5(.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR6(.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_4.v | 2,411 | module MODULE2 (
VAR4 ,
VAR8,
VAR2,
VAR9 ,
VAR5 ,
VAR10,
VAR7,
VAR6 ,
VAR3
);
output VAR4 ;
input VAR8;
input VAR2;
input VAR9 ;
input VAR5 ;
input VAR10;
input VAR7;
input VAR6 ;
input VAR3 ;
VAR11 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VA... | apache-2.0 |
OSCES/OSCES-FRAMEWORK | src/bsp/fpga/src/TopModule.v | 4,178 | module MODULE1
(
input VAR14 ,
inout wire [7:0] VAR47 ,
output wire [18:0] VAR43 ,
output wire VAR40 ,
output wire VAR64 ,
output wire VAR33 ,
inout wire [7:0] VAR9 ,
input wire [18:0] VAR12 ,
input wire VAR7 ,
input wire VAR11 ,
input wire VAR29 ,
output wire [4:0] VAR41 , output wire [4:0] VAR42 , output wire [4:0] V... | gpl-2.0 |
ultraembedded/altor32 | rtl/cpu_lite/altor32_lite.v | 43,963 | module MODULE1
(
input VAR10 ,
input VAR66 ,
input VAR259 ,
input VAR136 ,
input VAR223 ,
output reg VAR113 ,
output reg VAR121 ,
output reg [31:0] VAR155 ,
input [31:0] VAR165 ,
output reg [31:0] VAR105 ,
output [2:0] VAR12 ,
output reg VAR147 ,
output reg VAR203 ,
output reg VAR145 ,
output reg [3:0] VAR192 ,
input V... | lgpl-3.0 |
hightoon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_DDR_8TO1_16CHAN_RX.v | 17,805 | module MODULE1
(
VAR42,
VAR10,
VAR99,
VAR26,
VAR49,
VAR15,
VAR82,
VAR52,
VAR22,
VAR24,
VAR120,
VAR98,
VAR112,
VAR109,
VAR7,
VAR110,
VAR125
);
input [4:0] VAR49; input [4:0] VAR15; input VAR42,VAR10;
input VAR82; input VAR52; input VAR99; input VAR26; input VAR24;
output [39:0] VAR22; output [5:0] VAR120; output [5:0] V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b_m.v | 2,226 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR3,
VAR8,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR3;
input VAR8;
input VAR6 ;
input VAR4 ;
VAR2 VAR10 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (... | apache-2.0 |
imphil/fusesoc | doc/example/spi_slave.v | 1,056 | module MODULE1
(
input clk,
input rst,
input VAR7,
input VAR2,
output VAR9 = 1'b0,
input VAR5,
output reg [7:0] VAR1);
reg VAR4;
wire VAR3 = ~VAR5 & VAR4 & ~VAR7;
reg [2:0] VAR6;
always @(posedge clk) begin
VAR4 <= VAR7;
if (VAR5)
VAR6 <= 3'd0;
end
else if (VAR3) begin
VAR6 <= VAR6 + 1'd1;
VAR1[VAR6] <= VAR2;
end
if (r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.blackbox.v | 1,288 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR2;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.functional.pp.v | 1,386 | module MODULE1( VAR6, VAR2, VAR15, VAR4, VAR16, VAR3 );
input VAR15, VAR6, VAR4;
inout VAR16, VAR3;
output VAR2;
wire VAR11;
not VAR7( VAR11, VAR15 );
wire VAR1;
not VAR14( VAR1, VAR4 );
wire VAR9;
and VAR12( VAR9, VAR11, VAR1 );
wire VAR13;
not VAR8( VAR13, VAR6 );
wire VAR5;
and VAR17( VAR5, VAR13, VAR1 );
or VAR10( ... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/chardev/FSM_Character.v | 2,908 | module MODULE1(
VAR9, VAR10,
VAR23, VAR2,
VAR19, VAR4,
VAR20, VAR11,
clk,
reset
);
output [VAR8-1:0] VAR9;
output [VAR8-1:0] VAR10;
output [VAR8-1:0] VAR23;
output [VAR8-1:0] VAR2;
input [VAR8-1:0] VAR19;
input [VAR8-1:0] VAR4;
output VAR11;
output reg [VAR8-1:0] VAR20;
input clk;
input reset;
wire [6-1:0] VAR21;
wire ... | gpl-3.0 |
kyzhai/NUNY | src/hardware/homework.v | 6,385 | module MODULE1 (
address,
VAR2,
VAR48);
input [11:0] address;
input VAR2;
output [11:0] VAR48;
tri1 VAR2;
wire [11:0] VAR40;
wire [11:0] VAR48 = VAR40[11:0];
VAR15 VAR20 (
.VAR7 (address),
.VAR32 (VAR2),
.VAR30 (VAR40),
.VAR31 (1'b0),
.VAR12 (1'b0),
.VAR39 (1'b1),
.VAR42 (1'b0),
.VAR52 (1'b0),
.VAR41 (1'b1),
.VAR5 (1'b... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.behavioral.v | 3,306 | module MODULE1( VAR2, VAR1, VAR5, VAR8, VAR7, VAR9 );
input VAR7, VAR9, VAR1, VAR5, VAR8;
output VAR2;
VAR3 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7),.VAR9(VAR9));
VAR3 VAR4(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7),.VAR9(VAR9)); | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler_udivibs.v | 4,433 | module MODULE1
VAR27 = 32,
VAR20 = 32,
VAR22 = 32
)
(
input clk,
input reset,
input VAR9,
input [VAR27-1:0] VAR30,
input [VAR20-1:0] VAR31,
output wire [VAR22-1:0] VAR7,
output wire [VAR22-1:0] VAR15
);
localparam VAR11 = (VAR27 > VAR20)? VAR27 : VAR20;
reg [VAR27-1:0] VAR25[0:VAR27];
reg [VAR20-1:0] VAR5[0:VAR27];
reg... | mit |
balangs/eTeak | runtime/verilog/runtime.v | 13,340 | module MODULE1;
reg VAR8 VAR4 [0:VAR2-1];
reg VAR5 VAR6 [0:VAR2-1];
integer VAR3;
reg VAR9;
VAR1 VAR9 = 1;
reg VAR8 VAR7;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | bsd-3-clause |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_afifo.v | 6,196 | module MODULE1 #
(
parameter VAR6 = 100,
parameter VAR7 = 32,
parameter VAR21 = 16,
parameter VAR36 = 4,
parameter VAR26 = 1 )
(
input VAR13,
input rst,
input VAR30,
input [VAR7-1:0] VAR16,
input VAR19,
input VAR17,
output [VAR7-1:0] VAR25,
output reg VAR12,
output reg VAR4,
output reg VAR32
);
reg [VAR7-1:0] VAR9 [0:V... | bsd-2-clause |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_pll_stream.v | 2,148 | module MODULE1(
input wire VAR40,
input wire rst,
output wire VAR60,
output wire VAR33,
output wire VAR7
);
VAR6 #(
.VAR73("true"),
.VAR67("50.0 VAR62"),
.VAR31("VAR53"),
.VAR39(2),
.VAR10("65.000000 VAR62"),
.VAR2("0 VAR26"),
.VAR42(50),
.VAR34("130.000000 VAR62"),
.VAR70("0 VAR26"),
.VAR8(50),
.VAR71("0 VAR62"),
.VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.behavioral.v | 1,267 | module MODULE1( VAR3, VAR7, VAR5, VAR6 );
input VAR6, VAR5, VAR7;
output VAR3;
VAR2 VAR4(.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6));
VAR2 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.behavioral.v | 2,499 | module MODULE1 (
VAR23 ,
VAR24,
VAR3,
VAR13 ,
VAR10,
VAR22
);
output VAR23 ;
output VAR24;
input VAR3;
input VAR13 ;
input VAR10;
input VAR22;
supply1 VAR20;
supply0 VAR16;
supply1 VAR15 ;
supply0 VAR9 ;
wire VAR14 ;
wire VAR11 ;
reg VAR19 ;
wire VAR21 ;
wire VAR6;
wire VAR12;
wire VAR8;
wire VAR4 ;
wire VAR2 ;
wire VA... | apache-2.0 |
eecsninja/duinocube-core | altera/collision_buffer_1Kx9.v | 10,771 | module MODULE1 (
VAR55,
VAR5,
VAR43,
VAR3,
VAR27,
VAR44,
VAR47,
VAR6,
VAR42);
input [9:0] VAR55;
input [9:0] VAR5;
input VAR43;
input [8:0] VAR3;
input [8:0] VAR27;
input VAR44;
input VAR47;
output [8:0] VAR6;
output [8:0] VAR42;
tri1 VAR43;
tri0 VAR44;
tri0 VAR47;
wire [8:0] VAR59;
wire [8:0] VAR56;
wire [8:0] VAR6 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.pp.blackbox.v | 1,408 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR5 ,
VAR9 ,
VAR3,
VAR2 ,
VAR6 ,
VAR4 ,
VAR7
);
output VAR8 ;
output VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR3;
input VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController/src/nvme_pcie.v | 27,253 | module MODULE1 # (
parameter VAR406 = 128,
parameter VAR412 = 36,
parameter VAR353 = 64
)
(
input VAR297,
input VAR254,
input VAR322,
input VAR217,
output VAR354,
output [29:0] VAR108,
input VAR229,
output VAR126,
output [29:0] VAR99,
input VAR295,
input VAR129,
input VAR233,
output VAR317,
output [1:0] VAR382,
input [... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/shift_mux.v | 1,242 | module MODULE1
(
input wire [VAR8-1:0] VAR10,
input wire VAR3,
input wire VAR14,
output wire [VAR8-1:0] VAR4
);
genvar VAR17;
generate for (VAR17=0; VAR17<=VAR8-1 ; VAR17=VAR17+1) begin : VAR9
localparam VAR1=(2**VAR15)+VAR17;
case (VAR1>VAR8-1)
1'b1:begin : VAR2
VAR16 #(.VAR18(1)) VAR7(
.VAR13(VAR3),
.VAR5 (VAR10[VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.pp.symbol.v | 1,545 | module MODULE1 (
input VAR9 ,
output VAR2 ,
output VAR11 ,
input VAR6,
input VAR10 ,
input VAR5 ,
input VAR7 ,
input VAR3 ,
input VAR4 ,
input VAR1 ,
input VAR8
);
endmodule | apache-2.0 |
amrmorsey/Digital-Design-Project | risingdge.v | 1,138 | module MODULE1(
input clk,
input rst,
input in,
output out
);
reg [1:0] state, VAR1;
parameter [1:0] VAR3 = 2'b00, VAR5 = 2'b01, VAR4=2'b10 ;
always @ (*)
case (state)
VAR3: if(in) VAR1 = VAR5;
else VAR1 = VAR3;
VAR5: if (in) VAR1 = VAR4;
else VAR1 = VAR3;
VAR4: if(in) VAR1= VAR4;
else VAR1= VAR3;
default:
VAR1 = 2'VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.blackbox.v | 1,277 | module MODULE1 (
VAR6 ,
VAR4,
VAR1,
VAR2
);
output VAR6 ;
input VAR4;
input VAR1;
input VAR2 ;
supply1 VAR3;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_20.behavioral.pp.v | 1,164 | module MODULE1( VAR7, VAR6, VAR1, VAR5 );
input VAR7;
inout VAR1, VAR5;
output VAR6;
VAR4 VAR3(.VAR7(VAR7),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR2(.VAR7(VAR7),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/megacells/dspclkpll_bb.v | 1,523 | module MODULE1 (
VAR2,
VAR1,
VAR3);
input VAR2;
output VAR1;
output VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2_4.v | 2,086 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR5,
VAR9,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR5;
input VAR9;
input VAR8 ;
input VAR4 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR2,
VAR6,
VAR3
);
output VAR2;
... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_i2s/rtl/i2s_1khz_wave.v | 2,821 | module MODULE1(
clk,
rst,
VAR2,
pos,
VAR1
);
input clk;
input rst;
input [7:0] pos;
output [7:0] VAR2;
output [15:0] VAR1;
parameter VAR3 = 44;
assign VAR2 = VAR3;
assign VAR1 = VAR4[pos];
wire [15:0] VAR4 [VAR3:0];
assign VAR4[0] = 16'h0000;
assign VAR4[1] = 16'h1237;
assign VAR4[2] = 16'h240F;
assign VAR4[3] = 16'h35... | mit |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s386.v | 7,269 | module MODULE2 (VAR283,VAR244,VAR318);
input VAR283,VAR318;
output VAR244;
wire VAR14,VAR198;
trireg VAR232,VAR259;
nmos VAR212 (VAR259,VAR318,VAR198);
not VAR288 (VAR14,VAR259);
nmos VAR312 (VAR232,VAR14,VAR283);
not VAR208 (VAR244,VAR232);
not VAR168 (VAR198,VAR283);
endmodule
module MODULE1(VAR218,VAR46,VAR283,VAR34... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.v | 2,329 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR10 ,
VAR5,
VAR3 ,
VAR7 ,
VAR2 ,
VAR8
);
output VAR4 ;
input VAR9 ;
input VAR10 ;
input VAR5;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
VAR1 VAR6 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODU... | apache-2.0 |
alexforencich/verilog-axis | rtl/sync_reset.v | 1,697 | module MODULE1 #
(
parameter VAR1 = 2
)
(
input wire clk,
input wire rst,
output wire out
);
reg [VAR1-1:0] VAR2 = {VAR1{1'b1}};
assign out = VAR2[VAR1-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR2 <= {VAR1{1'b1}};
end else begin
VAR2 <= {VAR2[VAR1-2:0], 1'b0};
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR12 ,
VAR1,
VAR10,
VAR13 ,
VAR2
);
output VAR4 ;
input VAR11 ;
input VAR12 ;
input VAR1;
input VAR10;
input VAR13 ;
input VAR2 ;
wire VAR6 ;
wire VAR3;
and VAR9 (VAR6 , VAR11, VAR12 );
VAR8 VAR7 (VAR3, VAR6, VAR1, VAR10);
buf VAR5 (VAR4 , VAR3 );
endmodule | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | OLD/I2C/revised_master.v | 10,268 | module MODULE1(
input wire [6:0] address,
input wire [7:0] register,
input wire VAR1,
input wire VAR19,
input wire VAR7,
input wire en,
input wire reset,
input wire VAR13,
input wire VAR4,
input wire VAR10,
output reg [7:0] out,
output reg ack,
inout wire VAR2,
inout wire VAR16
);
reg [3:0] state;
reg [4:0] counter;
wi... | gpl-3.0 |
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