repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.pp.blackbox.v | 1,409 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR2,
VAR7,
VAR8,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR2;
input VAR7;
input VAR8;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/src/vivado_ip_dram/ecc/mig_7series_v2_3_fi_xor.v | 5,555 | module MODULE1 #
(
parameter integer VAR12 = 72,
parameter integer VAR5 = 9,
parameter integer VAR3 = 4
)
(
input wire clk ,
input wire [2*VAR3*VAR12-1:0] VAR8 ,
output wire [2*VAR3*VAR12-1:0] VAR1 ,
input wire VAR11 ,
input wire [VAR5-1:0] VAR10 ,
input wire [VAR12-1:0] VAR6
);
localparam VAR7 = VAR12 / VAR5;
reg [VAR... | mit |
RonobirDas/ECG604Microprocessor | Baseline/datapth.v | 1,076 | module MODULE1 (input clk, reset,
input VAR8, VAR36,
input VAR6, VAR12,
input VAR14, VAR17,
input [2:0] VAR28,
output VAR11,
output [31:0] VAR25,
input [31:0] VAR16,
output [31:0] VAR34, VAR31,
input [31:0] VAR40);
wire [4:0] VAR19;
wire [31:0] VAR5, VAR38, VAR33, VAR39;
wire [31:0] VAR32, VAR7;
wire [31:0] VAR23, VAR1... | mit |
alexforencich/verilog-ethernet | rtl/xgmii_baser_enc_64.v | 10,723 | module MODULE1 #
(
parameter VAR6 = 64,
parameter VAR4 = (VAR6/8),
parameter VAR2 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR6-1:0] VAR8,
input wire [VAR4-1:0] VAR7,
output wire [VAR6-1:0] VAR1,
output wire [VAR2-1:0] VAR3,
output wire VAR5
); | mit |
gigglesninja/digital-system-design | uart/uart.v | 2,977 | module MODULE1(
input clk,
input reset,
input VAR7,
input fsm,
output [2:0] VAR5,
output VAR24
);
reg VAR2, VAR37, VAR30, VAR33, VAR25, VAR21, VAR10, VAR8, VAR6;
reg [7:0] VAR4;
wire [7:0] ready, VAR13;
wire [8:0] VAR22;
reg [2:0] VAR20, VAR14;
reg [2:0] VAR11, VAR15, dout;
reg [1:0] VAR27;
assign ready = 8'b00000001;
... | gpl-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_next_hop_addr.v | 9,739 | module MODULE1
(VAR26, VAR5, VAR14, VAR47);
parameter VAR27 = 2;
parameter VAR39 = 4;
parameter VAR9 = 2;
parameter VAR12 = 1;
parameter VAR30 = VAR41;
parameter VAR42 = VAR32;
localparam VAR29 = VAR36(VAR27);
localparam VAR16 = VAR36(VAR39);
localparam VAR34 = VAR9 * VAR16;
localparam VAR8 = VAR36(VAR12);
localparam V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.behavioral.v | 1,879 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR13,
VAR11
);
output VAR12 ;
input VAR5 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR13;
input VAR11;
wire VAR9 VAR2 ;
wire VAR3 ;
wire VAR7;
not VAR4 (VAR2 , VAR5 );
and VAR15 (VAR3 , VAR2, VAR1, VAR10, VAR9 );
VAR6 VAR8 (VAR7, VAR3, VAR13, VAR11);
buf VAR1... | apache-2.0 |
fhgwright/SCSI2SD | software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.v | 1,691 | module MODULE1 (
output VAR2,
input [7:0] VAR3,
input VAR6
);
wire VAR7 = 1 ^ VAR3[0];
wire VAR4 = VAR3[1] ^ VAR3[2];
wire VAR5 = VAR3[3] ^ VAR3[4];
wire VAR1 = VAR3[5] ^ VAR3[6] ^ VAR3[7];
assign VAR2 = VAR6 ? VAR7 ^ VAR4 ^ VAR5 ^ VAR1 : 0;
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/pcie_bram_v6.v | 11,310 | module MODULE1
parameter VAR7 = 0, parameter VAR17 = 0 )
(
input VAR14, input VAR4,
input VAR13, input [12:0] VAR15, input [VAR17 - 1:0] VAR16,
input VAR12, input VAR2, input [12:0] VAR18,
output [VAR17 - 1:0] VAR19 );
localparam VAR5 = ((VAR17 == 4) ? 12 :
(VAR17 == 9) ? 11 :
(VAR17 == 18) ? 10 :
(VAR17 == 36) ? 9 :
8... | lgpl-3.0 |
sh-chris110/chris | FPGA/chris.sdram.ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1500364331 : 255;
endmodule | gpl-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/Sound.v | 7,964 | module MODULE2 (
input VAR27,
input VAR38,
input [ 2:0] VAR23,
input [ 1:0] VAR4,
input [15:0] VAR33,
output [15:0] VAR12,
input VAR17,
input VAR5,
input VAR15,
output reg VAR28,
input VAR21,
output VAR1,
output VAR36
);
reg [7:0] VAR30;
wire [3:0] VAR13 = {VAR23, VAR4[1]};
wire [7:0] VAR6 = VAR4[0] ? VAR33[7:0] : VAR3... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/pcie_reset_logic.v | 11,029 | module MODULE1
(
VAR12,
VAR29,
VAR30,
VAR23,
VAR16,
VAR32,
VAR6,
VAR34,
VAR38,
VAR18,
VAR15,
VAR4,
VAR40,
VAR37,
VAR2,
VAR41
);
input VAR12;
input VAR29;
input VAR30;
input VAR23;
input [3:0] VAR16;
input VAR32;
input VAR6;
input VAR34;
output VAR38;
output VAR18;
output VAR15;
output VAR4;
output VAR40;
output VAR37;
... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.behavioral.v | 18,884 | module MODULE1( VAR123, VAR128, VAR73, VAR283, VAR277, VAR124 );
input VAR283, VAR73, VAR123, VAR277, VAR128;
output VAR124;
reg VAR163;
VAR197 VAR24(.VAR123(VAR123),.VAR128(VAR128),.VAR73(VAR73),.VAR283(VAR283),.VAR277(VAR277),.VAR124(VAR124),.VAR163(VAR163));
VAR197 VAR63(.VAR123(VAR123),.VAR128(VAR128),.VAR73(VAR73)... | apache-2.0 |
ElegantLin/My-CPU | Snake/Snake.srcs/sources_1/new/VGA_Control.v | 2,032 | module MODULE1
(
input clk,
input rst,
input [1:0]VAR8,
input [5:0]VAR19,
input [4:0]VAR1,
output reg[9:0]VAR12,
output reg[9:0]VAR2,
output reg VAR13,
output reg VAR14,
output reg [11:0] VAR9
);
reg [19:0]VAR3;
reg [9:0]VAR11;
reg VAR10;
localparam VAR6 = 2'b00;
localparam VAR7 = 2'b01;
localparam VAR16 = 2'b10;
local... | gpl-3.0 |
mindrobots/P8X32A_Emulation | P8X32A_DE0_Nano/cog_vid.v | 5,029 | module MODULE1
(
input VAR12,
input VAR29,
input VAR15,
input VAR26,
input VAR21,
input [31:0] VAR23,
input [31:0] VAR17,
input [31:0] VAR20,
input [7:0] VAR4,
input VAR33,
output ack,
output [31:0] VAR3
);
reg [31:0] VAR30;
reg [31:0] VAR14;
always @(posedge VAR12 or negedge VAR15)
if (!VAR15)
VAR30 <= 32'b0;
else if ... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_dma_writer/rtl/wb_dma_writer.v | 11,651 | module MODULE1 #(
parameter VAR22 = 12
)(
input clk,
input rst,
input VAR110,
input VAR52,
input [3:0] VAR84,
input [31:0] VAR93,
input VAR40,
output reg VAR57,
output reg [31:0] VAR33,
input [31:0] VAR55,
output reg VAR14,
output VAR74,
output VAR8,
output VAR17,
output [3:0] VAR66,
output [31:0] VAR80,
output [31:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_nsr/sky130_fd_sc_hdll__udp_dff_nsr.blackbox.v | 1,353 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1,
VAR2,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.behavioral.v | 3,726 | module MODULE1( VAR19, VAR25, VAR14, VAR5 );
input VAR19, VAR25, VAR14;
output VAR5;
reg VAR7;
VAR1 VAR10(.VAR19(VAR19),.VAR25(VAR25),.VAR14(VAR14),.VAR5(VAR5),.VAR7(VAR7));
VAR1 VAR9(.VAR19(VAR19),.VAR25(VAR25),.VAR14(VAR14),.VAR5(VAR5),.VAR7(VAR7));
not VAR31(VAR20,VAR25);
and VAR16(VAR27,VAR14,VAR20);
and VAR13(VAR2... | apache-2.0 |
fpgasystems/caribou | hw/src/net/tcp_ip_wrapper.v | 55,246 | module MODULE1 #(
parameter VAR95 = 48'hE59D02350A00, parameter VAR94 = 32'h00000000,
parameter VAR335 = 32'h00FFFFFF,
parameter VAR346 = 32'h00000000,
parameter VAR288 = 0
)(
input VAR151,
input VAR440,
output VAR339,
input VAR191,
output[63:0] VAR33,
output[7:0] VAR108,
output VAR176,
input VAR45,
output VAR157,
inpu... | gpl-3.0 |
Madh93/scpu | modules/componentes.v | 4,551 | module MODULE3(input wire clk,
input wire VAR3, input wire [3:0] VAR25, VAR8, VAR20, input wire [7:0] VAR5, output wire [7:0] VAR16, VAR9);
reg [7:0] VAR11[0:15];
always @(posedge clk)
if (VAR3) VAR11[VAR20] <= VAR5;
assign VAR16 = (VAR25 != 0) ? VAR11[VAR25] : 8'b00000000;
assign VAR9 = (VAR8 != 0) ? VAR11[VAR8] : 8'b... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.behavioral.v | 3,634 | module MODULE1( VAR31, VAR19, VAR8, VAR30 );
input VAR31, VAR19, VAR8;
output VAR30;
reg VAR24;
VAR6 VAR22(.VAR31(VAR31),.VAR19(VAR19),.VAR8(VAR8),.VAR30(VAR30),.VAR24(VAR24));
VAR6 VAR1(.VAR31(VAR31),.VAR19(VAR19),.VAR8(VAR8),.VAR30(VAR30),.VAR24(VAR24));
not VAR4(VAR25,VAR19);
and VAR32(VAR15,VAR8,VAR25);
and VAR18(V... | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/ethmac/eth_wishbone.v | 70,559 | module MODULE1
(
VAR225, VAR142, VAR42,
VAR108, VAR162, VAR178,
VAR217,
VAR32,
VAR91, VAR260, VAR50,
VAR57, VAR276, VAR138,
VAR4, VAR169, VAR134,
VAR107, VAR186,
VAR172, VAR205, VAR104, VAR36, VAR241,
VAR192, VAR58, VAR115, VAR106, VAR30,
VAR84,
VAR11, VAR6, VAR155, VAR177, VAR53, VAR10, VAR301,
VAR123, VAR35, VAR37, V... | gpl-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Add_Sub/ADD_SUB_PIPELINED/ADD_SUB_FUNCIONAL_v1.srcs/sources_1/imports/Karatsuba_FPU/Pipeline_FPADD_sourcefiles/FPU_ADD_Substract_PIPELINED.v | 24,859 | module MODULE1
/*#(parameter VAR52 = 32, parameter VAR59 = 8, parameter VAR65 = 23,
parameter VAR184=26, parameter VAR129 = 5)
parameter VAR184 = 55, parameter VAR129 = 6) (
input wire clk,
input wire rst,
input wire VAR126,
input wire [VAR52-1:0] VAR55,
input wire [VAR52-1:0] VAR120,
input wire VAR47,
output wire VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.blackbox.v | 1,228 | module MODULE1 (
VAR6,
VAR5
);
output VAR6;
input VAR5;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Jside/pdp1 | pdp1_sbs_decoder.v | 2,801 | module MODULE1(VAR5, VAR17, VAR7, VAR10,
VAR16, VAR9, VAR4, VAR2);
parameter VAR11 = "VAR8";
input VAR5;
input VAR17;
input VAR7;
input VAR10;
output [0:11] VAR16;
output [0:11] VAR9;
output [0:11] VAR4;
output [0:11] VAR2;
generate
if(VAR11 == "VAR8") begin
assign VAR16 = 12'o0000;
assign VAR9 = 12'o0002;
assign VAR4 ... | gpl-3.0 |
chriz2600/DreamcastHDMI | Core/source/preproc/gammaconv.v | 1,162 | module MODULE1(
input VAR20,
input [4:0] VAR13,
input VAR16,
input [VAR4-1:0] VAR6,
input [7:0] VAR19,
input [7:0] VAR18,
input [7:0] VAR5,
input VAR23,
output reg VAR1,
output reg [VAR4-1:0] VAR14,
output reg [23:0] VAR17,
output reg VAR11
);
wire [7:0] VAR8;
wire [7:0] VAR15;
wire [7:0] VAR3;
VAR9 VAR21(
.VAR20(VAR20... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/op_lut_hdr_parser.v | 4,601 | module MODULE1
parameter VAR23 = VAR27/8,
parameter VAR24 = 8,
parameter VAR15 = VAR36(VAR24),
parameter VAR8 = 2,
parameter VAR11 = VAR11
)
( input [VAR27-1:0] VAR37,
input [VAR23-1:0] VAR20,
input VAR30,
output VAR22,
output [VAR24-1:0] VAR33, output [VAR24-1:0] VAR14, output [VAR15-1:0] VAR12,
input VAR35,
output VA... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_hclkgen_regs.v | 6,189 | module MODULE1(
input clk,
input VAR29,
output VAR49 ,
output VAR16 ,
output VAR42 ,
output [1:0] VAR44,
output [7:0] VAR26,
output [4:0] VAR4,
output VAR3,
output [5:0] VAR33,
output VAR7,
input VAR19,
output VAR34,
input [12-1:0] VAR37,
input VAR38,
input [32-1:0] VAR9,
output VAR50,
input VAR39,
output [32-1:0] VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.functional.v | 1,140 | module MODULE1 ();
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_round.v | 5,418 | module MODULE1
(input wire clk,
output reg [VAR7:0] VAR13,
input wire VAR19, VAR21,
input wire VAR4,
input wire [30:0] VAR1,
input wire [30:0] VAR5,
input wire [VAR10-1:0] VAR23,
input wire VAR15,VAR16,
input wire [VAR7:0] VAR6);
reg [2:0] VAR2;
reg [3:0] VAR8;
reg [3:0] VAR18;
reg [30:0] VAR20;
always @* begin
if(VAR1... | gpl-3.0 |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_rf.v | 63,233 | module MODULE1(clk, rst,
VAR99, VAR126, VAR96, VAR89, VAR17,
VAR329, VAR251,
VAR55, VAR167, VAR350, VAR50, VAR87, VAR327, VAR208, VAR125,
VAR66, VAR317, VAR98, VAR383, VAR16, VAR33, VAR373, VAR331,
VAR171, VAR263, VAR13, VAR5, VAR159, VAR391, VAR291, VAR345,
VAR335, VAR229, VAR367, VAR257, VAR115, VAR299, VAR253, VAR25... | apache-2.0 |
golfit/QcmPhaseDelayBoard | Delay.v | 2,641 | module MODULE1(clk, VAR5, VAR2, VAR4);
parameter VAR7=11;
input clk, VAR5;
input [VAR7-1:0] VAR2;
output wire VAR4;
reg VAR1, VAR3;
reg [VAR7-1:0] VAR6; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.blackbox.v | 1,322 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR5;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_reg_vram_addr.v | 8,395 | module MODULE1 (
VAR25,
VAR28, VAR16, VAR2, VAR18, VAR27, VAR15, VAR30, VAR1, VAR17, VAR31, VAR21, VAR13, VAR10, VAR14, VAR11, VAR3, VAR24 );
output [VAR9:0] VAR25;
input VAR28; input VAR16; input [VAR20:0] VAR2; input VAR18; input VAR27; input VAR15; input VAR30; input VAR1; input [VAR9:0] VAR17; input VAR31; input VA... | bsd-3-clause |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_tck.v | 8,351 | module MODULE1 (
VAR5,
VAR23,
VAR17,
VAR11,
VAR22,
VAR39,
VAR20,
VAR34,
VAR18,
VAR32,
VAR6,
VAR27,
VAR28,
VAR26,
VAR2,
VAR10,
VAR12,
VAR14,
VAR13,
VAR31,
VAR36,
VAR8,
VAR37,
VAR29,
VAR40,
VAR1,
VAR19,
VAR4,
VAR9,
VAR30,
VAR35
)
;
output [ 1: 0] VAR19;
output VAR4;
output [ 37: 0] VAR9;
output VAR30;
output VAR35;
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2_m.v | 2,114 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR7,
VAR4,
VAR9 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR7;
input VAR4;
input VAR9 ;
input VAR1 ;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5,
VAR6,
VAR3
);
output VAR5;
... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/statemachine_shared_OLD.v | 137,514 | module MODULE1(
input clk,
input VAR25,
input [3:0] VAR22,
input [3:0] VAR21,
input [3:0] VAR14,
input [3:0] VAR4,
input [11:0] VAR5,
input [11:0] VAR17,
input [11:0] VAR26,
input [11:0] VAR7,
input VAR11,
input VAR6,
input VAR1,
input VAR3,
input reset,
output VAR13,
output VAR12,
output VAR23,
output VAR27
);
reg [3:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv.functional.pp.v | 1,842 | module MODULE1 (
VAR2,
VAR4 ,
VAR7 ,
VAR6 ,
VAR1
);
output VAR2;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
wire VAR10 ;
wire VAR11;
pulldown VAR3 (VAR10 );
VAR5 VAR9 (VAR11, VAR7, VAR7, VAR10 );
bufif0 VAR8 (VAR2 , VAR11, VAR4);
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_m00_regslice_1/synth/zc702_m00_regslice_1.v | 15,513 | module MODULE1 (
VAR9,
VAR104,
VAR20,
VAR53,
VAR44,
VAR31,
VAR12,
VAR110,
VAR29,
VAR27,
VAR3,
VAR89,
VAR58,
VAR59,
VAR71,
VAR83,
VAR109,
VAR90,
VAR43,
VAR28,
VAR100,
VAR73,
VAR34,
VAR52,
VAR67,
VAR40,
VAR101,
VAR19,
VAR72,
VAR25,
VAR68,
VAR107,
VAR84,
VAR64,
VAR41,
VAR79,
VAR22,
VAR76,
VAR55,
VAR94,
VAR18,
VAR88,
VAR63... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.v | 2,703 | module MODULE2 (
VAR8 ,
VAR13 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR3,
VAR11 ,
VAR9 ,
VAR12 ,
VAR6
);
output VAR8 ;
output VAR13 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR3;
input VAR11 ;
input VAR9 ;
input VAR12 ;
input VAR6 ;
VAR7 VAR4 (
.VAR8(VAR8),
.VAR13(VAR13),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VA... | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/async_ram_2port.v | 4,940 | module MODULE1
( input [VAR3(VAR5)-1:0] VAR10
,input VAR16
,input [VAR2-1:0] VAR6
,output reg [VAR2-1:0] VAR12
,input [VAR3(VAR5)-1:0] VAR11
,input VAR14
,input [VAR2-1:0] VAR4
,output reg [VAR2-1:0] VAR8
);
reg [VAR2-1:0] VAR9 [VAR5-1:0]; reg [VAR2-1:0] VAR15;
reg [VAR2-1:0] VAR1;
VAR13 begin
if (VAR16) begin
VAR15 = ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.behavioral.pp.v | 1,561 | module MODULE1( VAR1, VAR4, VAR9, VAR6, VAR8, VAR2 );
input VAR9, VAR1, VAR6;
inout VAR8, VAR2;
output VAR4;
VAR7 VAR3(.VAR1(VAR1),.VAR4(VAR4),.VAR9(VAR9),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2));
VAR7 VAR5(.VAR1(VAR1),.VAR4(VAR4),.VAR9(VAR9),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_dexp_64ns_64ns_64_18_full_dsp.v | 1,637 | module MODULE1
VAR18 = 8,
VAR22 = 18,
VAR3 = 64,
VAR2 = 64,
VAR7 = 64
)(
input wire clk,
input wire reset,
input wire VAR4,
input wire [VAR3-1:0] VAR13,
input wire [VAR2-1:0] VAR12,
output wire [VAR7-1:0] dout
);
wire VAR19;
wire VAR16;
wire VAR8;
wire [63:0] VAR15;
wire VAR9;
wire [63:0] VAR14;
reg [VAR2-1:0] VAR20;
V... | gpl-3.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/artemis_pcie_interface.v | 24,130 | module MODULE1 #(
parameter VAR72 = 7,
parameter VAR66 = 9,
parameter VAR98 = 64'h000000000000C594
)(
input clk,
input rst,
input VAR208,
input VAR189,
output VAR197,
output VAR31,
input VAR153,
input VAR212,
output VAR193,
output VAR160,
input [2:0] VAR5,
output [7:0] VAR150,
output [11:0] VAR14,
output [7:0] VAR219,
... | gpl-2.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 13,287 | module MODULE1 (
VAR42,
VAR20,
VAR89,
VAR13,
VAR53,
VAR106,
VAR64,
VAR76,
VAR50,
VAR19,
VAR103,
VAR95,
VAR102,
VAR83,
VAR51,
VAR111,
VAR22,
VAR59,
VAR80,
VAR92,
VAR58,
VAR70,
VAR60,
VAR40,
VAR113,
VAR108,
VAR82,
VAR7,
VAR81,
VAR16,
VAR69,
VAR99,
VAR87,
VAR75,
VAR57,
VAR47,
VAR31,
VAR10,
VAR2,
VAR85,
VAR68,
VAR110,
VAR1... | gpl-3.0 |
hoangt/NOCulator | hring/hw/bless/cf/router.v | 5,962 | module MODULE1(VAR97,
VAR40,
VAR74, VAR71, VAR79, VAR52,
VAR56, VAR28, VAR11, VAR90,
VAR23, VAR95, VAR111, VAR8,
VAR54, VAR101, VAR18, VAR117,
VAR21, VAR120, VAR77, VAR86,
VAR46, VAR108, VAR37, VAR129,
VAR48, VAR57, VAR127, VAR87,
VAR12, VAR112, VAR89, VAR103,
VAR59, VAR78, VAR4,
VAR62,
VAR73, VAR99, VAR115);
input VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.behavioral.pp.v | 8,324 | module MODULE1( VAR12, VAR4, VAR5, VAR2, VAR8, VAR10, VAR1, VAR7, VAR11 );
input VAR1, VAR10, VAR12, VAR5, VAR4, VAR8;
inout VAR7, VAR11;
output VAR2;
VAR9 VAR6(.VAR12(VAR12),.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR8(VAR8),.VAR10(VAR10),.VAR1(VAR1),.VAR7(VAR7),.VAR11(VAR11));
VAR9 VAR3(.VAR12(VAR12),.VAR4(VAR4),.VAR5(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp.pp.symbol.v | 1,386 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR6,
input VAR2 ,
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR8
);
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binari_epxgolomb_1kth.v | 18,713 | module MODULE1(
VAR14 ,
VAR6 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR5
);
input [ 7:0 ] VAR14 ;
input VAR6 ;
output [ 2:0 ] VAR3 ;
output [ 2:0 ] VAR12 ;
output [ 2:0 ] VAR1 ;
output [14:0 ] VAR5 ;
reg [ 2:0 ] VAR17 ;
reg [ 2:0 ] VAR4 ;
reg [ 2:0 ] VAR13 ;
wire [ 7:0 ] VAR11 ;
wire [ 7:0 ] VAR2 ;
wire [ 7:0 ] VAR7 ;
wire [ 7:0 ] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.pp.symbol.v | 1,361 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR1 ,
input VAR7 ,
input VAR5 ,
output VAR6 ,
input VAR2,
input VAR8
);
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/axis_xgmii_rx_64.v | 15,668 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR7 = (VAR3/8),
parameter VAR1 = (VAR3/8),
parameter VAR18 = 4'h6,
parameter VAR15 = 16'h6666,
parameter VAR8 = 0,
parameter VAR10 = 96,
parameter VAR9 = (VAR8 ? VAR10 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR19,
input wire [VAR1-1:0] VAR12... | mit |
queq/just-stuff | pov/TopFixed/controlTransmitter.v | 2,359 | module MODULE1 (VAR18, VAR17, VAR4, VAR15, VAR11, VAR6, VAR1, VAR7, VAR16, VAR8, clk);
input VAR18, VAR17, VAR4, clk, VAR8, VAR15;
output reg VAR11, VAR6, VAR1, VAR7, VAR16;
reg [2:0] VAR9;
reg [2:0] VAR12;
parameter VAR14=3'b000, VAR3=3'b001, VAR13=3'b010, VAR5=3'b011;
parameter VAR2=3'b100, VAR10=3'b101;
always @(VAR... | mit |
SiLab-Bonn/pyBAR | firmware/lx9/src/top.v | 14,168 | module MODULE1 (
input wire VAR53,
input wire VAR120,
input wire VAR88,
input wire VAR7,
output wire VAR66,
inout wire VAR80,
output wire VAR142,
input wire VAR92,
input wire [3:0] VAR122,
input wire VAR47,
input wire VAR42,
input wire VAR130,
output wire [3:0] VAR167,
output wire VAR236,
output wire [3:0] VAR3,
input ... | bsd-3-clause |
swallat/yosys | techlibs/intel/max10/cells_arith.v | 2,584 | module MODULE1(
module 80alteramax10alu (VAR6, VAR27, VAR9, VAR4, VAR7, VAR19, VAR16);
parameter VAR12 = 0;
parameter VAR22 = 0;
parameter VAR29 = 1;
parameter VAR32 = 1;
parameter VAR17 = 1;
input [VAR29-1:0] VAR6;
input [VAR32-1:0] VAR27;
output [VAR17-1:0] VAR7, VAR19;
input VAR9, VAR4;
output VAR16;
wire VAR11 = VA... | isc |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/CvtColor_1_sectorocq.v | 1,246 | module MODULE1 (
VAR7, VAR1, VAR4, clk);
parameter VAR2 = 2;
parameter VAR3 = 3;
parameter VAR5 = 6;
input[VAR3-1:0] VAR7;
input VAR1;
output reg[VAR2-1:0] VAR4;
input clk;
reg [VAR2-1:0] VAR6[0:VAR5-1];
begin
begin | mit |
drichmond/riffa | fpga/riffa_hdl/tx_port_monitor_32.v | 8,732 | module MODULE1 #(
parameter VAR43 = 9'd32,
parameter VAR19 = 512,
parameter VAR7 = (VAR19 - 4),
parameter VAR31 = VAR5((2**VAR5(VAR19))+1),
parameter VAR39 = 1
)
(
input VAR4,
input VAR29,
input [VAR43:0] VAR24, input VAR44, output VAR1,
output [VAR43-1:0] VAR18, output VAR20, input [VAR31-1:0] VAR8,
output VAR42, inpu... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold0/sky130_fd_sc_lp__bushold0.pp.blackbox.v | 1,359 | module MODULE1 (
VAR1 ,
VAR3,
VAR4 ,
VAR2 ,
VAR6 ,
VAR5
);
inout VAR1 ;
input VAR3;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/channel_32.v | 9,863 | module MODULE1 #(
parameter VAR46 = 9'd32,
parameter VAR88 = 2, parameter VAR37 = 1024,
parameter VAR18 = 512,
parameter VAR19 = 1024,
parameter VAR85 = VAR36((VAR46/32)+1)
)
(
input VAR52,
input VAR41,
input [2:0] VAR33, input [2:0] VAR7,
input [31:0] VAR90, input [VAR46-1:0] VAR60,
output VAR57, input VAR86, input VA... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/db/altera_mult_add_vl9g.v | 22,181 | module MODULE1
(
VAR94,
VAR67,
VAR191,
VAR82,
VAR303) ;
input VAR94;
input [26:0] VAR67;
input [26:0] VAR191;
input VAR82;
output [53:0] VAR303;
tri1 VAR94;
tri0 [26:0] VAR67;
tri0 [26:0] VAR191;
tri1 VAR82;
wire [53:0] VAR211;
VAR136 VAR225
(
.VAR88(),
.VAR94(VAR94),
.VAR67(VAR67),
.VAR191(VAR191),
.VAR82(VAR82),
.VAR... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/rom_shared_bb.v | 8,530 | module MODULE1 (
VAR1,
VAR3,
VAR2,
VAR4,
VAR8,
VAR6,
VAR5,
VAR7);
input VAR1;
input [11:0] VAR3;
input [11:0] VAR2;
input VAR4;
input VAR8;
input VAR6;
output [31:0] VAR5;
output [31:0] VAR7;
tri0 VAR1;
tri1 VAR4;
tri1 VAR8;
tri1 VAR6;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2_1.v | 2,086 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR9,
VAR5,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR5;
input VAR6 ;
input VAR8 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2,
VAR7,
VAR1
);
output VAR2;
... | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/audio_direct_1.0/audio_direct.v | 1,086 | module MODULE1(
input wire VAR10,
input wire VAR6,
input wire VAR14,
output wire VAR16,
output wire VAR4,
output wire VAR5,
output wire VAR17
);
wire VAR9;
wire [15:0] VAR2;
reg VAR15;
reg [15:0] VAR1;
assign VAR17 = VAR15;
VAR12 VAR11 (
.clk(VAR10),
.en(VAR6),
.dout(VAR2),
.VAR16(VAR16),
.VAR13(VAR14)
);
always @(pose... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_backup.v | 2,445 | module MODULE1
, parameter VAR2=VAR3(VAR1)
)
(
input [VAR1-1:0] VAR11
, output logic [VAR5(VAR1, 2):0] VAR10
, output logic [VAR5(VAR1, 2):0] VAR12
);
if (VAR1 == 1) begin: VAR7
assign VAR10 = 1'b1;
assign VAR12 = 1'b0;
end
else begin: VAR13
for (genvar VAR8 = 0; VAR8 < VAR2; VAR8++) begin
logic [(2**(VAR8+1))-1:0] VAR... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/aemb/aeMB_bpcu.v | 5,265 | module MODULE1 (
VAR31, VAR4, VAR30, VAR10, VAR20,
VAR16, VAR21, VAR29, VAR14, VAR2, VAR7, VAR38, VAR32, VAR24, VAR5
);
parameter VAR27 = 24;
output [VAR27-1:2] VAR31;
output [31:2] VAR4, VAR30;
output VAR10;
output VAR20;
input [1:0] VAR16;
input [5:0] VAR21;
input [4:0] VAR29, VAR14;
input [31:0] VAR2; input [31:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b_2.v | 2,136 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR6 ,
VAR3,
VAR7,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR3;
input VAR7;
input VAR5 ;
input VAR4 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8 ,
VAR9,
VAR6
);
output VAR8 ... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/dpram_altera.v | 3,377 | module MODULE1 #(
parameter VAR4 = 3
)
(
input VAR19,
input [VAR4-1:0] VAR13,
input [3:0] VAR45,
input [31:0] VAR23,
output [31:0] VAR22,
input VAR56,
input [VAR4-1:0] VAR51,
input [3:0] VAR44,
input [31:0] VAR48,
output [31:0] VAR32
);
VAR40 VAR36 (
.VAR52 (VAR45),
.VAR46 (VAR19),
.VAR3 (|VAR45),
.VAR38 (VAR51),
.VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.behavioral.v | 3,106 | module MODULE1 (
VAR22 ,
VAR16 ,
VAR30 ,
VAR34 ,
VAR24 ,
VAR8,
VAR14
);
output VAR22 ;
input VAR16 ;
input VAR30 ;
input VAR34 ;
input VAR24 ;
input VAR8;
input VAR14;
supply1 VAR25;
supply1 VAR33 ;
supply0 VAR7 ;
supply1 VAR31 ;
supply0 VAR13 ;
wire VAR20 ;
wire VAR18 ;
wire VAR28 ;
reg VAR26 ;
wire VAR12 ;
wire VAR11... | apache-2.0 |
SymbiFlow/fpga-tool-perf | src/hps-accel-gen1-nexus/cfu.v | 593,115 | module MODULE3(VAR10, VAR354, VAR242, VAR121, VAR220, VAR165, VAR32, reset, clk, rst, VAR92);
reg \VAR350 = 0;
wire [32:0] \27 ;
wire [32:0] \28 ;
wire [31:0] \VAR331 ;
wire \VAR139 ;
reg \VAR319 ;
wire [31:0] \VAR269 ;
wire \VAR416 ;
reg \VAR295 ;
wire [31:0] \VAR153 ;
wire \VAR408 ;
reg \VAR110 ;
wire [31:0] \VAR234 ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.v | 2,443 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR1 ,
VAR11,
VAR6,
VAR10 ,
VAR12
);
output VAR7 ;
output VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR11;
input VAR6;
input VAR10 ;
input VAR12 ;
VAR9 VAR4 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(V... | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2.v | 12,481 | module MODULE1
(VAR166,
VAR181,
VAR179,
VAR97,
VAR29,
VAR114,
VAR121,
VAR88,
VAR173,
VAR159,
VAR211,
VAR7,
VAR137,
VAR74,
VAR111,
VAR19,
VAR61,
VAR67,
VAR26,
VAR167,
VAR187,
VAR184,
VAR198,
VAR168,
VAR76,
VAR94,
VAR45,
VAR83,
VAR152,
VAR162,
VAR189,
VAR51,
VAR139,
VAR138,
VAR102,
VAR36,
VAR127,
VAR66,
VAR120,
VAR112,
V... | bsd-3-clause |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_repeater_6.v | 5,374 | module MODULE1(
input VAR34,
input reset,
input VAR59,
output VAR5,
output VAR40,
input VAR24,
input [2:0] VAR22,
input [2:0] VAR32,
input [2:0] VAR1,
input [1:0] VAR19,
input [29:0] VAR7,
input VAR41,
input [7:0] VAR36,
input VAR3,
output VAR21,
output [2:0] VAR57,
output [2:0] VAR51,
output [2:0] VAR30,
output [1:0] ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa_0.v | 2,278 | module MODULE2 (
VAR6,
VAR3 ,
VAR2 ,
VAR8 ,
VAR1 ,
VAR11,
VAR4,
VAR7 ,
VAR10
);
output VAR6;
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR11;
input VAR4;
input VAR7 ;
input VAR10 ;
VAR5 VAR9 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR... | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/flter/filterbank.v | 8,057 | module MODULE1
parameter VAR33 = 8,
parameter VAR39 = 32,
parameter VAR44 = 1,
parameter VAR37 = 10,
parameter VAR43 = 0,
parameter VAR36 = 64
)
(
input wire clk,
input wire VAR49,
input wire [VAR39-1:0] VAR20,
input wire VAR25,
input wire [VAR44-1:0] VAR35,
input wire [VAR23-1:0] VAR7,
input wire VAR50,
output wire [V... | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/ddr2_example_driver.v | 30,814 | module MODULE1 (
clk,
VAR80,
VAR42,
VAR83,
VAR28,
VAR50,
VAR66,
VAR47,
VAR44,
VAR69,
VAR71,
VAR56,
VAR67,
VAR16,
VAR63,
VAR52,
VAR27,
VAR58,
VAR13
)
;
output [ 1: 0] VAR50;
output [ 3: 0] VAR66;
output VAR47;
output [ 9: 0] VAR44;
output VAR69;
output VAR71;
output [ 12: 0] VAR56;
output [ 3: 0] VAR67;
output [ 31: 0] ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.functional.pp.v | 1,538 | module MODULE1 (
VAR7,
VAR10,
VAR1 ,
VAR5 ,
VAR8
);
input VAR7;
input VAR10;
output VAR1 ;
input VAR5 ;
input VAR8 ;
wire VAR9;
VAR2 VAR6 VAR4 (VAR9 , VAR8, VAR5, VAR7, VAR10);
buf VAR3 (VAR1 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.behavioral.v | 2,340 | module MODULE1 (
VAR3 ,
VAR18,
VAR12 ,
VAR17,
VAR14
);
output VAR3 ;
input VAR18;
input VAR12 ;
input VAR17;
input VAR14;
supply1 VAR13;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR22 ;
wire VAR5 ;
wire VAR23 ;
reg VAR6 ;
wire VAR25 ;
wire VAR8;
wire VAR7;
wire VAR9;
wire VAR19 ;
wire VAR15 ;
wire VAR21 ;
wire VAR4 ;
VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4_lp.v | 2,239 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR10 ,
VAR4,
VAR11,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR4;
input VAR11;
input VAR2 ;
input VAR6 ;
VAR5 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR2(VAR2),
.... | apache-2.0 |
brianbennett/fpga_nes | hw/src/cmn/uart/uart_rx.v | 6,330 | module MODULE1
parameter VAR6 = 8,
parameter VAR12 = 1,
parameter VAR14 = 1, parameter VAR4 = 16
)
(
input wire clk, input wire reset, input wire VAR26, input wire VAR25, output wire [VAR6-1:0] VAR11, output wire VAR19, output wire VAR24 );
localparam [5:0] VAR23 = VAR12 * VAR4;
localparam [4:0] VAR15 = 5'h01,
VAR2 = 5... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v | 1,313 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR1;
or VAR4 (VAR3 , VAR2, VAR1 );
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_dmmu_tlb.v | 7,199 | module MODULE1(
clk, rst,
VAR33, VAR19, VAR45, VAR48, VAR31, VAR14, VAR27, VAR6, VAR29,
VAR7, VAR18, VAR41,
VAR1, VAR53, VAR25, VAR5, VAR40
);
parameter VAR58 = VAR16;
parameter VAR37 = VAR16;
input clk;
input rst;
input VAR33;
input [VAR37-1:0] VAR19;
output VAR45;
output [31:VAR3] VAR48;
output VAR31;
output VAR14;
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.symbol.v | 1,375 | module MODULE1 (
input VAR2,
input VAR7,
input VAR4,
input VAR5,
output VAR6
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_spram_64x22.v | 12,973 | module MODULE1(
VAR40, VAR16, VAR33,
clk, rst, VAR52, VAR46, VAR41, addr, VAR23, VAR4
);
parameter VAR31 = 6;
parameter VAR39 = 22;
input VAR40;
input [VAR7 - 1:0] VAR33;
output VAR16;
input clk; input rst; input VAR52; input VAR46; input VAR41; input [VAR31-1:0] addr; input [VAR39-1:0] VAR23; output [VAR39-1:0] VAR4;
... | gpl-2.0 |
omicronns/studies-sys-rek | de1-soc-proc/src/proc/core.v | 8,368 | module MODULE6(
input VAR64,
input [7:0] VAR26,
output [7:0] VAR34
);
wire [31:0] VAR11;
wire VAR69;
wire VAR82;
wire VAR65;
wire VAR13;
wire [1:0] VAR79;
wire [2:0] VAR87;
wire VAR20;
wire VAR55;
wire VAR32;
wire VAR33;
wire [3:0] VAR86;
wire [3:0] VAR97;
wire [3:0] VAR81;
wire [7:0] VAR77;
wire [7:0] VAR45;
wire [7:0... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.behavioral.v | 1,250 | module MODULE1( VAR5, VAR7, VAR2, VAR1 );
input VAR5, VAR7, VAR2;
output VAR1;
VAR6 VAR3(.VAR5(VAR5),.VAR7(VAR7),.VAR2(VAR2),.VAR1(VAR1));
VAR6 VAR4(.VAR5(VAR5),.VAR7(VAR7),.VAR2(VAR2),.VAR1(VAR1)); | apache-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_fmrv32im_axilm_0_0/synth/fmrv32im_artya7_fmrv32im_axilm_0_0.v | 6,838 | module MODULE1 (
VAR13,
VAR17,
VAR4,
VAR12,
VAR23,
VAR19,
VAR7,
VAR10,
VAR28,
VAR30,
VAR22,
VAR14,
VAR11,
VAR8,
VAR15,
VAR24,
VAR3,
VAR18,
VAR31,
VAR20,
VAR6,
VAR1,
VAR29,
VAR16,
VAR9,
VAR2,
VAR5,
VAR21,
VAR25
);
input wire VAR13;
input wire VAR17;
output wire [31 : 0] VAR4;
output wire [3 : 0] VAR12;
output wire [2 : ... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_afi_mux.v | 6,112 | module MODULE1(
VAR44,
VAR29,
VAR51,
VAR16,
VAR34,
VAR14,
VAR17,
VAR5,
VAR23,
VAR54,
VAR55,
VAR57,
VAR32,
VAR63,
VAR61,
VAR56,
VAR50,
VAR25,
VAR31,
VAR10,
VAR53,
VAR13,
VAR30,
VAR62,
VAR2,
VAR38,
VAR52,
VAR8,
VAR3,
VAR1,
VAR18,
VAR39,
VAR48,
VAR40,
VAR35,
VAR36,
VAR6,
VAR21,
VAR45,
VAR46,
VAR42,
VAR9,
VAR24,
VAR22,
VAR... | lgpl-3.0 |
dhytxz/PolyPC | hardware/ip_repo/hapara_axis_id_generator_1.0/hdl/hapara_axis_id_generator_v1_0_S00_AXI.v | 18,739 | module MODULE1 #
(
parameter integer VAR21 = 32,
parameter integer VAR29 = 4
)
(
input wire VAR22,
output wire VAR30,
output wire [VAR21 - 1 : 0] VAR50,
output wire [VAR21 - 1 : 0] VAR15,
output wire [VAR21 - 1 : 0] VAR44,
input wire VAR13,
input wire VAR28,
input wire [VAR29-1 : 0] VAR27,
input wire [2 : 0] VAR3,
inpu... | gpl-2.0 |
freecores/zet86 | rtl-model/alu.v | 12,090 | module MODULE7 (
input [31:0] VAR44,
input [15:0] VAR60,
output [31:0] out,
input [ 2:0] VAR114,
input [ 2:0] VAR68,
input [15:0] VAR124,
output [ 8:0] VAR71,
input VAR40,
input [15:0] VAR23,
input [15:0] VAR13,
input clk,
output VAR119
);
wire [15:0] VAR128, VAR130, VAR116, VAR46;
wire [8:0] VAR134;
wire [19:0] VAR122... | gpl-3.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | 49,867 | module MODULE1 (
VAR111,
VAR91,
VAR17,
VAR53,
VAR50,
VAR72,
VAR20,
VAR33,
VAR114,
VAR70,
VAR112,
VAR125,
VAR97,
VAR84,
VAR95,
VAR39,
VAR131,
VAR25,
VAR45,
VAR18,
VAR11,
VAR93,
VAR52,
VAR159,
VAR13,
VAR99,
VAR85
);
parameter VAR76 = 0;
parameter VAR147 = 0;
parameter VAR103 = 32;
parameter VAR143 = 20;
parameter VAR160 ... | gpl-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 58,188 | module MODULE1 (
input wire VAR13, input wire VAR293, input wire VAR86, input wire [31:0] VAR298, output wire VAR345, input wire [4:0] VAR307, input wire [31:0] VAR352, input wire VAR178, output wire [255:0] VAR65, output wire VAR341, input wire VAR159, input wire [255:0] VAR273, output wire [26:0] VAR234, output wire ... | mit |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_hbi.v | 2,034 | module MODULE1 (
VAR12, VAR5, VAR13, VAR4, VAR9, VAR10, VAR11, VAR14, VAR8, clk);
parameter VAR6 = 8;
parameter VAR7 = 8;
parameter VAR1 = 256;
input[VAR7-1:0] VAR12;
input VAR5;
output reg[VAR6-1:0] VAR13;
input[VAR7-1:0] VAR4;
input VAR9;
output reg[VAR6-1:0] VAR10;
input[VAR7-1:0] VAR11;
input VAR14;
output reg[VAR6... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.v | 2,339 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR3,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR3;
input VAR5;
VAR6 VAR7 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/eeprom_v1_06_a/hdl/verilog/OWM.v | 6,587 | module MODULE1 (
VAR25, VAR8, VAR83, VAR14, VAR22, VAR18, VAR91, VAR24,
VAR87, VAR56, VAR81,
VAR38, VAR55, VAR29, VAR13, VAR58, VAR30, VAR36, VAR71,
VAR5, VAR9, VAR77, VAR49, VAR41, VAR27, VAR42, VAR23,
VAR66, VAR68, VAR45, VAR16, VAR7, VAR82, VAR65, VAR26);
input [2:0] VAR25; input VAR8; input VAR83; input VAR14; inpu... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.functional.v | 1,462 | module MODULE1 (
VAR8 ,
VAR6,
VAR1,
VAR3,
VAR9,
VAR10
);
output VAR8 ;
input VAR6;
input VAR1;
input VAR3;
input VAR9;
input VAR10;
wire VAR5 ;
wire VAR2;
and VAR4 (VAR5 , VAR6, VAR1, VAR3, VAR9 );
or VAR7 (VAR2, VAR5, VAR10 );
buf VAR11 (VAR8 , VAR2 );
endmodule | apache-2.0 |
AmeerAbdelhadi/Binary-to-BCD-Converter | bcd7seg.v | 3,016 | module MODULE1 (
input [3:0] VAR1,
output reg [6:0] VAR2
);
always @(*) begin
case(VAR1)
4'h0 : VAR2 = 7'b1000000;
4'h1 : VAR2 = 7'b1111001;
4'h2 : VAR2 = 7'b0100100;
4'h3 : VAR2 = 7'b0110000;
4'h4 : VAR2 = 7'b0011001;
4'h5 : VAR2 = 7'b0010010;
4'h6 : VAR2 = 7'b0000010;
4'h7 : VAR2 = 7'b1111000;
4'h8 : VAR2 = 7'b000000... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.functional.v | 1,838 | module MODULE1( VAR15, VAR20, VAR2, VAR13, VAR19, VAR14, VAR9 );
input VAR19, VAR14, VAR9, VAR2, VAR15, VAR20;
output VAR13;
wire VAR18;
not VAR3( VAR18, VAR19 );
wire VAR7;
not VAR4( VAR7, VAR14 );
wire VAR24;
not VAR17( VAR24, VAR9 );
wire VAR6;
and VAR16( VAR6, VAR18, VAR7, VAR24 );
wire VAR22;
not VAR11( VAR22, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3.behavioral.pp.v | 1,837 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR5,
VAR12,
VAR10 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR5;
input VAR12;
input VAR10 ;
input VAR2 ;
wire VAR14 ;
wire VAR4;
nand VAR1 (VAR14 , VAR11, VAR6, VAR7 );
VAR3 VAR13 (VAR4, VAR14, VAR5, VAR12);
buf VAR9 (VAR8 , VAR4 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/fifo.v | 3,084 | module MODULE1 #(
parameter VAR7 = 3, VAR5 = 8
) (
input VAR4,
input VAR10,
input [VAR5-1:0] VAR13,
input VAR11,
input VAR12,
output [VAR5-1:0] VAR14,
input VAR16,
output VAR18,
output VAR2
);
wire [VAR7-1:0] VAR3;
wire [VAR7-1:0] VAR6;
wire VAR17;
wire VAR8;
wire VAR21, VAR19, VAR22, VAR1;
reg [VAR5-1:0] out = 0; reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.behavioral.pp.v | 7,501 | module MODULE1 (VAR5, VAR28, VAR15,
VAR42, VAR18, VAR20, VAR21, VAR26, VAR38, VAR35, VAR9, VAR16, VAR1,
VAR12, VAR29, VAR33, VAR7, VAR22, VAR13, VAR44, VAR4, VAR23,
VAR43, VAR2, VAR8, VAR34, VAR6);
output VAR5;
output VAR28;
inout VAR15;
inout VAR42;
inout VAR18;
inout VAR20;
inout VAR21;
inout VAR26;
inout VAR38;
inou... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkGbeWrk.v | 28,818 | module MODULE1(VAR21,
VAR77,
VAR161,
VAR125,
VAR113,
VAR99,
VAR132,
VAR147,
VAR168,
VAR62,
VAR164,
VAR76,
VAR46,
VAR130,
VAR167,
VAR55,
VAR103);
parameter [0 : 0] VAR111 = 1'b0;
input VAR21;
input VAR77;
input [2 : 0] VAR161;
input VAR125;
input [3 : 0] VAR113;
input [31 : 0] VAR99;
input [31 : 0] VAR132;
output [1 : 0... | lgpl-3.0 |
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