repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
nickdesaulniers/Omicron | instruction_fetch.v | 1,389 | module MODULE1(
input VAR7,
input VAR9,
input [6:0] VAR10,
input VAR1,
output [6:0] VAR4,
output [15:0] VAR3
);
reg [6:0] VAR11;
assign VAR4 = VAR11 + 1;
always@(posedge VAR7 or negedge VAR9) begin
if(!VAR9) begin
VAR11 <= 7'b0;
end else begin
if(VAR1) begin
VAR11 <= VAR10;
end else begin
VAR11 <= VAR4;
end
end
end
VAR... | gpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Lab6/debounce.v | 1,228 | module MODULE1(VAR1, VAR2, clk);
output VAR1; input VAR2; input clk;
reg [3:0] VAR3;
always @(posedge clk) begin
VAR3[3:1] <= VAR3[2:0];
VAR3[0] <= VAR2;
end
assign VAR1 = ((VAR3 == 4'b0000) ? 1'b0 : 1'b1);
endmodule | mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_3_stub.v | 1,485 | module MODULE1(VAR2, VAR6, VAR7, VAR3, din, VAR4, VAR5, dout, VAR1, VAR8)
;
input VAR2;
input VAR6;
input VAR7;
input VAR3;
input [9:0]din;
input VAR4;
input VAR5;
output [9:0]dout;
output VAR1;
output VAR8;
endmodule | mit |
atti92/heterogenhomework | project1/solution1/syn/verilog/fir_hw.v | 20,598 | module MODULE1 (
VAR102,
VAR30,
VAR34,
VAR82,
VAR146,
VAR158,
VAR23,
VAR45,
VAR160
);
parameter VAR32 = 1'b1;
parameter VAR46 = 1'b0;
parameter VAR81 = 9'b1;
parameter VAR5 = 9'b10;
parameter VAR138 = 9'b100;
parameter VAR94 = 9'b1000;
parameter VAR133 = 9'b10000;
parameter VAR41 = 9'b100000;
parameter VAR123 = 9'b1000... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR17 ,
VAR10 ,
VAR2,
VAR16,
VAR7 ,
VAR12
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR17 ;
input VAR10 ;
input VAR2;
input VAR16;
input VAR7 ;
input VAR12 ;
wire VAR13 ;
wire VAR15 ;
wire VAR11;
not VAR4 (VAR13 , VAR9 );
and VAR6 (VAR15 , VAR13, VAR1, VAR17, VAR10 );
VAR14 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v | 5,423 | module MODULE1 #
(
parameter VAR8 = 100
)
(
input clk,
input [1:0] VAR3,
input [1:0] VAR9,
input [5:0] din,
output reg [3:0] VAR2
);
reg VAR6;
reg [3:0] VAR4;
reg [3:0] VAR1;
reg [3:0] VAR7;
reg [3:0] VAR5;
always @(posedge clk)
always @(VAR3 or din or VAR6)
case (VAR3)
2'b00: VAR4 = {din[3], din[2], din[1], din[0]};
2... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.functional.pp.v | 1,072 | module MODULE1( VAR7, VAR1, VAR4, VAR9, VAR5 );
input VAR1, VAR7;
inout VAR9, VAR5;
output VAR4;
wire VAR3;
not VAR10( VAR3, VAR1 );
wire VAR8;
not VAR2( VAR8, VAR7 );
or VAR6( VAR4, VAR3, VAR8 );
endmodule | apache-2.0 |
SiLab-Bonn/pyBAR | firmware/mmc3_8chip_multi_tx_eth/src/mmc3_8chip_multi_tx_eth.v | 31,195 | module MODULE1(
input wire VAR264,
input wire VAR252,
output wire [3:0] VAR367,
output wire VAR93,
output wire VAR329,
input wire [3:0] VAR190,
input wire VAR5,
input wire VAR38,
output wire VAR343,
inout wire VAR103,
output wire VAR354,
output wire [7:0] VAR392,
output wire [7:0] VAR220, VAR164,
output wire [7:0] VAR3... | bsd-3-clause |
parallella/oh | common/hdl/oh_fifo_cdc.v | 2,240 | module MODULE1 # (parameter VAR3 = 104, parameter VAR26 = 32, parameter VAR4 = "VAR25" )
(
input VAR14, input VAR15, input VAR9, input [VAR3-1:0] VAR7, output VAR20, input VAR28, output reg VAR10, output [VAR3-1:0] VAR5, input VAR22, output VAR8, output VAR16, output VAR23 );
wire VAR1;
wire VAR2;
VAR17 #(.VAR4(VAR4),
... | mit |
ShepardSiegel/ocpi | rtl/mkWciTarget.v | 25,292 | module MODULE1(VAR61,
VAR22,
VAR144,
VAR43,
VAR123,
VAR95,
VAR94,
VAR131,
VAR160,
VAR91,
VAR133,
VAR138);
input VAR61;
input VAR22;
input [2 : 0] VAR144;
input VAR43;
input [3 : 0] VAR123;
input [31 : 0] VAR95;
input [31 : 0] VAR94;
output [1 : 0] VAR131;
output [31 : 0] VAR160;
output VAR91;
output [1 : 0] VAR133;
inp... | lgpl-3.0 |
mgohde/MiniMicroII | pipeBlockedU.v | 1,840 | module MODULE1(
VAR4,
VAR9,
VAR5,
VAR3,
VAR8,
VAR1
);
input [15:0] VAR4;
input [15:0] VAR9;
input [15:0] VAR5;
input [15:0] VAR3;
input [15:0] VAR8;
output VAR1;
wire [6:0] o1;
wire [6:0] o2;
wire [6:0] o3;
wire [6:0] o4;
wire [6:0] o5;
assign o1=VAR4[15:9];
assign o2=VAR9[15:9];
assign o3=VAR5[15:9];
assign o4=VAR3[15... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.functional.pp.v | 1,863 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR10 ,
VAR13 ,
VAR3,
VAR5,
VAR7 ,
VAR14
);
output VAR9 ;
input VAR12 ;
input VAR10 ;
input VAR13 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR14 ;
wire VAR1 ;
wire VAR8;
xor VAR2 (VAR1 , VAR12, VAR10, VAR13 );
VAR6 VAR11 (VAR8, VAR1, VAR3, VAR5);
buf VAR4 (VAR9 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.functional.v | 2,051 | module MODULE1 (
VAR8,
VAR7,
VAR2 ,
VAR17 ,
VAR11 ,
VAR3 ,
VAR10
);
input VAR8;
input VAR7;
output VAR2 ;
input VAR17 ;
input VAR11 ;
input VAR3 ;
input VAR10 ;
wire VAR10 VAR5 ;
wire VAR10 VAR12 ;
wire VAR4 ;
wire VAR9;
nor VAR13 (VAR5 , VAR3, VAR10 );
nor VAR16 (VAR12 , VAR17, VAR11 );
or VAR14 (VAR4 , VAR12, VAR5 );... | apache-2.0 |
subailong/miaow | src/verilog/rtl/fetch/pc_block.v | 10,578 | module MODULE1 (
VAR129,
VAR26,
wr,
VAR9,
VAR19,
VAR25,
clk,
rst
);
parameter VAR28 = 32;
input [31:0] VAR129;
input [5:0] VAR26;
input wr;
input clk, rst;
input VAR9;
input [5:0] VAR19;
output [32:0]VAR25;
wire write;
wire [31:0] VAR48;
wire [32:0] VAR17, VAR40;
wire [32:0] VAR56, VAR11;
wire [32:0] VAR52, VAR4;
wire ... | bsd-3-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/Rot_tst.v | 1,438 | module MODULE1;
reg clk;
reg rst;
reg enable;
reg [15:0] VAR8;
reg [15:0] VAR11;
reg [15:0] VAR4;
reg [15:0] VAR2;
reg [15:0] VAR1;
wire [31:0] VAR7;
wire [31:0] VAR3;
wire [31:0] VAR6;
wire VAR10;
VAR5 VAR9 (
.clk(clk),
.rst(rst),
.enable(enable),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.symbol.v | 1,392 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR5,
input VAR1
);
supply1 VAR6;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.blackbox.v | 1,295 | module MODULE1 (
VAR4 ,
VAR7,
VAR1,
VAR3
);
output VAR4 ;
output VAR7;
input VAR1;
input VAR3 ;
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_ss_444to422.v | 5,110 | module MODULE1 (
clk,
VAR7,
VAR21,
VAR3,
VAR6,
VAR15);
parameter VAR13 = 0;
parameter VAR10 = 16;
localparam VAR4 = VAR10 - 1;
input clk;
input VAR7;
input [VAR4:0] VAR21;
input [23:0] VAR3;
output [VAR4:0] VAR6;
output [15:0] VAR15;
reg VAR14 = 'd0;
reg [VAR4:0] VAR17 = 'd0;
reg [23:0] VAR12 = 'd0;
reg VAR16 = 'd0;
re... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_bram_reader_v1_0/axis_bram_reader.v | 3,421 | module MODULE1 #
(
parameter integer VAR17 = 32,
parameter integer VAR18 = 32,
parameter integer VAR20 = 10,
parameter VAR5 = "VAR13"
)
(
input wire VAR19,
input wire VAR29,
input wire [VAR20-1:0] VAR12,
output wire [VAR20-1:0] VAR14,
input wire VAR23,
output wire [VAR17-1:0] VAR22,
output wire VAR15,
output wire VAR30... | mit |
Elphel/x353 | compressor/csconvert18.v | 30,070 | module MODULE1(VAR105,
VAR107,
VAR29,
VAR17, VAR22, VAR28, din,
VAR43,
VAR34, VAR55, VAR67,
VAR35,
VAR12,
VAR31,
VAR104,
VAR102,
VAR25,
VAR57);
input VAR105; input VAR107; input VAR29; input VAR17;
input [ 9:0] VAR22; input [ 9:0] VAR28; input [ 7:0] din; input VAR43; output [7:0] VAR34; output [8:0] VAR55; output [7:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.behavioral.pp.v | 50,218 | module MODULE1 ( VAR58, VAR30, VAR83, VAR86, VAR78,
VAR72, VAR59, VAR27, VAR37, VAR74,
VAR29, VAR63,VAR53, VAR60, VAR46, VAR43, VAR14, VAR21, VAR71, VAR24,
VAR75, VAR42, VAR80, VAR61, VAR88, VAR33, VAR64, VAR10, VAR40, VAR32,
VAR6, VAR38, VAR44, VAR20, VAR82, VAR68, VAR73, VAR48, VAR56, VAR13 );
input VAR82;
input VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o_0.v | 2,448 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR6,
VAR1,
VAR7 ,
VAR12
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR12 ;
VAR8 VAR10 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VA... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/fifo.v | 7,418 | module MODULE1
parameter VAR28 = 32, parameter VAR4 = 1024, parameter VAR20 = 2
)
(
input VAR6, input VAR42,
input [VAR28-1:0] VAR2, input VAR7, output VAR31,
output [VAR28-1:0] VAR12, input VAR36, output VAR30 );
localparam VAR25 = 2**VAR26(VAR4);
localparam VAR16 = VAR19(VAR25);
wire [VAR20:0] VAR11;
wire VAR37;
wire... | bsd-3-clause |
parallella/oh | spi/hdl/axi_spi.v | 8,311 | module MODULE1(
VAR97, VAR38, VAR39, VAR19, VAR63,
VAR68, VAR32, VAR31, VAR60, VAR53,
VAR2, VAR83, VAR56, VAR1, VAR75,
VAR92,
VAR88, VAR66, VAR67, VAR26, VAR15,
VAR85, VAR65, VAR89, VAR76, VAR81,
VAR45, VAR42, VAR8, VAR25,
VAR100, VAR74, VAR54, VAR6, VAR10,
VAR27, VAR72, VAR91, VAR35,
VAR93, VAR58, VAR18, VAR13, VAR99,... | mit |
DougFirErickson/parallella-hw | fpga/old/eio_tx/hdl/eio_tx.v | 9,985 | module MODULE1 (
VAR65, VAR41, VAR67, VAR18, VAR3, VAR52,
VAR91, VAR69,
reset, VAR1, VAR82, VAR43, VAR84,
VAR72, VAR102, VAR62, VAR19, VAR54, VAR101,
VAR94, VAR7, VAR100, VAR106
);
parameter VAR56 = "VAR93";
output VAR65, VAR41; input reset;
input VAR1;
output VAR67, VAR18; output [7:0] VAR3, VAR52;
input VAR82, VAR43;... | gpl-3.0 |
kyzhai/NUNY | src/hardware/stage2_bb.v | 4,988 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
jotego/jt12 | hdl/jt12_pg_dt.v | 2,786 | module MODULE1(
input [ 2:0] VAR6,
input [10:0] VAR2,
input [ 2:0] VAR4,
output reg [ 4:0] VAR10,
output reg signed [5:0] VAR9
);
reg [5:0] VAR7;
reg [4:0] VAR5;
reg [5:0] VAR3;
reg [4:0] VAR8, VAR1;
always @(*) begin
VAR10 = { VAR6, VAR2[10], VAR2[10] ? (|VAR2[9:7]) : (&VAR2[9:7])};
case( VAR4[1:0] )
2'd1: VAR7 = { 1'... | gpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/vfabric_ceil.v | 2,306 | module MODULE1(VAR13, VAR9,
VAR12, VAR5, VAR14,
VAR10, VAR1, VAR4);
parameter VAR16 = 32;
parameter VAR18 = 4;
parameter VAR6 = 64;
input VAR13, VAR9;
input [VAR16-1:0] VAR12;
input VAR5;
output VAR14;
output [VAR16-1:0] VAR10;
output VAR1;
input VAR4;
reg [VAR18-1:0] VAR19;
wire [VAR16-1:0] VAR24;
wire VAR8;
wire VAR2... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_1master.v | 17,513 | module MODULE1
parameter VAR204 = 32, parameter VAR152 = 32, parameter VAR13 = 4)
(input VAR67,
input VAR175,
input [VAR204-1:0] VAR44,
output [VAR204-1:0] VAR22,
input [VAR152-1:0] VAR170,
input [VAR13-1:0] VAR41,
input VAR99,
input VAR167,
input VAR189,
output VAR14,
output VAR25,
output VAR79,
input [VAR204-1:0] VAR... | gpl-2.0 |
rurume/openrisc_vision_hardware | ISE/gpio_top.v | 30,367 | module MODULE1(
VAR87, VAR12, VAR63, VAR91, VAR58, VAR5, VAR64, VAR80,
VAR88, VAR25, VAR6, VAR68,
VAR84,
VAR65, VAR45, VAR31
, VAR24
);
parameter VAR77 = 32;
parameter VAR55 = VAR17+1;
parameter VAR33 = VAR3;
input VAR87; input VAR12; input VAR63; input [VAR55-1:0] VAR91; input [VAR77-1:0] VAR58; input [3:0] VAR5; inpu... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v | 11,336 | module MODULE1 #
(
parameter integer VAR37 = 32,
parameter integer VAR16 = 1,
parameter integer VAR4 = 32,
parameter VAR1 = "VAR13"
)
(
input wire clk ,
input wire reset ,
input wire [VAR37-1:0] VAR6,
input wire [VAR37/8-1:0] VAR34,
input wire VAR38,
output reg VAR20,
input wire VAR45,
input wire VAR40,
input wire VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.functional.v | 1,752 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR12 ,
VAR13 ,
VAR11
);
input VAR6 ;
input VAR7 ;
output VAR9 ;
input VAR12 ;
input VAR13 ;
input VAR11;
wire VAR5;
wire VAR1;
not VAR3 (VAR1 , VAR11 );
VAR2 VAR8 VAR4 (VAR5 , VAR13, VAR12, VAR1, VAR6, VAR7);
buf VAR10 (VAR9 , VAR5 );
endmodule | apache-2.0 |
praveendath92/securePUF | source/sirc_files/ethernetController.v | 88,726 | module MODULE1 #(
parameter VAR38 = 1,
parameter VAR75 = 1,
parameter VAR72 = 17,
parameter VAR148 = 13,
parameter VAR94 = 1,
parameter VAR26 = 48'hAAAAAAAAAAAA
)(
input wire VAR57, input wire reset,
input wire [7:0] VAR33, input wire VAR18, input wire VAR142, input wire VAR143, output reg VAR65,
output wire [7:0] VAR1... | gpl-2.0 |
superibk/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/nandc_ecc_dual_master.v | 8,722 | module MODULE1 #(
parameter VAR28 = VAR28,
parameter VAR20 = VAR20,
parameter VAR47 = VAR47,
parameter VAR87 = VAR87,
parameter VAR8 = VAR8,
parameter VAR22 = VAR22,
parameter VAR77 = VAR77,
parameter VAR45 = VAR45,
parameter VAR29 = VAR29,
parameter VAR26 = VAR26
) (
input wire VAR33, input wire VAR81,
input wire [2:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.pp.blackbox.v | 1,372 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR7,
VAR2 ,
VAR8 ,
VAR9 ,
VAR3
);
output VAR5 ;
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR7;
input VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_8.behavioral.v | 1,093 | module MODULE1( VAR4, VAR1 );
input VAR4;
output VAR1;
VAR2 VAR3(.VAR4(VAR4),.VAR1(VAR1));
VAR2 VAR5(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.functional.pp.v | 1,702 | module MODULE1( VAR21, VAR2, VAR4, VAR9, VAR15, VAR20, VAR19, VAR16 );
input VAR15, VAR20, VAR2, VAR4, VAR9;
inout VAR19, VAR16;
output VAR21;
wire VAR22;
not VAR23( VAR22, VAR15 );
wire VAR17;
not VAR13( VAR17, VAR20 );
wire VAR11;
and VAR3( VAR11, VAR22, VAR17 );
wire VAR7;
not VAR18( VAR7, VAR2 );
wire VAR10;
not VA... | apache-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_read_addr_in.v | 4,829 | module MODULE1
(
input VAR10, input [2:0] VAR7, input [14:0] VAR14, input [14:0] VAR17, input [14:0] VAR18, input [14:0] VAR13, output reg [4:0] VAR15,
output reg [4:0] VAR21,
output reg [4:0] VAR19,
output reg [4:0] VAR20
);
reg [6:0] VAR9;
reg [6:0] VAR2;
reg [6:0] VAR5;
reg [6:0] VAR3;
reg [14:0] VAR4;
reg [14:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.behavioral.v | 1,958 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR12 ,
VAR4 ,
VAR13 ,
VAR1 ,
VAR9,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR12 ;
input VAR4 ;
input VAR13 ;
input VAR1 ;
input VAR9;
input VAR6;
wire VAR13 VAR2 ;
wire VAR16 ;
wire VAR11;
and VAR3 (VAR2 , VAR4, VAR8, VAR12 );
or VAR7 (VAR16 , VAR2, VAR1, VAR13 );
VAR10 VAR15 (VAR11, V... | apache-2.0 |
hoglet67/opc | opc2/opc2cpu.v | 2,365 | module MODULE1( inout[7:0] VAR8, output[9:0] address, output VAR19, input clk, input VAR26);
parameter VAR10=0, VAR1=1, VAR29=2, VAR22=3, VAR7=4 ;
parameter VAR14=4'b1100, VAR13=4'b1000, VAR18=4'b1001, VAR12=4'b1010;
parameter VAR24 =4'b0100, VAR23=4'b0101, VAR11 =4'b0110, VAR9=4'b0111;
parameter VAR27 =4'b0000, VAR5=4... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/output_queues.v | 15,377 | module MODULE1
parameter VAR100 = 64,
parameter VAR94=VAR100/8,
parameter VAR38 = 2,
parameter VAR40 = 4,
parameter VAR24 = 8,
parameter VAR118 = 6,
parameter VAR16 = 13
)
( VAR88,
VAR51,
VAR109,
VAR77,
VAR61,
VAR113,
VAR6,
VAR31,
VAR68,
VAR66,
VAR97,
VAR19,
VAR112,
VAR50,
VAR28,
VAR92,
VAR121,
VAR27,
VAR117,
VAR46,
VA... | apache-2.0 |
dachdecker2/icoboard_ws2812b_display | memory.v | 5,146 | module MODULE1 (
input [0:0] clk, input [0:0] VAR9, input [16:0] VAR20, input [7:0] VAR12, input [0:0] VAR13, output reg [0:0] VAR17, output reg [0:0] VAR8, input [16:0] VAR1, output reg [7:0] VAR18, input [0:0] VAR19, output reg [0:0] VAR15, output reg [0:0] VAR6,
output reg [15:0] VAR10, output reg [0:0] VAR11, outpu... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/io_pins.v | 2,220 | module MODULE1
( inout wire [15:0] VAR14, inout wire [15:0] VAR13, inout wire [15:0] VAR19, inout wire [15:0] VAR5,
input wire [15:0] VAR18, input wire [15:0] VAR1, input wire [15:0] VAR16, input wire [15:0] VAR6,
input VAR8, input VAR4, input VAR2,
input [6:0] VAR20, input [31:0] VAR15, input VAR17);
reg [15:0] VAR24,... | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_1g_fifo.v | 9,606 | module MODULE1 #
(
parameter VAR106 = 8,
parameter VAR47 = (VAR106>8),
parameter VAR27 = (VAR106/8),
parameter VAR77 = 1,
parameter VAR30 = 64,
parameter VAR111 = 4096,
parameter VAR65 = 1,
parameter VAR117 = VAR65,
parameter VAR2 = 0,
parameter VAR59 = 4096,
parameter VAR63 = 1,
parameter VAR55 = VAR63,
parameter VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.behavioral.pp.v | 1,890 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR4,
VAR10,
VAR1,
VAR11 ,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR4;
input VAR10;
input VAR1;
input VAR11 ;
input VAR6 ;
wire VAR3 ;
wire VAR13;
VAR12 VAR7 (VAR3 , VAR9, VAR10, VAR1 );
VAR12 VAR8 (VAR13, VAR4, VAR10, VAR1 );
notif0 VAR5 (VAR2 , VAR3, VAR13);
endmodule | apache-2.0 |
eecsninja/duinocube-core | altera/sprite_ram_4Kx16.v | 11,037 | module MODULE1 (
VAR44,
VAR36,
VAR25,
VAR43,
VAR41,
VAR20,
VAR21,
VAR35,
VAR61,
VAR4,
VAR62);
input [11:0] VAR44;
input [8:0] VAR36;
input [1:0] VAR25;
input VAR43;
input VAR41;
input [15:0] VAR20;
input [127:0] VAR21;
input VAR35;
input VAR61;
output [15:0] VAR4;
output [127:0] VAR62;
tri1 [1:0] VAR25;
tri1 VAR43;
tri... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_phy_write.v | 15,959 | module MODULE1 #
(
parameter VAR31 = 72,
parameter VAR22 = 1,
parameter VAR34 = 0,
parameter VAR4 = 5,
parameter VAR17 = 0,
parameter VAR50 = 1,
parameter VAR51 = 1,
parameter VAR11 = 1
)
(
input VAR67,
input VAR36,
input VAR62,
input [(2*VAR31)-1:0] VAR25,
input [(2*VAR31/8)-1:0] VAR38,
input VAR35,
input VAR27,
input... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_TX_CLK_DIV.v | 2,217 | module MODULE1 (
address,
VAR8,
clk,
VAR7,
VAR2,
VAR9,
VAR5,
VAR1
)
;
output [ 6: 0] VAR5;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR7;
input VAR2;
input [ 31: 0] VAR9;
wire VAR3;
reg [ 6: 0] VAR4;
wire [ 6: 0] VAR5;
wire [ 6: 0] VAR6;
wire [ 31: 0] VAR1;
assign VAR3 = 1;
assign VAR6 ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/d_SC_deviders_s_lfs_XOR.v | 13,219 | module MODULE3(VAR7, VAR4, VAR3);
parameter [0:12] VAR8 = 13'b1001100100001;
input wire VAR7;
input wire [VAR5-1:0] VAR4;
output wire [VAR5-1:0] VAR3;
wire VAR1;
assign VAR1 = VAR4[VAR5-1];
assign VAR3[0] = VAR7 ^ VAR1;
genvar VAR2;
generate
for (VAR2=1; VAR2<VAR5; VAR2=VAR2+1)
begin: VAR6
if (VAR8[VAR2] == 1)
begin
as... | gpl-3.0 |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_wb.v | 12,117 | module MODULE1 (clk, VAR18,
VAR5, VAR16, VAR26, VAR25, VAR11,
VAR13, VAR6, VAR24, VAR10, VAR14, VAR7, VAR17,
VAR21, VAR4 );
input clk;
input VAR18;
input VAR5;
input VAR16;
input VAR26;
input [3:0] VAR17;
input [VAR9-1:0] VAR11;
input [7:0] VAR6; output [7:0] VAR24;
reg [7:0] VAR24;
wire [7:0] VAR6;
reg [7:0] VAR15;
re... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/fifo_packer_64.v | 5,060 | module MODULE1 (
input VAR11,
input VAR23,
input [63:0] VAR10, input [1:0] VAR4, input VAR20, input VAR3, input VAR2, output [63:0] VAR22, output VAR16, output VAR24, output VAR19, output VAR17 );
reg [1:0] VAR6=0, VAR6=0;
reg VAR13=0, VAR13=0;
reg VAR7=0, VAR7=0;
reg VAR21=0, VAR21=0;
reg VAR14=0, VAR14=0;
reg [95:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.functional.v | 1,273 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
wire VAR2;
not VAR5 (VAR2, VAR4 );
buf VAR1 (VAR3 , VAR2 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_stub.v | 2,357 | module MODULE1(VAR18, VAR5, VAR4,
VAR17, VAR19, VAR3, VAR6, VAR20, VAR11,
VAR12, VAR16, VAR14, VAR7, VAR15, VAR10,
VAR8, VAR13, VAR2, VAR9, VAR1)
;
input VAR18;
input VAR5;
input [8:0]VAR4;
input VAR17;
output VAR19;
input [31:0]VAR3;
input [3:0]VAR6;
input VAR20;
output VAR11;
output [1:0]VAR12;
output VAR16;
input VA... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/bank_cntrl.v | 25,516 | module MODULE1 #
(
parameter VAR110 = 100,
parameter VAR10 = "VAR52",
parameter VAR49 = 3,
parameter VAR136 = 2,
parameter VAR61 = "8",
parameter VAR65 = 12,
parameter VAR23 = 5,
parameter VAR125 = 8,
parameter VAR106 = "VAR42",
parameter VAR24 = "VAR104",
parameter VAR17 = 4,
parameter VAR4 = 4,
parameter VAR29 = 2,
p... | lgpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_phy_alt_mem_phy_pll_bb.v | 18,017 | module MODULE1 (
VAR5,
VAR11,
VAR2,
VAR12,
VAR8,
VAR3,
VAR4,
VAR6,
VAR1,
VAR10,
VAR13,
VAR7,
VAR9,
VAR14);
input VAR5;
input VAR11;
input [3:0] VAR2;
input VAR12;
input VAR8;
input VAR3;
output VAR4;
output VAR6;
output VAR1;
output VAR10;
output VAR13;
output VAR7;
output VAR9;
output VAR14;
tri0 VAR5;
tri0 [3:0] VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b_4.v | 2,300 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR2 ,
VAR6 ,
VAR4 ,
VAR7,
VAR11,
VAR1 ,
VAR5
);
output VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR7;
input VAR11;
input VAR1 ;
input VAR5 ;
VAR8 VAR9 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_top.v | 27,246 | module MODULE1(
VAR362, VAR79, VAR162, VAR397,
VAR310,
VAR155,
VAR247,
VAR53, VAR329, VAR57, VAR342, VAR281, VAR63,
VAR311, VAR209, VAR52, VAR56, VAR327, VAR330,
VAR387,
VAR388, VAR364,
VAR288, VAR274, VAR54, VAR231, VAR160, VAR36,
VAR308, VAR359, VAR180, VAR226, VAR83, VAR31,
VAR67,
VAR273, VAR275,
VAR250, VAR173, VAR... | gpl-3.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_cfgrs.v | 10,880 | module MODULE1
parameter VAR7 = "VAR57",
parameter VAR27 = "VAR57",
parameter VAR90 = "VAR57",
parameter VAR18 = "VAR38",
parameter VAR17 = 5,
parameter VAR6 = 9,
parameter VAR1 = 2,
parameter VAR2 = "VAR38",
parameter VAR14 = 6,
parameter VAR101 = 1,
parameter VAR87 = "VAR38",
parameter VAR98 = 5,
parameter VAR54 = 9,... | mpl-2.0 |
takeshineshiro/fpga_linear_128 | IMG_BUFFER_bb.v | 7,895 | module MODULE1 (
VAR4,
VAR1,
VAR6,
VAR3,
VAR2,
VAR5,
VAR7);
input [7:0] VAR4;
input [10:0] VAR1;
input VAR6;
input [10:0] VAR3;
input VAR2;
input VAR5;
output [7:0] VAR7;
tri1 VAR5;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.functional.v | 1,930 | module MODULE1 (
VAR10,
VAR7,
VAR1 ,
VAR14 ,
VAR11 ,
VAR4 ,
VAR12
);
input VAR10;
input VAR7;
output VAR1 ;
input VAR14 ;
input VAR11 ;
input VAR4 ;
input VAR12 ;
wire VAR12 VAR8 ;
wire VAR5 ;
wire VAR2;
and VAR13 (VAR8 , VAR4, VAR14, VAR11 );
nor VAR3 (VAR5 , VAR12, VAR8 );
VAR6 VAR9 (VAR2, VAR5, VAR10, VAR7);
buf VAR... | apache-2.0 |
dwaipayanBiswas/ECG-feature-extraction-using-DWT | level2arch.v | 1,481 | module MODULE1 (VAR4,clk,VAR9);
reg signed [15:0] VAR3,VAR5;
input [15:0] VAR4;
input clk, VAR9;
wire clk, VAR9;
reg [15:0] VAR1, VAR2;
reg [2:0] VAR7;
reg [8:0] VAR11;
reg [8:0] VAR12;
reg [15:0] VAR10 [0:VAR8-2];
integer VAR6;
always @(posedge clk or negedge VAR9)
if (!VAR9)
begin
VAR1 <= 0;
VAR2 <= 0;
VAR3 <= 0;
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.pp.blackbox.v | 1,299 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
wsoltys/AtomFpga | mist/user_io.v | 11,338 | module MODULE1 #(parameter VAR32=0) (
input [(8*VAR32)-1:0] VAR5,
input VAR20,
input VAR6,
output reg VAR61,
input VAR27,
output reg [7:0] VAR59,
output reg [7:0] VAR51,
output reg [15:0] VAR53,
output reg [15:0] VAR39,
output [1:0] VAR49,
output [1:0] VAR50,
output VAR42,
output reg [7:0] VAR33,
input [31:0] VAR63,
in... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_top.v | 66,885 | module MODULE1 #
(
parameter VAR8 = 100, parameter VAR101 = "0", parameter VAR300 = 3, parameter VAR62 = "8", parameter VAR111 = "VAR342", parameter VAR161 = "VAR177", parameter VAR246 = 1, parameter VAR390 = 5,
parameter VAR96 = 12, parameter VAR26 = 1, parameter VAR171 = 1, parameter VAR350 = 5,
parameter VAR250 = 8,... | mit |
HFoxtail/Mu80 | trunk/rom.v | 2,745 | module MODULE1 (VAR29, VAR67, VAR59, VAR41, VAR39, VAR12, VAR4);
input VAR59;
input [13:0] VAR67;
input [7:0] VAR41;
input VAR39;
input [13:0] VAR29;
output [7:0] VAR12;
output [7:0] VAR4;
tri1 VAR59;
tri0 VAR10;
tri0 VAR47;
wire [7:0] VAR33;
wire [7:0] VAR14;
wire [7:0] VAR12 = VAR33[7:0];
wire [7:0] VAR4 = VAR14[7:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.pp.blackbox.v | 1,245 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR3,
VAR5,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/phyIniCommand0_and.v | 1,183 | module MODULE1
(
input [(VAR1-1):0] VAR7,
input [(VAR5-1):0] addr,
input VAR2, clk,
output [(VAR1-1):0] VAR3
);
reg [VAR1-1:0] VAR6[2**VAR5-1:0];
reg [VAR5-1:0] VAR4;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.functional.pp.v | 1,819 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR14,
VAR13,
VAR12 ,
VAR8
);
output VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR14;
input VAR13;
input VAR12 ;
input VAR8 ;
wire VAR3 ;
wire VAR11;
or VAR10 (VAR3 , VAR6, VAR1, VAR4 );
VAR9 VAR7 (VAR11, VAR3, VAR14, VAR13);
buf VAR5 (VAR2 , VAR11 );
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/vio_0/vio_0_stub.v | 1,365 | module MODULE1(clk, VAR1, VAR4, VAR2, VAR3)
;
input clk;
output [0:0]VAR1;
output [0:0]VAR4;
output [0:0]VAR2;
output [0:0]VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.pp.symbol.v | 1,409 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR4 ,
input VAR5 ,
input VAR3 ,
output VAR8 ,
input VAR2 ,
input VAR10,
input VAR6,
input VAR9
);
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_rec_fifo.v | 13,697 | module MODULE1(
rst,
VAR165,
VAR103,
din,
VAR246,
VAR233,
dout,
VAR390,
VAR130,
VAR15,
VAR420,
VAR340,
VAR366,
VAR44
);
input rst;
input VAR165;
input VAR103;
input [127 : 0] din;
input VAR246;
input VAR233;
output [255 : 0] dout;
output VAR390;
output VAR130;
output VAR15;
output VAR420;
output [10 : 0] VAR340;
output... | gpl-2.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/LX150_comm_tweaks/hdl/sha256_pipes2.v | 5,372 | module MODULE2 ( clk, VAR4, VAR5, out );
parameter VAR10 = 64;
input clk;
input [255:0] VAR4;
input [511:0] VAR5;
output [255:0] out;
localparam VAR7 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v | 2,301 | module MODULE1 (
address,
VAR3,
clk,
VAR6,
VAR9,
VAR7,
VAR5,
VAR8
)
;
output [ 7: 0] VAR5;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR6;
input VAR9;
input [ 31: 0] VAR7;
wire VAR2;
reg [ 7: 0] VAR1;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR4;
wire [ 31: 0] VAR8;
assign VAR2 = 1;
assign VAR4 ... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/soc_system_bb.v | 3,358 | module MODULE1 (
VAR37,
VAR32,
VAR13,
VAR26,
VAR38,
VAR40,
VAR29,
VAR23,
VAR19,
VAR51,
VAR47,
VAR33,
VAR43,
VAR9,
VAR46,
VAR1,
VAR28,
VAR24,
VAR36,
VAR7,
VAR27,
VAR48,
VAR11,
VAR34,
VAR39,
VAR3,
VAR5,
VAR41,
VAR6,
VAR20,
VAR44,
VAR17,
VAR12,
VAR25,
VAR4,
VAR50,
VAR49,
VAR52,
VAR16,
VAR22,
VAR42,
VAR2,
VAR10,
VAR35,
VAR... | apache-2.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/DE2_115_makomk_mod/fpgaminer_top.v | 5,033 | module MODULE1 (VAR21);
parameter VAR29 = VAR27;
parameter VAR29 = 0;
localparam [5:0] VAR30 = (6'd1 << VAR29);
localparam [31:0] VAR19 = (32'd1 << (7 - VAR29)) + 32'd1;
input VAR21;
reg [255:0] state = 0;
reg [511:0] VAR23 = 0;
reg [31:0] VAR8 = 32'h00000000;
wire VAR5;
VAR17 VAR40 (VAR21, VAR5);
assign VAR5 = VAR21;
... | gpl-3.0 |
sheiksadique/USB-Uart | UART_TX.v | 2,206 | module MODULE1(
input [7:0] VAR2, input VAR4,
input VAR3, input VAR6,
input VAR7,
output reg VAR5
);
reg [3:0] state=0;
reg [7:0] VAR1=0;
always @(posedge VAR6)
begin
if (VAR4 & state<2) begin
VAR1 <= VAR2; end else if (state[3] & VAR7) begin
VAR1 <= (VAR1 >> 1); end
case(state)
4'b0000: if(VAR4 & VAR3) state <= 4'b001... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9250/axi_ad9250_pnmon.v | 6,678 | module MODULE1 (
VAR10,
VAR13,
VAR15,
VAR12,
VAR4);
input VAR10;
input [27:0] VAR13;
output VAR15;
output VAR12;
input [ 3:0] VAR4;
reg [27:0] VAR7 = 'd0;
reg [27:0] VAR6 = 'd0;
wire [27:0] VAR9;
function [27:0] VAR11;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[22] ^ din[17];
dout[26] = din[21] ^ din[16];
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.pp.symbol.v | 1,376 | module MODULE1 (
input VAR10 ,
input VAR7 ,
input VAR1 ,
input VAR6 ,
output VAR4 ,
input VAR5 ,
input VAR11 ,
input VAR9 ,
input VAR3,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_4.v | 2,150 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2,
VAR3,
VAR1,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR1;
input VAR8 ;
input VAR4 ;
VAR9 VAR5 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR7 ,
VAR2
);
output VAR6 ;... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/ShiftReg16.v | 1,138 | module MODULE1(
input clk,
input VAR8,
input signed [15:0] din,
input [4:0] VAR10,
output reg signed [15:0] dout = 16'd0
);
parameter VAR6 = 32;
reg [15:0] VAR5 [0:VAR6-3];
reg [4:0] VAR2 = 5'd0;
reg VAR3 = 1'b1;
integer VAR1;
integer VAR4;
VAR9 for (VAR4=0; VAR4 < (VAR6-2); VAR4=VAR4+1) VAR5[VAR4]=16'd0; VAR7
always @... | gpl-3.0 |
spesialstyrker/boula | src/rx_fsm.v | 15,287 | module MODULE1(
input wire VAR16,
input wire VAR12, input wire VAR2, input wire [VAR17 - 1:0] VAR11,
input wire VAR7,
output reg VAR21,
input wire VAR14,
output reg VAR10,
input wire [1:0] VAR4, output reg [2:0] VAR9,
input wire VAR20, output reg VAR5, output reg VAR19, output reg VAR6
);
parameter VAR17 = 8;
localpara... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.v | 2,163 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR3,
VAR5,
VAR8 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR8 ;
input VAR2 ;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR3;
supply0 VAR5;... | apache-2.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/RegWGPR.v | 46,748 | module MODULE1(
VAR19, VAR91,
VAR208, VAR102, VAR213, VAR43,
VAR35, VAR280, VAR148, VAR110,
VAR104, VAR164, VAR53, VAR209,
VAR262, VAR268, VAR287, VAR48,
VAR216, VAR153, VAR299, VAR191,
VAR304, VAR270, VAR88, VAR319, VAR62,
VAR225, VAR40, VAR38, VAR12, VAR247,
VAR300, VAR11, VAR229, VAR126, VAR24,
VAR261, VAR303, VAR26... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/writeUSBWireData.v | 8,898 | module MODULE1 (
VAR2,
VAR16,
VAR23,
VAR15,
VAR7,
VAR28,
VAR17,
VAR12,
VAR24,
clk,
rst
);
input [1:0] VAR2;
input VAR15;
input VAR17;
input clk;
input VAR24;
input rst;
output [1:0] VAR16;
output VAR23;
output VAR7;
output VAR28;
output VAR12;
wire [1:0] VAR2;
reg [1:0] VAR16;
reg VAR23;
wire VAR15;
reg VAR7;
reg VAR28... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/bless_mc/merge.v | 4,316 | module MODULE1(
VAR34,
VAR27,
VAR24, VAR22,
VAR35,
VAR36,
VAR6,
VAR20, VAR1,
VAR32,
VAR33,
VAR17,
VAR31, VAR4,
VAR28,
VAR19,
VAR13,
VAR21, VAR8,
VAR9,
VAR30,
VAR12,
VAR16, VAR25,
VAR29,
VAR2,
VAR15,
VAR11,
VAR7,
VAR5,
VAR18
);
input VAR34, VAR36, VAR33, VAR19, VAR30;
input [VAR10-1:0] VAR27, VAR6, VAR17, VAR13, VAR12;
... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cmn/block_ram/single_port_ram_sync.v | 2,372 | module MODULE1
parameter VAR4 = 6,
parameter VAR3 = 8
)
(
input wire clk,
input wire VAR2,
input wire [VAR4-1:0] VAR7,
input wire [VAR3-1:0] VAR8,
output wire [VAR3-1:0] VAR5
);
reg [VAR3-1:0] VAR1 [2**VAR4-1:0];
reg [VAR4-1:0] VAR6;
always @(posedge clk)
begin
if (VAR2)
VAR1[VAR7] <= VAR8;
VAR6 <= VAR7;
end
assign VAR... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port.v | 9,869 | module MODULE1 #(
parameter VAR39 = 3
)
(
input VAR25,
input VAR44,
input [31:0] VAR95,
input VAR75,
input VAR31,
input [2:0] VAR78,
input [1:0] VAR59,
input VAR19,
input [3:0] VAR93,
input [31:0] VAR64,
output [31:0] VAR107,
output VAR37,
input VAR53,
input VAR34,
input [31:0] VAR45,
output [31:0] VAR66,
input [31:0] ... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/phy/phy_top.v | 54,043 | module MODULE1 #
(
parameter VAR171 = 100,
parameter VAR174 = 2, parameter VAR62 = 3333, parameter VAR34 = 300.0, parameter VAR268 = "VAR236", parameter [7:0] VAR238 = 8'b00000001,
parameter [7:0] VAR66 = 8'b00000000,
parameter VAR279 = 2, parameter VAR255 = 1, parameter VAR9 = 10, parameter VAR166 = 1, parameter VAR24... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.blackbox.v | 1,300 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR1;
supply1 VAR6;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/rc4.v | 3,247 | module MODULE1(clk, VAR11, VAR5, ready, VAR2, enable);
input clk;
input VAR11;
output reg [7:0] VAR5;
output reg ready;
input [7:0] VAR2; input enable;
reg [7:0] VAR1;
reg [7:0] VAR4[0:255];
reg [3:0] state;
reg [7:0] VAR10[0:255];
reg [7:0] VAR9;
reg [7:0] VAR3;
reg [7:0] VAR8;
reg [7:0] VAR7;
assign VAR6 = ready; | mit |
pwwu/FPGA | VGAbased/final/vga_game_text_top.v | 3,853 | module MODULE1
(
input wire clk, reset,
input wire [1:0] VAR8,
output wire VAR18, VAR13,
output wire [2:0] VAR26
);
localparam [1:0]
VAR30 = 2'b00,
VAR25 = 2'b01,
VAR28 = 2'b10,
VAR9 = 2'b11;
reg [1:0] VAR14, VAR16;
wire [9:0] VAR29, VAR7;
wire VAR22, VAR6;
wire [3:0] VAR1;
wire [2:0] VAR27;
reg [2:0] VAR20, VAR15;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.pp.blackbox.v | 1,434 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR4,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR4;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/imports/common/reg_ro_4burst.v | 2,259 | module MODULE1(
input wire clk,
input wire [15:0] VAR6, input wire [18:0] VAR1,
input wire [2:0] VAR13, input wire VAR12, input wire VAR2, input wire VAR17, input wire [63:0] VAR15,
output reg [15:0] VAR8, output wire VAR3
);
reg [2:0] VAR16;
reg VAR9;
reg [15:0] VAR14;
reg VAR4;
reg [2:0] VAR18;
reg VAR7;
reg VAR5;
re... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2_2.v | 2,086 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR4 ,
VAR1,
VAR9,
VAR2 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR9;
input VAR2 ;
input VAR7 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6,
VAR8,
VAR4
);
output VAR6;
... | apache-2.0 |
jmahler/EECE344-Digital_System_Design | lab03/CPLD/led_ctl.v | 1,612 | module MODULE1(
input VAR5,
VAR8,
VAR4,
VAR3,
inout [7:0] VAR1,
output reg [7:0] VAR7);
assign VAR1 = (~(VAR3 | VAR5 | ~VAR8)) ? ~(VAR7) : 8'VAR6;
wire VAR2;
assign VAR2 = VAR8 | VAR3;
always @(negedge VAR4, posedge VAR2) begin
if (~VAR4)
VAR7 <= ~(8'h00);
end
else
VAR7 <= ~(VAR1);
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR9 ,
input VAR4 ,
output VAR7 ,
input VAR8 ,
input VAR3,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
JakeMercer/mac | rx.v | 5,550 | module MODULE1 #(
parameter VAR2 = 3'h0,
parameter VAR26 = 3'h1,
parameter VAR6 = 3'h2,
parameter VAR7 = 3'h3,
parameter VAR34 = 3'h4,
parameter VAR39 = 3'h5,
parameter VAR25 = 3'h6
)(
input reset,
input VAR3,
input VAR40,
input VAR4,
input [7:0] VAR17,
input VAR32,
output reg [7:0] VAR36,
output reg VAR33,
output reg ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_3/zqynq_lab_1_design_auto_pc_3_stub.v | 5,743 | module MODULE1(VAR35, VAR6, VAR60, VAR12,
VAR55, VAR31, VAR3, VAR54, VAR27, VAR36,
VAR48, VAR13, VAR45, VAR25, VAR42, VAR15, VAR75,
VAR17, VAR77, VAR43, VAR32, VAR58, VAR23, VAR76,
VAR49, VAR53, VAR20, VAR30, VAR16, VAR72,
VAR14, VAR1, VAR8, VAR50, VAR34, VAR41, VAR4,
VAR22, VAR63, VAR64, VAR10, VAR71, VAR73, VAR46,
VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/872e0473ecb52965/ip_design_axi_gpio_0_0_stub.v | 2,378 | module MODULE1(VAR1, VAR2, VAR19,
VAR11, VAR21, VAR9, VAR4, VAR14, VAR12,
VAR18, VAR6, VAR8, VAR17, VAR13, VAR10,
VAR7, VAR15, VAR16, VAR3, VAR22, VAR20, VAR5)
;
input VAR1;
input VAR2;
input [8:0]VAR19;
input VAR11;
output VAR21;
input [31:0]VAR9;
input [3:0]VAR4;
input VAR14;
output VAR12;
output [1:0]VAR18;
output V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.behavioral.v | 1,512 | module MODULE1 (
VAR2 ,
VAR12,
VAR6,
VAR4
);
output VAR2 ;
input VAR12;
input VAR6;
input VAR4;
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR13 ;
wire VAR8 ;
wire VAR10;
or VAR5 (VAR8 , VAR6, VAR12 );
and VAR11 (VAR10, VAR8, VAR4 );
buf VAR9 (VAR2 , VAR10 );
endmodule | apache-2.0 |
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