repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
joshtm00/Verificaci-n-de-Circuitos-Digitales | LIFO_FIFO/ram.v | 1,170 | module MODULE1 (VAR3, VAR7, VAR8, VAR1, VAR9, VAR6, clk );
parameter VAR2 = 32;
parameter VAR4 = 11;
parameter VAR5 = 2048;
input [VAR2-1:0] VAR3;
input [VAR4-1:0] VAR1;
input [VAR4-1:0] VAR8;
input VAR9;
input VAR6;
input clk;
output reg [VAR2-1:0] VAR7;
reg [VAR2-1:0] MODULE1 [0:VAR5 - 1];
always @ (posedge clk) begi... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_vc_alloc_sep_of.v | 21,263 | module MODULE1
(clk, reset, VAR57, VAR94, VAR95, VAR17,
VAR52, VAR33, VAR55, VAR18, VAR12,
VAR38, VAR26);
parameter VAR54 = 2;
parameter VAR74 = 2;
localparam VAR71 = VAR54 * VAR74;
parameter VAR53 = 1;
localparam VAR40 = VAR71 * VAR53;
parameter VAR32 = 5;
parameter VAR109 = VAR7;
parameter VAR8 = VAR97;
input clk;
in... | gpl-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/decode/decode.v | 13,643 | module MODULE1(
VAR87,
VAR5,
VAR4,
VAR24,
VAR136,
VAR148,
VAR30,
VAR145,
VAR29,
VAR61,
VAR108,
VAR2,
VAR157,
VAR106,
VAR40,
VAR73,
VAR57,
VAR60,
VAR158,
VAR116,
VAR64,
VAR113,
VAR86,
VAR146,
VAR102,
VAR172,
VAR160,
VAR101,
VAR38,
VAR173,
VAR167,
VAR122,
VAR65,
VAR12,
VAR118,
VAR104,
VAR54,
clk,
rst
);
input clk;
input ... | bsd-3-clause |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/xillybus_core.v | 2,630 | module MODULE1
(
input VAR2,
input [7:0] VAR62,
input [15:0] VAR12,
input [4:0] VAR57,
input [15:0] VAR26,
input [2:0] VAR44,
input VAR39,
input [15:0] VAR5,
input [63:0] VAR10,
input [7:0] VAR52,
input VAR29,
input VAR67,
input VAR50,
input [11:0] VAR7,
input [7:0] VAR22,
input VAR63,
input VAR14,
input VAR15,
input V... | mit |
bbrown1867/PresentLWC | hw/present_encrypt_sbox.v | 2,121 | module MODULE1 (
output reg [3:0] VAR2,
input [3:0] VAR1
);
always @(VAR1)
case (VAR1)
4'h0 : VAR2 = 4'hC;
4'h1 : VAR2 = 4'h5;
4'h2 : VAR2 = 4'h6;
4'h3 : VAR2 = 4'hB;
4'h4 : VAR2 = 4'h9;
4'h5 : VAR2 = 4'h0;
4'h6 : VAR2 = 4'hA;
4'h7 : VAR2 = 4'hD;
4'h8 : VAR2 = 4'h3;
4'h9 : VAR2 = 4'hE;
4'hA : VAR2 = 4'hF;
4'hB : VAR2 =... | mit |
ZenoFuturista/fpga-shovel-and-pickaxe | verilog/sha_miner/altera_modules.v | 3,551 | module MODULE4 (clk, in, out);
parameter VAR6 = 32;
parameter VAR3 = 64;
input clk;
input [(VAR6-1):0] in;
output [(VAR6-1):0] out;
reg [(VAR6-1):0] VAR4[0:(VAR3-1)];
always@(posedge clk) begin
VAR4[1:(VAR3-1)] <= VAR4[0:(VAR3-2)];
VAR4[0] <= in;
end
assign out = VAR4[VAR3-1];
endmodule
module MODULE1 (clk, in, out);
p... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/Freq_Count_Top.v | 1,713 | module MODULE1(
input VAR7,VAR4,
output reg [63:0] VAR2,
input VAR3
);
reg VAR10; wire VAR5;
reg VAR6;
reg VAR12;
parameter VAR9 = 50000000;
parameter VAR8 = 100000000;
reg [31:0] VAR1;
always@(posedge VAR7 or negedge VAR3)begin
if(!VAR3)begin
VAR1 <= 32'b0;
VAR10 <= 1'b0;
end
else begin
VAR1 <= VAR1 + 1'b1;
if(VAR1 ==... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.functional.v | 1,191 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
output VAR4;
pullup VAR1 (VAR3 );
pulldown VAR2 (VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.blackbox.v | 1,203 | module MODULE1 (
VAR1,
VAR2,
VAR5
);
output VAR1;
input VAR2;
input VAR5;
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/response_handler.v | 3,386 | module MODULE1 (
input clk,
input VAR13,
input VAR3,
output VAR15,
input [1:0] VAR10,
output reg [VAR5-1:0] VAR8,
input [VAR5-1:0] VAR12,
input VAR16,
input enable,
output reg VAR2,
input VAR4,
output VAR11,
input VAR7,
output VAR1,
output [1:0] VAR6
);
parameter VAR5 = 3;
assign VAR6 = VAR10;
assign VAR1 = VAR4;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.behavioral.pp.v | 1,911 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR1,
VAR6,
VAR3 ,
VAR11
);
output VAR9 ;
output VAR2 ;
input VAR1;
input VAR6;
input VAR3 ;
input VAR11 ;
wire VAR4 ;
wire VAR7;
pullup VAR13 (VAR4 );
VAR8 VAR12 (VAR9 , VAR4, VAR1 );
pulldown VAR5 (VAR7);
VAR10 VAR14 (VAR2 , VAR7, VAR6);
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/branches/avendor/fpu_div.v | 18,460 | module MODULE1( clk, rst, enable, VAR6, VAR18, VAR30, VAR37,
VAR41);
input clk;
input rst;
input enable;
input [63:0] VAR6;
input [63:0] VAR18;
output VAR30;
output [55:0] VAR37;
output [11:0] VAR41;
parameter VAR20 = 53;
reg [53:0] VAR52;
reg [53:0] VAR45;
reg VAR35;
reg VAR66;
reg VAR78;
reg VAR39;
reg VAR55;
reg VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.behavioral.pp.v | 1,832 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR3,
VAR4,
VAR1 ,
VAR8
);
output VAR9 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR8 ;
wire VAR7 ;
wire VAR10;
buf VAR11 (VAR7 , VAR5 );
VAR6 VAR12 (VAR10, VAR7, VAR3, VAR4);
buf VAR2 (VAR9 , VAR10 );
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/ctrl/qmem_decoder.v | 2,619 | module MODULE1 #(
parameter VAR8 = 32, parameter VAR13 = 32, parameter VAR22 = VAR13/8, parameter VAR11 = 2 )(
input wire clk,
input wire rst,
input wire VAR9,
input wire VAR12,
input wire [VAR8-1:0] VAR21,
input wire [VAR22-1:0] VAR7,
input wire [VAR13-1:0] VAR3,
output wire [VAR13-1:0] VAR16,
output wire VAR10,
outpu... | gpl-3.0 |
donnaware/AGC | rtl/de0/modules/ng_CRG.v | 3,731 | module MODULE1(
input VAR20, input [100:0] VAR9, input [ 15:0] VAR7, output [ 15:0] VAR4, output [ 15:0] VAR6, output [ 15:0] VAR5, output [ 15:0] VAR15 );
reg [ 15:0] VAR2; reg [ 15:0] VAR16; reg [ 15:0] VAR11; reg [ 15:0] VAR12;
assign VAR4 = VAR2;
assign VAR6 = VAR12;
assign VAR5 = VAR16;
assign VAR15 = VAR11;
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4_2.v | 2,126 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR2 ,
VAR3 ,
VAR6,
VAR5
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR6;
input VAR5;
VAR8 VAR1 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR9,
VAR4,
VAR7,
VAR2,
VAR3
);
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.behavioral.v | 1,676 | module MODULE1 (
VAR4 ,
VAR17,
VAR15,
VAR11,
VAR9,
VAR1
);
output VAR4 ;
input VAR17;
input VAR15;
input VAR11;
input VAR9;
input VAR1;
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR8 ;
wire VAR6 ;
wire VAR10 ;
wire VAR7;
and VAR14 (VAR6 , VAR11, VAR17, VAR15 );
and VAR12 (VAR10 , VAR9, VAR1 );
or VAR16 (VAR7, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.functional.pp.v | 1,810 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR7 ,
VAR9 ,
VAR13,
VAR10,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR13;
input VAR10;
input VAR3 ;
input VAR1 ;
wire VAR11 ;
wire VAR2;
and VAR4 (VAR11 , VAR9, VAR8, VAR7 );
VAR12 VAR5 (VAR2, VAR11, VAR13, VAR10);
buf VAR14 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a_4.v | 2,295 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR3 ,
VAR2 ,
VAR1,
VAR10
);
output VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR1;
input VAR10;
VAR5 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_rx_pipeline.v | 26,674 | module MODULE1 #(
parameter VAR73 = 128, parameter VAR75 = "VAR20", parameter VAR37 = 1,
parameter VAR32 = (VAR73 == 128) ? 2 : 1, parameter VAR16 = VAR73 / 8 ) (
output reg [VAR73-1:0] VAR27, output reg VAR82, input VAR15, output [VAR16-1:0] VAR33, output VAR70, output reg [21:0] VAR55,
input [VAR73-1:0] VAR81, input ... | mit |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/new/Small Program Top.v | 1,976 | module MODULE1(
input clk,
input rst,
input VAR12,
input VAR22,
input VAR1,
input VAR4,
output VAR7,
output VAR23,
output [11:0]VAR3,
output [7:0]VAR13,
output [3:0]sel
);
wire[7:0] VAR39;
wire[7:0] VAR16;
wire[7:0] VAR35;
wire[15:0] VAR41;
wire[1:0] VAR30;
wire[7:0] VAR32;
wire[9:0] VAR18;
wire[9:0] VAR9;
wire VAR5;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.blackbox.v | 1,219 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/pipeline/registers/ex_mem_reg.v | 4,728 | module MODULE1
parameter VAR14 = 20,
parameter VAR10 = 32,
parameter VAR6 = 32,
parameter VAR31 = 5
)
(
input clk,
input VAR27,
input en,
input VAR11,
input VAR21,
input VAR12,
input [VAR10-1:0] VAR9,
input [VAR10-1:0] VAR29, input [VAR10-1:0] VAR28,
input [VAR31-1:0] VAR7,
input [VAR31-1:0] VAR13,
input VAR3,
input VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.symbol.v | 1,186 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
cpulabs/mist1032isa | src/core/l1_data/l1_data_cache.v | 18,496 | module MODULE1(
input wire VAR83,
input wire VAR10,
input wire VAR9,
input wire VAR15,
input wire VAR29,
input wire VAR87,
input wire [31:0] VAR112,
input wire VAR7,
output wire VAR71,
input wire [1:0] VAR51,
input wire [3:0] VAR68,
input wire VAR55,
input wire [13:0] VAR84,
input wire [1:0] VAR113,
input wire [2:0] VA... | bsd-2-clause |
linuxbest/lzs | jhash/rtl/verilog/jhash.v | 2,825 | module MODULE1(
VAR12, VAR3, VAR11, VAR13,
VAR9, rst, VAR15, VAR4, VAR2, clk, VAR17
);
input VAR17; input clk; input [63:0] VAR2; input VAR4; input VAR15; input rst; input VAR9;
output VAR13; output [31:0] VAR11; output VAR3; output VAR12;
wire VAR18; wire [31:0] VAR5; wire [31:0] VAR8; wire [31:0] VAR7; wire VAR6; wir... | gpl-2.0 |
misomosi/FM-Synthesizer | Digital Synth/ComponentLibrary.cydsn/Key_Matrix_Driver_v1_0/Key_Matrix_Driver_v1_0.v | 4,156 | module MODULE1 (
output VAR4,
output [3:0] VAR8,
output reg [31:0] VAR6,
input VAR3,
input [7:0] VAR5
);
parameter VAR7 = 0;
generate
if (VAR7 == 1)
begin
reg [1:0] VAR2; reg VAR1;
assign VAR8 = ~(4'b1000 >> VAR2);
assign VAR4 = (VAR2 == 2'b00) && VAR1;
always @ (posedge VAR3)
begin
VAR2 <= VAR2 + 1;
VAR6 <= VAR6; case... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_To_Electrical_Position.v | 1,763 | module MODULE1
(
VAR1,
VAR6
);
input signed [17:0] VAR1; output signed [17:0] VAR6;
wire signed [35:0] VAR5; wire signed [17:0] VAR7; wire signed [17:0] VAR4;
assign VAR5 = {{2{VAR1[17]}}, {VAR1, 16'b0000000000000000}};
assign VAR7 = VAR5[33:16];
VAR9 VAR8 (.VAR3(VAR7), .VAR2(VAR4) );
assign VAR6 = VAR4;
endmodule | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/ram_1port_fast.v | 1,429 | module MODULE1 #(parameter VAR15 = 64, VAR10=128, VAR19=0)(
input clk
,input reset
,input VAR4
,output VAR20
,input VAR28
,input [VAR5(VAR10)-1:0] VAR14
,input [VAR15-1:0] VAR2
,output VAR18
,input VAR16
,output [VAR15-1:0] VAR26
);
logic [VAR15-1:0] VAR8;
VAR1
VAR22 (
.VAR13 (VAR14)
,.VAR12 (VAR4 & VAR28)
,.VAR17 (VAR... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_port_monitor_128.v | 8,408 | module MODULE1 #(
parameter VAR5 = 9'd128,
parameter VAR30 = 512,
parameter VAR34 = (VAR30 - 4),
parameter VAR20 = VAR25((2**VAR25(VAR30))+1),
parameter VAR44 = 1
)
(
input VAR24,
input VAR14,
input [VAR5:0] VAR31, input VAR19, output VAR41,
output [VAR5-1:0] VAR21, output VAR23, input [VAR20-1:0] VAR7,
output VAR36, i... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_asfifo_xilinx.v | 1,586 | module MODULE1
VAR30 = 4)
(output wire [8:0] VAR23,
output wire VAR21,
input wire VAR28,
input wire VAR1,
input wire [8:0] VAR14,
output wire VAR32,
input wire VAR8,
input wire VAR19,
input wire VAR26);
VAR4 #(
.VAR18(9),
.VAR15("VAR3")
) VAR5 (
.VAR9(),
.VAR11(),
.VAR16(VAR23[7:0]),
.VAR24(VAR23[8]),
.VAR13(VAR21),
.V... | lgpl-3.0 |
maijohnson/comp3601_blue_15s2 | AudioController/bcdtoseg.v | 1,585 | module MODULE1(VAR7, VAR10, VAR2, VAR9, VAR8, VAR5, VAR4,
VAR14, VAR3, VAR6, VAR17, VAR11, VAR1, VAR13, VAR16);
input VAR7, VAR10, VAR2, VAR9, VAR8, VAR5, VAR4;
output VAR14, VAR3, VAR6, VAR17, VAR11, VAR1, VAR13, VAR16;
wire [3:0] VAR15;
reg [6:0] VAR12;
assign VAR15[3] = VAR2;
assign VAR15[2] = VAR9;
assign VAR15[1] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.pp.blackbox.v | 1,240 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR5,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR5;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon.behavioral.pp.v | 2,730 | module MODULE1 (
VAR23,
VAR1 ,
VAR20 ,
VAR6 ,
VAR10 ,
VAR9 ,
VAR11 ,
VAR14 ,
VAR4
);
output VAR23;
output VAR1 ;
input VAR20 ;
input VAR6 ;
input VAR10 ;
input VAR9 ;
input VAR11 ;
input VAR14 ;
input VAR4 ;
wire VAR24 ;
wire VAR8 ;
wire VAR25 ;
wire VAR5 ;
wire VAR17 ;
wire VAR7 ;
wire VAR3;
xor VAR19 (VAR24 , VAR20, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.functional.pp.v | 1,775 | module MODULE1 (
VAR1,
VAR3,
VAR5 ,
VAR7 ,
VAR9
);
input VAR1;
input VAR3;
output VAR5 ;
input VAR7 ;
input VAR9;
wire VAR2 ;
wire VAR8;
VAR11 VAR10 (VAR2 , VAR7, VAR1, VAR3 );
VAR11 VAR4 (VAR8, VAR9, VAR1, VAR3 );
notif0 VAR6 (VAR5 , VAR2, VAR8);
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/app/BMD_128_TX_ENGINE.v | 39,741 | module MODULE1 (
clk,
VAR79,
VAR80,
VAR76,
VAR105,
VAR109,
VAR128,
VAR56,
VAR54,
VAR58,
VAR129,
VAR32,
VAR110,
VAR51,
VAR26,
VAR91,
VAR95,
VAR10,
VAR36,
VAR17,
VAR126,
VAR88,
VAR119,
VAR75,
VAR59,
VAR77,
VAR35,
VAR64,
VAR113,
VAR19,
VAR86,
VAR116,
VAR73,
VAR83,
VAR37,
VAR65,
VAR34,
VAR24,
VAR90,
VAR25,
VAR87,
VAR1,
VAR... | gpl-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/small_fifo.v | 2,662 | module MODULE1
parameter VAR14 = 3,
parameter VAR4 = 2**VAR14 - 1
)
(
input [VAR1-1:0] din, input VAR7,
input VAR13,
output reg [VAR1-1:0] dout, output VAR6,
output VAR9,
output VAR10,
output VAR11,
output [VAR14:0] VAR8,
input reset,
input clk
);
parameter VAR3 = 2 ** VAR14;
reg [VAR1-1:0] VAR5 [VAR3 - 1 : 0];
reg [VA... | lgpl-2.1 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/driver_7segment.v | 7,970 | module MODULE1 (
VAR34, VAR1, VAR44,
VAR4,
VAR11,
VAR47, VAR6, VAR25, VAR38, VAR27, VAR40 );
output [15:0] VAR34;
output [7:0] VAR1,VAR44,VAR4,VAR11;
input VAR47; input [13:0] VAR6; input [15:0] VAR25; input VAR38; input [1:0] VAR27; input VAR40;
parameter [14:0] VAR50 = 15'h0090;
parameter VAR17 = 2;
parameter [VAR17-... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a_1.v | 2,444 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR11 ,
VAR12 ,
VAR3 ,
VAR4 ,
VAR6,
VAR5,
VAR1 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR11 ;
input VAR12 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR1 ;
input VAR8 ;
VAR10 VAR2 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(... | apache-2.0 |
rohit91/HDMI2USB | hdl/edid/edid_master_slave_hack.v | 5,582 | module MODULE1(
input VAR24,
input clk,
inout VAR4,
output VAR6,
input VAR14,
inout VAR16,
input VAR31,
output reg VAR22,
output [7:0] VAR19,
output VAR21,
output reg VAR9,
input VAR28
);
reg VAR5;
wire [7:0] VAR30;
reg [6:0] counter;
reg [6:0] VAR2, VAR10;
reg [7:0] VAR25;
reg VAR17,VAR13;
wire VAR3,VAR26;
assign VAR3... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync.v | 1,950 | module MODULE1
,parameter VAR9(VAR12)
,parameter VAR9(VAR18)
, parameter VAR20 = "VAR1"
)
(input VAR23
, input VAR5
, input VAR19
, input VAR17
, input [VAR12-1:0] VAR10
, input [VAR18-1:0] VAR15
, input VAR21
, input [VAR12-1:0] VAR3
, output logic [VAR18-1:0] VAR16
, output logic VAR11
);
logic [VAR12-1:0] VAR13;
log... | bsd-3-clause |
toyoshim/tvcl | sample/LED.v | 1,026 | module MODULE1(
clk,
VAR4,
VAR2,
VAR9,
VAR6,
VAR8,
VAR13,
VAR1,
VAR7,
VAR10);
input clk;
input VAR4;
output VAR2;
output VAR9;
output VAR6;
output VAR8;
output VAR13;
output VAR1;
output VAR7;
output VAR10;
reg [4:0] VAR11;
assign VAR10 = VAR11[0] & VAR4;
always @ (posedge clk or negedge VAR4) begin
if (!VAR4) begin
VA... | bsd-3-clause |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/hdl/bd_wrapper.v | 6,819 | module MODULE1
(VAR47,
VAR10,
VAR54,
VAR40,
VAR32,
VAR52,
VAR7,
VAR25,
VAR19,
VAR58,
VAR5,
VAR36,
VAR39,
VAR20,
VAR60,
VAR34,
VAR43,
VAR23,
VAR22,
VAR3,
VAR14,
VAR35,
VAR51,
VAR4,
VAR28,
VAR50,
VAR57,
VAR2,
VAR31,
VAR53,
VAR24,
VAR48,
VAR46,
VAR29,
VAR45,
VAR15,
VAR44,
VAR9,
VAR18,
VAR37,
VAR13,
VAR41,
VAR1,
VAR56,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.v | 2,316 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR1,
VAR5 ,
VAR8 ,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR1;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
VAR4 VAR7 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR9 ,
VAR1
);
output VA... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Video_Clipper.v | 9,897 | module MODULE1 (
clk,
reset,
VAR27,
VAR39,
VAR31,
VAR1,
VAR37,
VAR14,
VAR7,
VAR32,
VAR16,
VAR34,
VAR41,
VAR13
);
parameter VAR23 = 15; parameter VAR40 = 0;
parameter VAR3 = 720; parameter VAR42 = 244; parameter VAR45 = 9; parameter VAR30 = 7;
parameter VAR26 = 40;
parameter VAR43 = 40;
parameter VAR28 = 2;
parameter VA... | gpl-2.0 |
asicguy/gplgpu | hdl/dlp/dlp_store.v | 10,743 | module MODULE1
(
input VAR42, input VAR18, input VAR46, input VAR32, input [(VAR30*8)-1:0] VAR34, input VAR31, input VAR36, input VAR21, input [3:0] VAR17,
output reg [1:0] VAR43, output [1:0] VAR49,
output VAR16, output [31:0] VAR51, output [31:0] VAR10, output VAR35, output [31:0] VAR27, output [3:0] VAR19, output [7... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/dma_if.v | 10,174 | module MODULE1 # (
parameter VAR6 = 128,
parameter VAR18 = 36,
parameter VAR73 = 64
)
(
input VAR3,
input VAR25,
input [2:0] VAR28,
input [2:0] VAR27,
input VAR97,
output [7:0] VAR19,
input [44:0] VAR92,
output VAR16,
output [6:0] VAR69,
output [18:0] VAR1,
input VAR20,
output [6:0] VAR43,
input [18:0] VAR57,
output VA... | gpl-3.0 |
which0326/ca_project2 | code/Data_Memory.v | 1,589 | module MODULE1
(
VAR12,
VAR13,
VAR10,
VAR3,
VAR15,
VAR5,
VAR11,
VAR9
);
input VAR12;
input VAR13;
input [31:0] VAR10;
input [255:0] VAR3;
input VAR15;
input VAR5;
output VAR11;
output [255:0] VAR9;
reg [255:0] memory [0:511]; reg [3:0] VAR6;
reg ack;
reg VAR14;
reg [255:0] VAR8;
wire [26:0] addr;
parameter VAR1 = 3'h0,... | cc0-1.0 |
mda-ut/AquaTux | fpga/fpga_hw/top_level/motor_controller/motor_controller.v | 1,230 | module MODULE2 (input clk, input VAR8, input VAR11, input [15:0] period, input [15:0] VAR4, output [3:0] out);
reg [VAR1-1:0] VAR5 = 0;
reg VAR10;
always @(posedge clk)
begin
if (VAR5 == period)
VAR5 <= 0;
end
else
VAR5 <= VAR5 + 1;
VAR10 <= (VAR11 && VAR5 < VAR4) ? ~VAR8 : VAR8;
end
MODULE1 MODULE1(clk, VAR10, VAR11, ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR12 ,
VAR11 ,
VAR16 ,
VAR13 ,
VAR8 ,
VAR4,
VAR2,
VAR9 ,
VAR6
);
output VAR12 ;
input VAR11 ;
input VAR16 ;
input VAR13 ;
input VAR8 ;
input VAR4;
input VAR2;
input VAR9 ;
input VAR6 ;
wire VAR5 ;
wire VAR3;
VAR10 VAR17 (VAR3, VAR16, VAR13, VAR8 );
VAR7 VAR1 VAR15 (VAR5 , VAR3, VAR11, , VAR4, VAR2);
b... | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/forwarding_unit.v | 4,930 | module MODULE2 (
input VAR3,
input VAR7,
input [4:0] VAR6,
input [4:0] VAR15,
input [4:0] VAR19,
input [4:0] VAR1,
input [4:0] VAR10,
input [4:0] VAR9,
output [1:0] VAR8,
output [1:0] VAR18,
output [1:0] VAR11,
output [1:0] VAR13 );
wire [3:0] VAR16, VAR14;
assign VAR8 = VAR16[0] ? 2'b01 : VAR16[2] ? 2'b10 : 2'b00;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.behavioral.pp.v | 2,018 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR8 ,
VAR7 ,
VAR17 ,
VAR15,
VAR6,
VAR4 ,
VAR9
);
output VAR1 ;
input VAR16 ;
input VAR8 ;
input VAR7 ;
input VAR17 ;
input VAR15;
input VAR6;
input VAR4 ;
input VAR9 ;
wire VAR10 ;
wire VAR3 ;
wire VAR5;
nor VAR13 (VAR10 , VAR16, VAR8 );
and VAR11 (VAR3 , VAR10, VAR7, VAR17 );
VAR12 VAR... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/stable_match/stable_match_seq.v | 6,063 | module MODULE1
parameter VAR23 =10,
parameter VAR12 =10,
parameter VAR25 =10,
parameter VAR30 =10
)
(
clk,
rst,
VAR39, VAR33, VAR57,
VAR3,
VAR34
);
function integer VAR15;
input [31:0] VAR21;
reg [31:0] VAR41;
begin
VAR41 = VAR21 - 1;
for (VAR15=0; VAR41>0; VAR15=VAR15+1)
VAR41 = VAR41>>1;
end
endfunction
localparam VA... | gpl-3.0 |
TheMadSocrates/vercpu-project | rtl/core/ff_d.v | 1,332 | module MODULE1 #(parameter VAR5=8) (
input wire [VAR5 - 1 : 0] VAR4,
input wire en,
input wire clk,
input wire VAR1,
output wire [VAR5 - 1 : 0] VAR3
);
reg [VAR5 - 1 : 0] VAR2;
assign VAR3 = VAR2;
always @(posedge clk) begin
if(VAR1)
VAR2 <= {VAR5{1'b0}};
end
else if(en)
VAR2 <= VAR4;
end
endmodule | gpl-3.0 |
bbrown1867/ObjectTracking | hw/common/Sdram_Control_4Port/Sdram_PLL.v | 17,077 | module MODULE1 (
VAR11,
VAR25,
VAR28,
VAR90);
input VAR11;
output VAR25;
output VAR28;
output VAR90;
wire [5:0] VAR35;
wire [0:0] VAR44 = 1'h0;
wire [2:2] VAR92 = VAR35[2:2];
wire [1:1] VAR113 = VAR35[1:1];
wire [0:0] VAR6 = VAR35[0:0];
wire VAR25 = VAR6;
wire VAR28 = VAR113;
wire VAR90 = VAR92;
wire VAR68 = VAR11;
wir... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.behavioral.pp.v | 1,098 | module MODULE1( VAR5, VAR1, VAR4 );
input VAR5;
inout VAR1, VAR4;
VAR2 VAR6(.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR3(.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.pp.symbol.v | 1,375 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR7,
input VAR5 ,
input VAR1 ,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/localram.v | 52,818 | module MODULE1(clk, addr, VAR14, VAR45, VAR24, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR14;
output [31:0] VAR45;
input [3:0] VAR24;
input en;
input reset;
VAR10 VAR9(
.VAR54 (VAR45[3:0]),
.VAR13 (addr[13:2]),
.VAR39 (clk),
.VAR64 (VAR14[3:0]),
.VAR59 (en),
.VAR25 (reset),
.VAR29 (VAR24[0])
);
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.pp.symbol.v | 1,402 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR8 ,
input VAR1 ,
input VAR6 ,
output VAR10 ,
input VAR4 ,
input VAR9,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v | 6,986 | module MODULE1 (
VAR9,
VAR32, VAR6, VAR11, VAR1, VAR30, VAR26 );
output [15:0] VAR9;
input VAR32; input [13:0] VAR6; input [15:0] VAR11; input VAR1; input [1:0] VAR30; input VAR26;
parameter [14:0] VAR3 = 15'h0190;
parameter VAR16 = 3;
parameter [VAR16-1:0] VAR34 = 'h0,
VAR22 = 'h2,
VAR20 = 'h4,
VAR36 = 'h6;
parameter ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b_2.v | 2,300 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR10 ,
VAR4,
VAR7,
VAR11 ,
VAR8
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR10 ;
input VAR4;
input VAR7;
input VAR11 ;
input VAR8 ;
VAR3 VAR2 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.... | apache-2.0 |
ellore/processor | ram.v | 3,980 | module MODULE1 (addr, clk, din, dout, VAR1, VAR2);
input [7 : 0] din;
input [15: 0] addr;
input clk, VAR1;
output [7 : 0] dout;
output[7:0] VAR2;
reg [7:0] memory[65535:0];
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.behavioral.pp.v | 2,207 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR14 ,
VAR7 ,
VAR8 ,
VAR17,
VAR2,
VAR5 ,
VAR12
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR14 ;
input VAR7 ;
input VAR8 ;
input VAR17;
input VAR2;
input VAR5 ;
input VAR12 ;
wire VAR6 ;
wire VAR11 ;
wire VAR18 ;
wire VAR13;
and VAR10 (VAR6 , VAR14, VAR7 );
and VAR19 (VAR11... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_axis_dma_tx.v | 8,307 | module MODULE1 (
VAR53,
VAR56,
VAR52,
VAR31,
VAR57,
VAR14,
VAR59,
VAR58,
VAR22,
VAR44,
VAR25,
VAR41,
VAR42,
VAR10);
parameter VAR23 = 64;
localparam VAR17 = VAR23 - 1;
localparam VAR3 = 6'd3;
localparam VAR8 = 6'd60;
localparam VAR1 = 6'd40;
localparam VAR48 = 6'd50;
input VAR53;
input VAR56;
output VAR52;
input VAR31;... | gpl-3.0 |
rohit21122012/CPU | MU/Register32.v | 2,970 | module MODULE1(
input [31:0] VAR17;
input clk,reset;
input VAR3;
input VAR12;
output [31:0] VAR25;
reg [31:0] VAR19;
VAR18 VAR27(VAR17[0],clk, reset,VAR3, VAR12, VAR25[0]);
VAR18 VAR37(VAR17[1],clk, reset,VAR3, VAR12, VAR25[1]);
VAR18 VAR16(VAR17[2],clk, reset,VAR3, VAR12, VAR25[2]);
VAR18 VAR20(VAR17[3],clk, reset,VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba_4.v | 2,316 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR7,
VAR6,
VAR3,
VAR2 ,
VAR10
);
output VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR7;
input VAR6;
input VAR3;
input VAR2 ;
input VAR10 ;
VAR4 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v | 27,685 | module MODULE5 (
clk,
reset,
VAR129,
VAR98,
VAR108,
VAR56,
VAR209
);
parameter VAR168 = 18;
parameter VAR102 = 42;
parameter VAR177 = 21;
localparam VAR201 = 43;
input clk;
input reset;
input VAR129;
input VAR98;
input [VAR168-1:0] VAR108; output VAR56;
output [VAR168-1:0] VAR209;
localparam VAR116 = 18; localparam VAR... | mit |
oceanborn-mx/sirius | src.verilog/Multiplicacion_Matricial_Hipercubica/Multiplicacion_Matricial_Hipercubica/src/fsm_ctrol.v | 1,440 | module MODULE1 (
input VAR5, input VAR1, input VAR8, output reg[7:0] VAR4, output reg[7:0] VAR11, output reg[7:0] VAR6, output reg[7:0] VAR10, output reg VAR7 );
reg[2:0] VAR9,VAR2;
always @ *
begin : VAR3
case (VAR9)
3'b000 : begin if (VAR8)
VAR2 = 3'b001;
end
else
VAR2 = VAR9;
VAR4 = 8'b00001111;
VAR11 = 8'b00001111;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.functional.v | 1,974 | module MODULE1 (
VAR2,
VAR1,
VAR12 ,
VAR13 ,
VAR10 ,
VAR9 ,
VAR6 ,
VAR5
);
input VAR2;
input VAR1;
output VAR12 ;
input VAR13 ;
input VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
wire VAR6 VAR8 ;
wire VAR11 ;
wire VAR15;
and VAR7 (VAR8 , VAR13, VAR10 );
nor VAR4 (VAR11 , VAR9, VAR6, VAR5, VAR8 );
VAR3 VAR14 (VAR15, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.behavioral.pp.v | 2,780 | module MODULE1 (
VAR14 ,
VAR9 ,
VAR3 ,
VAR22 ,
VAR4 ,
VAR17 ,
VAR29 ,
VAR6
);
input VAR14 ;
input VAR9 ;
output VAR3 ;
input VAR22 ;
input VAR4 ;
input VAR17 ;
input VAR29 ;
input VAR6;
wire VAR21 ;
wire VAR28 ;
wire VAR10 ;
reg VAR24 ;
wire VAR5 ;
wire VAR11 ;
wire VAR26 ;
wire VAR16;
wire VAR20 ;
wire VAR19 ;
wire VA... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_phy_10g_fifo.v | 22,034 | module MODULE1 #
(
parameter VAR28 = 64,
parameter VAR86 = (VAR28/32),
parameter VAR61 = VAR28,
parameter VAR98 = (VAR61>8),
parameter VAR164 = (VAR61/8),
parameter VAR153 = 1,
parameter VAR191 = 1,
parameter VAR199 = 64,
parameter VAR26 = 0,
parameter VAR120 = 0,
parameter VAR38 = 0,
parameter VAR171 = 0,
parameter VA... | mit |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/SyncRegister.v | 4,836 | module MODULE2(
VAR7,
VAR11,
VAR6,
VAR18,
VAR17,
VAR1,
VAR13
);
parameter VAR4 = 1 ;
parameter VAR16 = { VAR4 {1'b0 }} ;
input VAR7 ;
input VAR11 ;
input VAR18 ;
input [VAR4 -1 : 0] VAR1 ;
output VAR17 ;
input VAR6 ;
output [VAR4 -1 : 0] VAR13 ;
wire VAR8 ;
reg [VAR4 -1 : 0] VAR5 ;
reg [VAR4 -1 : 0] VAR13 ;
VAR19 sync(... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_speed/axi_mc_speed.v | 8,358 | module MODULE1
(
input [2:0] VAR16,
output [2:0] VAR51,
output [31:0] VAR33,
output VAR26,
input [1:0] VAR71,
input VAR58,
input VAR82,
input VAR98,
input VAR91,
input [31:0] VAR54,
output VAR3,
input VAR104,
input [31:0] VAR41,
input [ 3:0] VAR24,
output VAR74,
output VAR75,
output [ 1:0] VAR39,
input VAR112,
input VA... | gpl-3.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/pcie_bram_top_s6.v | 5,421 | module MODULE1 #(
parameter VAR11 = 0,
parameter VAR39 = 31,
parameter VAR22 = 20,
parameter VAR21 = 1,
parameter VAR13 = 2,
parameter VAR28 = 1,
parameter VAR25 = 'h1FFF,
parameter VAR46 = 1,
parameter VAR5 = 2,
parameter VAR1 = 1
) (
input VAR15,
input VAR2,
input VAR9,
input [11:0] VAR19,
input [35:0] VAR41,
input V... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/jtag_lm32.v | 4,955 | module MODULE1 (
input VAR28,
input VAR29,
output VAR4,
input VAR31,
input VAR10,
input VAR38,
input VAR32,
input VAR18,
input VAR24,
output VAR12,
input [7:0] VAR13,
input [2:0] VAR14,
output [7:0] VAR15,
output [2:0] VAR1
);
wire [9:0] VAR11;
VAR3 VAR20 (
.VAR25(VAR28),
.VAR26(VAR38),
.VAR7(VAR8),
.VAR9(VAR29),
.VAR2... | lgpl-3.0 |
securelyfitz/WTFpga | extras/stopwatch.v | 3,279 | module MODULE4 (
input VAR39,
input VAR10, VAR2, VAR5, VAR15,
output VAR8, VAR11, VAR46, VAR25, VAR24,
output VAR3, VAR12, VAR9, VAR17, VAR7, VAR20, VAR38, VAR47,
output VAR42, VAR28, VAR37, VAR43, VAR26, VAR4, VAR36, VAR23
);
wire [7:0] VAR27, VAR40;
reg [7:0] VAR18 = 0, VAR31 = 0;
reg [7:0] VAR44 = 0, VAR1 = 0;
reg [... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_30.v | 7,066 | module MODULE1 (
VAR9,
VAR15,
VAR68,
VAR52,
VAR6,
VAR46,
VAR20,
VAR12,
VAR43,
VAR53,
VAR31,
VAR33,
VAR57,
VAR56,
VAR19,
VAR16,
VAR24,
VAR42,
VAR54,
VAR17,
VAR59
)
;
output [ 12: 0] VAR68;
output [ 2: 0] VAR52;
output VAR6;
output [ 0: 0] VAR46;
inout [ 0: 0] VAR20;
inout [ 0: 0] VAR12;
output [ 0: 0] VAR43;
output [ 7:... | gpl-3.0 |
csail-csg/recycle-bsv-lib | src/v/EHR_7.v | 3,427 | module MODULE1 (
VAR9,
VAR30,
VAR20,
VAR15,
VAR12,
VAR19,
VAR31,
VAR33,
VAR10,
VAR23,
VAR29,
VAR24,
VAR18,
VAR11,
VAR32,
VAR27,
VAR28,
VAR34,
VAR6,
VAR22,
VAR5,
VAR3,
VAR7
);
parameter VAR21 = 1;
parameter VAR2 = 0;
input VAR9;
input VAR30;
output [VAR21-1:0] VAR20;
input [VAR21-1:0] VAR15;
input VAR12;
output [VAR21-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.behavioral.pp.v | 2,065 | module MODULE1 (
VAR4,
VAR9,
VAR11 ,
VAR10 ,
VAR3 ,
VAR14
);
input VAR4;
input VAR9;
output VAR11 ;
input VAR10 ;
input VAR3 ;
input VAR14;
wire VAR2 ;
wire VAR5 ;
wire VAR16 ;
wire VAR12;
not VAR1 (VAR2 , VAR14 );
or VAR13 (VAR5 , VAR3, VAR10 );
nand VAR8 (VAR16 , VAR2, VAR5 );
VAR6 VAR15 (VAR12, VAR16, VAR4, VAR9);
b... | apache-2.0 |
balanx/laotzu | RTL/asyn_fifo_read.v | 4,317 | module MODULE1 #(
parameter VAR10 = 1, parameter VAR22 = 6,
parameter [VAR22:0] VAR17 = 44,
parameter [VAR22:0] VAR5 = 0,
parameter [VAR22:0] VAR24 = 7
) (
input wire VAR3 ,
input wire VAR13 ,
input wire VAR19 ,
input wire [VAR22:0] VAR15 ,
output reg [VAR22-1:0] VAR16 ,
output reg [VAR22:0] VAR21 ,
output VAR1 ,
outpu... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/wb_artemis_pcie_platform.v | 16,532 | module MODULE1 #(
parameter VAR135 = 10,
parameter VAR132 = 6,
parameter VAR106 = 7
) (
input clk,
input rst,
output VAR2,
input VAR101,
input VAR48,
input [3:0] VAR110,
input [31:0] VAR24,
input VAR42,
output reg VAR14,
output reg [31:0] VAR31,
input [31:0] VAR121,
output [31:0] VAR103,
output reg VAR54,
output VAR10,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.pp.symbol.v | 1,285 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR3 ,
input VAR4 ,
output VAR7 ,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
phisiart/tvm | verilog/tvm_buffer.v | 4,713 | module MODULE1 #(
parameter VAR11 = 256,
parameter VAR18 = 1024,
parameter VAR8 = 10, parameter VAR20 = 8, parameter VAR7 = 2, parameter VAR19 = 3, parameter VAR9 = 8, parameter VAR14 = 2, parameter VAR10 = 3 ) (
input clk,
input rst,
input VAR1, input [VAR19-1:0] VAR2, input VAR21, output VAR3, output [VAR11-1:0] VAR4... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO_EP_MEM_ACCESS.v | 12,293 | module MODULE1 #(
parameter VAR79 = 1
) (
clk,
VAR30,
VAR10, VAR62, VAR25,
VAR68, VAR64, VAR34, VAR69, VAR1
);
input clk;
input VAR30;
input [10:0] VAR10;
input [3:0] VAR62;
output [31:0] VAR25;
input [10:0] VAR68;
input [7:0] VAR64;
input [31:0] VAR34;
input VAR69;
output VAR1;
localparam VAR36 = 3'b000;
localparam VA... | lgpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/sync_fifo.v | 5,636 | module MODULE1 #(
parameter VAR2 = 32, parameter VAR14 = 1024, parameter VAR32 = 0, parameter VAR17 = 2**VAR26(VAR14),
parameter VAR34 = VAR21(VAR17),
parameter VAR7 = VAR21(VAR17+1)
)
(
input VAR6, input VAR23, input [VAR2-1:0] VAR1, input VAR20, output [VAR2-1:0] VAR33, input VAR24, output VAR12, output VAR18, output... | mit |
calee0219/Course | DLAB/Lab08/n2s.v | 4,667 | module MODULE1(
input clk,
input rst,
input [7:0] VAR1,
input VAR22,
output [127:0] VAR6
);
wire [399:0] VAR18, VAR13;
reg [399:0] VAR9, VAR2;
reg [30:0] counter;
wire [3:0] VAR14 [2:0];
wire [7:0] VAR4;
wire VAR11, VAR8;
assign VAR6 = (VAR22)? VAR9:VAR2;
VAR17 VAR3 (
.clk(clk), .VAR12(VAR11), .VAR10(VAR1), .VAR16(8'd1... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_up_clocks_1.v | 10,590 | module MODULE1 (
VAR56,
reset,
VAR37,
VAR73,
VAR50,
VAR7
);
input VAR56;
input reset;
output VAR37;
output VAR73;
output VAR50;
output VAR7;
localparam VAR15 = 1;
localparam VAR91 = 1;
wire [ 2: 0] VAR54;
wire VAR60;
wire VAR100;
assign VAR7 = VAR60;
assign VAR50 = VAR54[0];
assign VAR37 = VAR54[1];
assign VAR73 = VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.behavioral.v | 1,831 | module MODULE1 (
VAR20 ,
VAR7,
VAR19,
VAR2,
VAR5,
VAR16,
VAR12
);
output VAR20 ;
input VAR7;
input VAR19;
input VAR2;
input VAR5;
input VAR16;
input VAR12;
supply1 VAR6;
supply0 VAR11;
supply1 VAR17 ;
supply0 VAR1 ;
wire VAR10 ;
wire VAR8 ;
wire VAR15 ;
wire VAR3;
nand VAR4 (VAR10 , VAR19, VAR7 );
nand VAR18 (VAR8 , VA... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_sysref_gen.v | 3,043 | module MODULE1 (
input VAR6,
input VAR5,
output reg VAR2
);
parameter VAR8 = 128;
localparam VAR3 = VAR8/2 - 1;
reg [ 7:0] counter;
reg VAR7;
reg VAR1;
reg VAR4;
always @(posedge VAR6) begin
VAR7 <= VAR5;
VAR1 <= VAR7;
VAR4 <= VAR1;
end
always @(posedge VAR6) begin
if (VAR4) begin
counter <= (counter < VAR3) ? counter ... | mit |
monotone-RK/FACE | MCSoC-15/8-way/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_memc_flow_vcontrol.v | 15,690 | module MODULE1 #
(
parameter VAR36 = 100,
parameter VAR47 = 4,
parameter VAR20 = 32,
parameter VAR22 = 6,
parameter VAR54 = 4,
parameter VAR23 = "VAR40",
parameter VAR55 = "VAR42"
)
(
input VAR69,
input [9:0] VAR1,
input [3:0] VAR29,
input [5:0] VAR58,
input VAR30,
output reg VAR5,
input VAR68,
input [2:0] VAR24,
input... | mit |
zuloloxi/mecrisp-ice | hx8k/icestorm/uart.v | 4,551 | module MODULE1(
input wire clk,
output wire VAR30
);
localparam VAR1 = (VAR15 / VAR25) - 1;
localparam VAR20 = VAR9(VAR1);
wire [VAR20-1:0] VAR4 = VAR1;
reg [VAR20-1:0] counter;
assign VAR30 = (counter == VAR4);
always @(posedge clk)
counter <= VAR30 ? 0 : (counter + 1);
endmodule
module MODULE4(
input wire clk,
input ... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/rw_manager_ram.v | 1,262 | module MODULE1
(
VAR9,
VAR5,
VAR2,
VAR1, VAR4,
VAR8
);
parameter VAR7=36;
parameter VAR3=8;
input [(VAR7-1):0] VAR9;
input [(VAR3-1):0] VAR5, VAR2;
input VAR1, VAR4;
output reg [(VAR7-1):0] VAR8;
reg [VAR7-1:0] VAR6[2**VAR3-1:0];
always @ (posedge VAR4)
begin
if (VAR1)
VAR6[VAR2] <= VAR9[VAR7-1:0];
VAR8 <= VAR6[VAR5];
... | lgpl-3.0 |
mlab-upenn/pvs | hdl_harness/async_receiver.v | 3,555 | module MODULE1(clk, VAR10, VAR5, VAR4, VAR3, VAR11);
input clk, VAR10;
output VAR5; output [7:0] VAR4;
parameter VAR13 = 50000000; parameter VAR18 = 115200;
output VAR3; output VAR11;
parameter VAR2 = VAR18*8;
parameter VAR19 = 16;
wire [VAR19:0] VAR14 = ((VAR2<<(VAR19-7))+(VAR13>>8))/(VAR13>>7);
reg [VAR19:0] VAR6;
al... | gpl-3.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_sdram_0.v | 23,937 | module MODULE2 (
clk,
rd,
VAR40,
wr,
VAR34,
VAR64,
VAR36,
VAR2,
VAR12,
VAR31
)
;
output VAR64;
output VAR36;
output VAR2;
output VAR12;
output [ 40: 0] VAR31;
input clk;
input rd;
input VAR40;
input wr;
input [ 40: 0] VAR34;
wire VAR64;
wire VAR36;
wire VAR2;
reg [ 1: 0] VAR80;
reg [ 40: 0] VAR15;
reg [ 40: 0] VAR24;
w... | apache-2.0 |
eda-globetrotter/MarcheProcessor | final/src/pipe2.v | 2,351 | module MODULE1(VAR21, VAR6,
VAR19, VAR11,
VAR12, VAR16,
VAR25, VAR2,
VAR15, VAR9,
VAR26, VAR23,
VAR20, VAR10,
VAR13, VAR1,
VAR5, VAR4,
VAR14, VAR18,
VAR17, VAR3,
VAR24, VAR8,
VAR22, VAR7,
clk,
reset);
input [0:4] VAR21;
input [0:1] VAR19;
input VAR12, VAR25;
input [0:20] VAR15;
input [0:15] VAR26;
input VAR20;
input [0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.blackbox.v | 1,459 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR4
);
output VAR3 ;
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR4;
supply1 VAR2;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR11 ;
endmodule | apache-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_malloc_v2.v | 36,831 | module MODULE1 #(
parameter VAR127 = 512,
parameter VAR122 = 64, parameter VAR65 = 1, parameter VAR136 = 24,
parameter VAR116 = 5,
parameter VAR117 = 1,
parameter VAR60 = 0
)
(
input wire clk,
input wire rst,
input wire [15:0] VAR79,
input wire VAR119,
output reg VAR6,
output reg [31:0] VAR139,
output reg VAR73,
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4bb/sky130_fd_sc_hs__nand4bb.behavioral.pp.v | 1,897 | module MODULE1 (
VAR11,
VAR6,
VAR3 ,
VAR2 ,
VAR10 ,
VAR13 ,
VAR9
);
input VAR11;
input VAR6;
output VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR13 ;
input VAR9 ;
wire VAR9 VAR1 ;
wire VAR15 ;
wire VAR14;
nand VAR8 (VAR1 , VAR9, VAR13 );
or VAR7 (VAR15 , VAR10, VAR2, VAR1 );
VAR5 VAR12 (VAR14, VAR15, VAR11, VAR6);
buf VA... | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/ps2_kbd.v | 3,218 | module MODULE1 (
clk,
VAR1,
VAR12,
VAR5,
VAR7,
VAR9,
ready,
VAR3
);
input clk, VAR1; input VAR12, VAR5; input VAR7; output [ 7: 0] VAR9; output ready; output reg VAR3;
reg [ 3: 0] VAR6; reg [ 9: 0] buffer; reg [ 7: 0] VAR2[7:0]; reg [ 2: 0] VAR10, VAR8; reg [ 2: 0] VAR4; integer VAR11; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.pp.symbol.v | 1,225 | module MODULE1 (
input VAR1 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.